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USN 18EC34

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Third Semester B.E. Degree Examination, Feb./Mar. 2022

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Digital System Design

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Time: 3 hrs. Max. Marks: 100

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2. Any revealing of identification, appeal to evaluator and /or equations written eg, 42+8 = 50, will be treated as malpractice.

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Note: Answer any FIVE full questions, choosing ONE full question from each module.

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Module-1
1 a. Define and explain the combinational logic circuit along with block diagram.

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(06 Marks)
b. Develop the canonical minterm and maxterm forms in decimal notation for the following
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Boolean functions:
Important Note : 1. On completing your answers, compulsorily draw diagonal cross lines on the remaining blank pages.

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i) X = f(a, b ,c, d) = ab  cd

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ii) Y = f(a, b, c) = (a  b)(b  c) (08 Marks)
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c. Simplify the following function using K-map method and also construct logic circuit for the
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simplified equation (function).

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Y = f(a, b, c, d) = (0, 1, 2, 4, 5, 6, 8, 9, 10, 12, 13, 14). (06 Marks)
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a. Simplify the following Boolean function by using Q-M method:
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X = f(a, b, c) = (0, 1, 2, 3, 4, 5, 6). (10 Marks)

b. Design a combinational logic circuit for valid single digit BCD data, the output is
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1 whenever a number is greater than 5 appears at the input. -S (05 Marks)

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c. Identify the PI and EPI for the following function:

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M = f(a, b, c, d) =  (1, 2, 3, 5, 7, 11, 12, 13, 14, 15). (05 Marks)

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Module-2
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3 a. Draw and explain the circuit for 3 to 8 decoder. (06 Marks)

b. Design and implement a full adder circuit using logic gates. (08 Marks)
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c. Write a short notes on PLD’s and FPGA.

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(06 Marks)
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4 a. Define MUX and explain 4:1 MUX with the help of logic diagram using gates. (06 Marks)
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b. Explain 4-bit carry look-ahead adder with diagram.

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(08 Marks)
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c. Design and implement 1-bit comparator circuit. (06 Marks)

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Module-3
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5 a. Compare sequential circuit and combinational circuits. (06 Marks)

b. Write a short notes on SR-latch. (06 Marks)
c. Illustrate master-slave J-K flip-flop using NAND Gates. (08 Marks)
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6 a. Distinguish between synchronous and asynchronous counter. (06 Marks)
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b. Explain 4-bit universal shift register along with diagram. (08 Marks)
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c. Explain the working of clocked SR-FF using NAND Gates. (06 Marks)

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Module-4
7 a. Explain Mealy and Moore model with diagrams. (10 Marks)
b. Design and develop Mod-6 synchronous counter using T-FF. (10 Marks)

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8 a. Construct the excitation table, transition table, state table and state diagram for the following

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sequential circuit. (Refer Fig.Q.8(a)). (14 Marks)

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Fig.Q.8(a)

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b. List out the applications of shift registers along with brief explanation. (06 Marks)
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Module-5
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9 a. Explain the operation of serial adder with accumulator. (12 Marks)

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b. Illustrate state assignment rules. (08 Marks)
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10 a. Write a short notes on:

i) Sequential circuit design steps
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ii) BCD to Ex-3 code convertor. (10 Marks)
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b. Explain 4-bit Ring and Johnson counter along with diagram. -S (10 Marks)
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