18EC34
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USN
8
Third Semester B.E. Degree Examination, July/August 2022
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Digital System Design
Time: 3 hrs. Max. Marks: 100
0
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Note: Answer any FIVE full questions, choosing ONE full question from each module.
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01
Module-1
2. Any revealing of identification, appeal to evaluator and /or equations written eg, 42+8 = 50, will be treated as malpractice.
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1 a. Convert the following Boolean function into minterm canonical or maxterm canonical form:
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(i) y x y z (ii) (A B C)(A D) (06 Marks)
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b. Simplify the Boolean function and identify the prime and essential prime implicants:
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(i) f (a , b, c, d) m (1, 5, 7, 8, 9, 10, 11, 13, 15)
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(ii) f (a , b, c, d) M (0, 2, 3, 8, 9, 10, 12, 14) (06 Marks)
Important Note : 1. On completing your answers, compulsorily draw diagonal cross lines on the remaining blank pages.
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c. Simplify the given Boolean function using Quine-Mc Cluskey method.
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f (a , b, c, d) m (0, 1, 2, 3, 6, 7, 8, 9, 14, 15) (08 Marks)
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OR
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2 a. Design a combinational logic circuit that has three input variables and produces a logic 1
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output when more than one input variables are logic 1. (06 Marks)
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b. Simplify the following Boolean function using K-map.
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(i) f(w,x,y,z) = π(2, 3, 8, 9, 10, 11, 12, 13, 14, 15)
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m
(ii) f(w,x,y,z) = m (6, 7, 9, 10, 13) + d (1, 4, 5, 11, 15) (06 Marks)
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8p
c. Simplify the given Boolean function using Quine-Mc Clusky method.
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f ( w , x , y, z) m(1, 3, 13, 15) d(8, 9, 10, 11) (08 Marks)
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Module-2
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3 a. Design a combinational circuit using 3 : 8 decoder (IC – 74138) that generates a logic 1
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output when majority of 4 inputs are true. (06 Marks)
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b. Explain 4-bit carry look ahead adder with neat diagram.
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(08 Marks)
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c. Implement a full adder using PAL. (06 Marks)
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OR
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4 a. Implement f ( w , x , y, z) m(0, 1, 2, 4, 5, 7, 8, 9, 12, 13) using 8 : 1 MUX with w,x,y as select
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lines. (06 Marks)
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b. Design 2-bit magnitude comparator. (08 Marks)
SA
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c. Explain the Basic Architecture of a Xilinx XCR3064XL CPLD. (06 Marks)
Module-3
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5 a. Explain the working of Master Slave JK Flip-Flop with function table and timing diagram.
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(08 Marks)
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b. Differentiate between Flip Flops and Latches. (04 Marks)
c. Design an universal shift Register using positive edge triggered DFF having the behavior as
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specified.
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Mode Operation
00 Hold
01 Shift right
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10 Shift left
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11 Parallel load
(08 Marks)
1 of 3
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SA
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OR
6 a. Explain positive edge Triggered D Flip Flop with the help of circuit diagram and waveform.
(08 Marks)
8
b. Obtain the characteristic equation for the following Flip Flop (i) J.K. (ii) S.R. (06 Marks)
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c. Design a mod-8 asynchronous upcounter using negative edge triggered JK FF. (06 Marks)
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Module-4
7 a. Design a synchronous mod-6 counter using clocked JK Flip Flop for the sequence
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01
0–2–3–6–5–1 (08 Marks)
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b. Distinguish between Moore and Melay model with necessary block diagram. (06 Marks)
c. Analyze the following synchronous circuit. (Refer Fig. Q7 (c))
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02
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-2
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09
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A
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U
VT
Fig. Q7 (c) m (06 Marks)
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8p
A
OR
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a. Design a synchronous mod-6 counter using clocked T-Flip Flop for the sequence,
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8 -S
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0 – 2 – 3 – 6 – 5 – 1. (06 Marks)
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b. Draw the state diagram, for the sequential circuit shown. (Refer Fig. Q8 (b))
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A
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22
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20
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A
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Fig. Q8 (b) (06 Marks)
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2 of 3
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SA
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c. Analyze the given synchronous sequential circuit. (Refer Fig. Q8 (c))
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0 :4
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2
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Fig. Q8 (c) (08 Marks)
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Module-5
9 a. Design a Mealy type sequence detector to detect a serial input sequence of 101. (08 Marks)
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b. List the guidelines for construction of state graphs. (06 Marks)
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c. With the help of neat block diagram, explain serial adder with accumulator.
U
(06 Marks)
VT
OR
m
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10 a. Design a Moore type sequence detector to detect a serial input sequence of 101. (08 Marks)
8p
b. Construct Moore and Mealy state diagram, that will detect input sequence 10110, when
A
input pattern is detected, z is asserted high. Give state diagrams for each state. (06 Marks)
A
:3
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c. With the help of neat block diagram, explain parallel binary divider. (06 Marks)
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31
*****
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20
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3 of 3
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