18EC34

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Third Semester B.E. Degree Examination, July/August 2021
Digital System Design

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Time: 3 hrs. Max. Marks: 100

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Note: Answer any FIVE full questions.
2. Any revealing of identification, appeal to evaluator and /or equations written eg, 42+8 = 50, will be treated as malpractice.

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1 a. Define combinational logic circuit and place the following equation into the proper

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canonical form:

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P = f(a, b, c) = ab + ac + bc (04 Marks)

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b. Obtain minimal expression using k-map for the following incompletely specified function:
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F(a, b, c, d) = m(0, 1, 4, 6, 7, 9, 15) + d(3, 5, 11, 13) and draw the circuit diagram using
Important Note : 1. On completing your answers, compulsorily draw diagonal cross lines on the remaining blank pages.

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basic gates. (06 Marks)

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c. Minimize the expression using Quine Mecluskey method.
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Y  ABC D  ABCD  ABC D  ABCD  A BCD  A B C D (10 Marks)

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2 a. Place the following equations into the proper canonical form:

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i) G = f(w, x, y, z) = wx  y z
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ii) T = f(a, b, c) = (a  b) (b  c) am (04 Marks)

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b. Obtain minimal logical expression for the given maxterm expression using K-map
f(a, b, c, d) = M (0, 1, 4, 5, 6, 7, 9, 14) . d(13, 15). (06 Marks)
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c. Obtain all the prime implicants of the following Boolean function using Quine-Meckluskey
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f(a, b, c, d) = (0, 2, 3, 5, 8, 10, 11). Verify the result using K map technique. (10 Marks)
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3 a. Draw the circuit for 3 to 8 decoder and explain. (08 Marks)

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b. Implement the following Boolean function using 4:1 multiplexer.

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F[A, B, C, D] = m (0, 1, 2, 4, 6, 9, 12, 14). (06 Marks)

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c. A combinational circuit is defined by the functions F1 = m (3, 5, 7), F2 = m (4, 5, 7).

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Implement the circuit with a programmable logic array having 3 inputs, 3 product terms and
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two outputs. (06 Marks)

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4 a. Draw the key pad interfacing diagram to a digital system using 10-line decimal to BCD
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encoder and explain.

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(06 Marks)
b. Explain Look-Ahead carry adder with neat diagram and relevant expression.
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(06 Marks)
c. Design 2-bit comparator using gates.
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(08 Marks)
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5 a. Explain the operation of a switch debouncer using S-R. Latch with the help of circuit and
waveforms. (06 Marks)
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b. Find characteristic equations for S-R and T. Flip flops with the help of function tables and
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explain. (06 Marks)

c. Explain the working principle of 4-bit synchronous binary counts. (08 Marks)
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6 a. Draw the logic diagram, functional table and timing diagram of master-slave JK flip flop
and explain briefly. (10 Marks)
b. Explain four bit binary ripple counter with logic and timing diagram. (10 Marks)

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7 a. Design mod-6 synchronous counter by using JK flip-flop, with excitation table. (10 Marks)

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b. Draw and explain Mealy and Moore sequential circuit model and compare mealy and Moore

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circuit models. (10 Marks)

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8 a. Design a Mod-6 synchronous counter using clocked T Flip-Flop. (10 Marks)

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b. Construct the transition table, state table and state diagram for the sequential circuit shown
in Fig.Q.8(b). (10 Marks)

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Fig.Q.8(b)
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9 a. Design and draw Mealy model of sequential detector circuit to detect the pattern 101.
(10 Marks)
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b. Draw the block diagram of serial adder with accumulator and explain its working operation.
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10 a. State the guidelines for construction of state graph. (06 Marks)

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b. Draw the block diagram of binary multiplier and explain its working principle. (08 Marks)
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c. Draw and explain the operation of FPGA implementation of a parallel adder with
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accumulator. (06 Marks)

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