UNIT-4

ARM PROCESSOR: Advanced RISC Machine (ARM) Processor is considered to be a

family of Central Processing Units that are used in music players, smartphones, wearables,
tablets, and other consumer electronic devices.

 ARM uses Reduced Instruction Set Computing Architecture (RISC).

 ARM works by executing single instruction per cycle.
 Performance can be optimized by a Software-based approach.
 ARM processors require fewer registers, but they require more memory.
 Execution is faster in ARM Processes .

Features of ARM Processor

 Multiprocessing System
 Tightly Coupled Memory
 Memory Management
 Thumb-2 Technology
 One-Cycle Execution Time
 Pipelining
 A large number of Registers
 Load store instructions


ARM Architecture:

The ARM7 TDMI processor has two operating states

1) ARM

32-bit word aligned ARM instructions are executed in this state.

2) Thumb

16-bit, half word aligned Thumb instructions are executed in this state,
In Thumb state the program counter uses bit 1 to select between alternate half words.
 A[31:0]

Address Register Address

Incrementer
PC bus

PC

REGISTER
BANK
ALU bus

Control Lines
INSTRUCCTION
DECODER
Multiplier
A bus

B bus

SHIFT

A.L.U.
Instruction Reg.

Thumb to
ARM
Write Data Reg. Read Data Reg.
translator

D[31:0]
Von Neumann architecture

 32-bit data bus it involves moving information to and from the system's RAM or the
CPU.

 32 bit address allows the CPU to send the address to RAM, and the data bus allows the
actual data transfer to the CPU. The term bus itself refers to the connection between the
two devices that allows them to communicate.

 In line barrel shifter used to shift the contents of registers, allowing for efficient data
manipulation. For example, in the ARM architecture, the barrel shifter is used to perform
shift and rotate operations on the contents of registers.

 37 (32-bit) registers

 Instruction decoder and control unit: The Instruction Decoder is a CPU component that
decodes and interprets the contents of the Instruction Register, i.e. its splits whole
instruction into fields for the Control Unit to interpret. The Instruction decoder is often
considered to be a part of the Control Unit.

 Incrementer is responsible for upgrading the address register contents before the core
reads or writes the next register value from memory location
Register Organization pf ARM Processor:

Basically there are two types of registers – General purpose registers and Special purpose
registers. General-purpose registers hold either data or an address. The letter r is prefixed to the
register number to identify them. For example, the label r4 is assigned to register 4.
Figure depicts the active registers that are available in user mode, which is a protected state that
is often utilized for running programs. There are seven various modes that the CPU may work in,
which we shall go through momentarily. The registers in this example are all 32 bits in size. Up
to 18 active registers are available: 16 data registers and 2 processor status registers. The data
registers are labeled r0 through r15 by the programmer. The ARM processor contains three
registers: r13, r14, and r15, each of which is allocated to a specific duty or unique function

 Register 13 is traditionally used as the stack pointer (SP) and stores the head of the stack
in the current processor mode.
 Register r14 is called the link register (LR) and is where the core puts the return address
whenever it calls a subroutine.
 Register 15 is the program counter (PC) and contains the address of the next instruction
to be fetched by the processor.
Current Program Status Register ( CPSR)

 CPSR in ARM is used in core to monitor and control internal functions. The vacant area
has been set aside for future development.
 Flags, status, extension, and control are the four fields of the CPSR, each of which is 8
bits wide.
 Status and extension fields are kept for future use in current designs.
 Several ARM processor cores include extra bits allocated to the J bit.

Fig: CPSR

The ARM has seven operating modes:

User: unprivileged mode under which most tasks run

FIQ: entered when a high priority (fast) interrupt is raised

IRQ: entered when a low priority (normal) interrupt is raised

SVC: (Supervisor) entered on reset and when a Software Interrupt instruction is executed

Abort: used to handle memory access violations

Undef: used to handle undefined instructions

System: privileged mode using the same registers as user mode

Pipeline
The instruction pipeline The ARM7TDMI core uses a pipeline to increase the speed of
the flow of instructions to the processor. This allows several operations to take place
simultaneously, and the processing and memory systems to operate continuously. A three-stage
pipeline is used, so instructions are executed in three stages: • Fetch • Decode • Execute. The
instruction pipeline is shown in Figure
Exceptions and interrupts interrupt vector table

An exception is any condition that needs to halt normal execution of the instructions

Examples

•Resetting ARM core

•Failure of fetching instructions

•HWI

•SWI

Each exception causes the ARM core to enter a specific mode.

Exceptions and modes

Exception Mode Purpose

Fast Interrupt Request FIQ Fast interrupt handling
Interrupt Request IRQ Normal interrupt handling
SWI and RESET SVC Protected mode for OS
Pre-fetch or data abort ABT Memory protection handling
Undefined Instruction UND SW emulation of HW
coprocessors
Interrupt Vector Table

Instruction set of ARM Processor

Conditional execution
All ARM7TDMI instructions can be executed conditionally, based on a 4-bit condition
field in the instruction. The processor tests the state of the condition flags in the CPSR (N, Z, V,
C), and if the condition flag state matches the condition, the instruction executes normally. If the
condition flag state does not match the condition, the instruction is executed as a NOP (no
operation).
THUMB INSTUCTUION

The Thumb instruction set is a subset of the most commonly used 32-bit ARM
instructions. Thumb instructions are each 16 bits long, and have a corresponding 32-bit ARM
instruction that has the same effect on the processor model. Thumb instructions operate with the
standard ARM register configuration, allowing excellent interoperability between ARM and
Thumb states.
On execution, 16-bit Thumb instructions are transparently decompressed to full 32-bit
ARM instructions in real time, without performance loss.
Thumb has all the advantages of a 32-bit core:
• 32-bit address space
• 32-bit registers
• 32-bit shifter, and Arithmetic Logic Unit (ALU)
• 32-bit memory transfer.
The following
Figure ARM vs. Thumb programmer’s models