CADD ASSIGNMENT -1

O_level_2
Problem statement: To Implement an ALU with a MAC
Feature
(on Xilinx Vivado)
Name: Prajwal R and Rengashyam
Section: D
SRN: PES1UG23EC217 and PES1UG23EC241
Description
Our goal was to make it so that the fpga can be used similar to a logical
calculator as it would make analysis of complex equations easier. Something
similar to adding a logic mode to our scientific calculator to evaluate logical
expressions. To make this possible first we need to make it realizable on the
fpga for which we took the first step through this project. During this project
we encountered multiple issues and challenges which we worked around from
which we gained a lot of insight that helped know how much though is put to
realise an idea from the scratch to a finished product.

This ALU with MAC has 6 inputs, namely clock, enable, reset, input Operands A
and B and the control signal. The control signal defines the operation to be
done on the operand and the enable signal turn the accumulator on and off.
When in accumulation mode, for every clock pose edge the output of the
operation is stored and is used instead of input A in next cycle of operations.
The outputs include the result of the operation and an indicator variable which
shows when to give the next operation or when the current result is being
stored into the data of the system.
Truth table
The ALU does 8 operation which include

1.Addition – control signal 000

Input Output
A B C (accumulated En =0 En=1
value)
A B Previous value A+B C+B
or initially 0

2.Subsraction – control signal 001

Input Output
A B C (accumulated En =0 En=1
value)
A B Previous value A-B C-B
or initially 0

3.AND – control signal 010

Input Output
A B C (accumulated En =0 En=1
value)
A B Previous value A&B C&B
or initially 0
4.OR – control signal 011
Input Output
A B C (accumulated En =0 En=1
value)
A B Previous value A|B C|B
or initially 0

5.XOR – control signal 100

Input Output
A B C (accumulated En =0 En=1
value)
A B Previous value A^B C^B
or initially 0

6.Multiplication – control signal 101

Input Output
A B C (accumulated En =0 En=1
value)
A B Previous value A*B C*B
or initially 0

7.Left shift – control signal 110 (this operation doesn’t support accumulation)
Input Output
A En =0 En=1

A A<<1 A<<1
8.Right shift – control signal 111

Input Output
A En =0 En=1

A A>>1 A>>1

Design Module Code (system Verilog)

` mescale 1ns / 1ps
module ALU (
input logic hclk,en, // Clock signal for sequen al logic
input logic reset, // Reset signal
input logic [7:0] A,B, // 8-bit input B
input logic [2:0] control, // 3-bit control signal
output logic [7:0] result, // 8-bit output result
output logic indicator // to indicate clk at output for when data is stored
);
logic clk;
freq100Mhz_1 reducer (hclk,1'b0,clk,indicator); //reducing clock from 100Mhz to 2 second
logic [7:0] C; // Internal 8-bit register for A

// Sequen al block to update A and result

always_ff @(posedge clk , posedge reset , posedge en) begin
if (reset) begin
C <= 8'b0; // Reset C to 0
result <= 8'b0; // Reset result to 0
end else begin
case (control)

3'b000: begin
result <= A + B; // Perform addi on
if(en)begin
result <= C + B; // Perform opera on
C <= result; // Store the addi on result in C for the next cycle
end
end
3'b001: begin
result <= A - B; // Subtrac on (doesn't update C)
if(en)begin
result <= C - B; // Perform opera on
C <= result; // Store the addi on result in C for the next cycle
end
 3'b010: begin
result <= A & B; // AND opera on (doesn't update C)
if(en)begin
result <= C & B; // Perform opera on
C <= result; // Store the addi on result in C for the next cycle
end
end
3'b011: begin
result <= A | B; // OR opera on (doesn't update C)
if(en)begin
result <= C | B; // Perform opera on
C <= result; // Store the addi on result in C for the next cycle
end
end
3'b100: begin
result <= A ^ B; // XOR opera on (doesn't update C)
if(en)begin
result <= C ^ B; // Perform opera on
C <= result; // Store the addi on result in C for the next cycle
end
end
3'b101: begin
result <= A * B; // mul plica on opera on (doesn't update C)
if(en)begin
result <= C * B; // Perform opera on
C <= result; // Store the addi on result in C for the next cycle
end
end
3'b110: result <= A << 1; // Le shi A (doesn't update C)
3'b111: result <= A >> 1; // Right shi A (doesn't update C)
default: result <= 8'b0; // Default case
endcase
end
end
endmodule

module freq100Mhz_1 (
input logic clk_in, //100Mhz
input logic res,
output logic clk_out, //1Hz
output logic clk_out_1
);
parameter int DIV = 100000000*2; // Number of clock cycles to divide by
logic [27:0] counter;
always_ff@(posedge clk_in,posedge res)
if(res)
counter<=0;
else if(clk_in)
if(counter<DIV)
begin
counter<=counter+1;
clk_out=0;clk_out_1=0;
end
else
begin
counter<=0;
clk_out=1;clk_out_1=1;
end
endmodule
Testbench Module

module ALU_tb;

// Testbench signals
logic clk,ck;
logic en;
logic reset;
logic [7:0] A,B;
logic [2:0] control;
logic [7:0] result;

// Instan ate the ALU

ALU uut (
.clk(clk),
.reset(reset),
.en(en),
.A(A),
.B(B),
.control(control),
.result(result),
.ck(ck)
);

// Clock genera on: 10 ns period (100 MHz)

always #10 clk = ~clk;

// Test procedure
ini al begin
// Ini alize signals
clk = 0;en=0;
reset = 0;
A=0;B = 0;
control = 0;

// Apply reset
reset = 1;en=0;
#10;
reset = 0;en=0;
#10;

// Test addi on with feedback on A

A = 8'h04;
B = 8'h03;
control = 3'b000;en=1; // Addi on
#10;

#10; // Wait for next clock cycle

A = 8'h01;
B = 8'h02; // Change B to 2
control = 3'b000;en=1; // Addi on
#10;
 // Test subtrac on (without upda ng A)
control = 3'b001; // Subtrac on
#10;
// Test AND opera on
control = 3'b010; // AND
#10;
// Test OR opera on
control = 3'b011; // OR
#10;
// Test XOR opera on
control = 3'b100; // XOR
#10;
// Test NOT opera on
control = 3'b101; // NOT
#10;
// Test le shi
control = 3'b110; // Le Shi
#10;
// Test right shi
control = 3'b111; // Right Shi
#10;
// Apply reset again
reset = 1;
#10;
reset = 0;
#10;
// Finish the simula on
$finish;
end
endmodule

Simulation Graph

(ck here is running wrt to the frequency reducer circuit and is changing for
every 2 seconds only)

Utilization Report
RTL Schematic

Synthesis Schematic
 XDC file (I/O setup)

set_property IOSTANDARD LVCMOS33 [get_ports {A[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {A[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {control[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {control[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {control[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {result[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {result[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {result[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {result[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {result[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {result[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {result[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {result[0]}]
set_property PACKAGE_PIN R2 [get_ports {A[3]}]
set_property PACKAGE_PIN T1 [get_ports {A[2]}]
set_property PACKAGE_PIN U1 [get_ports {A[1]}]
set_property PACKAGE_PIN W2 [get_ports {A[0]}]
set_property PACKAGE_PIN R3 [get_ports {B[3]}]
set_property PACKAGE_PIN T2 [get_ports {B[2]}]
set_property PACKAGE_PIN T3 [get_ports {B[1]}]
set_property PACKAGE_PIN V2 [get_ports {B[0]}]
set_property PACKAGE_PIN W15 [get_ports {control[2]}]
set_property PACKAGE_PIN W16 [get_ports {control[0]}]
set_property PACKAGE_PIN W17 [get_ports {control[1]}]
set_property PACKAGE_PIN L1 [get_ports {result[7]}]
set_property PACKAGE_PIN P1 [get_ports {result[6]}]
set_property PACKAGE_PIN N3 [get_ports {result[5]}]
set_property PACKAGE_PIN P3 [get_ports {result[4]}]
set_property PACKAGE_PIN U3 [get_ports {result[3]}]
set_property PACKAGE_PIN W3 [get_ports {result[2]}]
set_property PACKAGE_PIN V3 [get_ports {result[1]}]
set_property PACKAGE_PIN V13 [get_ports {result[0]}]
set_property PACKAGE_PIN V17 [get_ports en]
set_property IOSTANDARD LVCMOS33 [get_ports en]
set_property IOSTANDARD LVCMOS33 [get_ports hclk]
set_property IOSTANDARD LVCMOS33 [get_ports reset]
set_property PACKAGE_PIN W5 [get_ports hclk]
set_property PACKAGE_PIN V16 [get_ports reset]
set_property IOSTANDARD LVCMOS33 [get_ports ck]
set_property PACKAGE_PIN W18 [get_ports ck]

Block Diagram
Clk

En
Reset Output
input A
indicator
ALU with MAC
Input B
Output
control Result
signal
Conclusion
We were able to implement this simpler version of the final product we wanted
a logic calculator. This ALU with MAC will be the core of the logic calculator if
we were to implement one. Some of the issues we faced were not perfectly
resolved. If the device is run without to resetting for the first use the internal
variables aren’t properly initialised and sometimes the clock for accumulation
is faster than the user’s input leading to errors . But in this implementation we
made sure to reset the fpga for every new test run and made the clock division
send an output frequency of 2 seconds. And were able to solve logic
expressions in 2 variables of output less than 2^8 (256). Hence implemented
ALU with MAC (accumulator for 4 bit input and 8bit output with 8 operation and
an indicator on fpga.