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Assignment 2

The document outlines Assignment 2 for a Digital Logic Design course, detailing tasks related to the functioning of digital components such as Half Adder, Full Adder, Decoder, and Multiplexor. It includes specific functions to be implemented using a Decoder and a Multiplexor, with a total of 80 marks available. The assignment is due on December 29, 2021, and is instructed by Dr. F. Anjam.

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11 views1 page

Assignment 2

The document outlines Assignment 2 for a Digital Logic Design course, detailing tasks related to the functioning of digital components such as Half Adder, Full Adder, Decoder, and Multiplexor. It includes specific functions to be implemented using a Decoder and a Multiplexor, with a total of 80 marks available. The assignment is due on December 29, 2021, and is instructed by Dr. F. Anjam.

Uploaded by

yawarzaman2
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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DLD – Digital Logic Design

Assignment 2
Date: 22-12-2021
Due Date: 29-12-2021
Instructor: Dr. F. Anjam Total Marks: 80 (relative)

1. Explain the working of: (CLO 1 --- marks = 40)


i. Half Adder
ii. Full Adder
iii. Decoder
iv. Multiplexor

2. Implement the following functions using Decoder. (CLO 2 --- marks = 20)

i. F1 = A’·B·C’·D + A’·B’·C·D + A·B·C·D


ii. F2 = A·B·C’·D’ + A·B·C

3. Implement the following functions using MUX. (CLO 2 --- marks = 20)

i. F(A, B, C) = A’·B·C’ + A’·B·C + A·B


ii. F(A, B, C) = ∑(0, 3, 5, 6)

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