Digital IC Design

Combinational MOS Logic

Combinational MOS Logic

See Kang and Leblebici Book
Digital IC Design

Combinational MOS Logic

Complex Designs: Stick Diagram: The stick-diagram layout does not carry any information on
the actual geometry relations of the individual features, but it conveys valuable information on the
relative placement of the transistors and their interconnections in comparatively complex logic function
implementation.
This optimization is provided by Euler’s Rule in Stick/Layout Diagrams
For example: Following Boolean function is to be implemented using CMOS logic.
Also the general stick layout and optimized stick layout to be obtained.
Digital IC Design

Combinational MOS Logic

Digital IC Design

Euler-path approach to get optimized layout

Advantages:
✓ more compact (smaller) layout area,
✓ simple routing of signals,
✓ Less parasitic capacitance.
Digital IC Design

Design rules:

Design rules are the communication link between the designer specifying requirements and
the fabricator who materializes them.

To pattern various layers in silicon, masks are made out of these design rules. Most common
is “Lambda-based” rules. Using these rules, stick diagrams are drawn.

Stick diagrams are nothing but an interface between the symbol circuit and the actual layout.

It conveys layer information through colour codes.

A stick diagram is a cartoon of layout.

Does not show:

Exact placement of components/vias but shows relative placement of components.
Transistor sizes
wire length, wire width, tub boundaries
Goes one step closer to the layout
Helps plan the layout and routing
Digital IC Design

Lambda () based design rules:

• Minimum width of PolySi and diffusion line 2
• Minimum width of Metal line 3 as metal lines run over a more uneven surface than other conducting layers to ensure their
continuity
• PolySi – PolySi space 2
• Metal - Metal space 2
• Diffusion – Diffusion space 3 To avoid the possibility of their associated regions overlapping and conducting current.
• Diffusion – PolySi space  To prevent the lines overlapping to form unwanted capacitor
• It is recommended practice to leave  between a metal edge and a polySi or diffusion line to which it is not electrically
connected

 

Metal

 Diffusion

   Polysilicon

Metal

Polysilicon
Digital IC Design

Stick Diagrams – Notations or color coding

Metal (blue)

Poly (red)

N diff (green)

P diff (yellow)
Can also draw
in shades of
gray/line style.
Buried Contact

Contact Cut

Similarly for contacts, via, tub etc.. 7

Digital IC Design

Stick Diagrams

N+ N+

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Digital IC Design

Stick Diagrams
VDD
VDD
X

X
x Stick x x
x Diagram X

Gnd Gnd

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Digital IC Design

Stick Diagrams

VDD
VDD
X

X
x x x
x X

Gnd Gnd

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Digital IC Design

Stick Diagrams – Some rules

Rule 1.
When two or more ‘sticks’ of the same type cross or touch each other that represents
electrical contact.

Rule 2.
When two or more ‘sticks’ of different type cross or touch each other there is no
electrical contact.
(If electrical contact is needed we have to show the connection explicitly).

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Digital IC Design

Stick Diagrams – Some rules

Rule 3.
When a poly crosses diffusion it represents a transistor.

Note: If a contact is shown then it is not a transistor.

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Digital IC Design

Stick Diagrams – Some rules

Rule 4.
In CMOS, a demarcation line is drawn to avoid touching of p-diff with n-diff. All pMOS
must lie on one side of the line and all nMOS will have to be on the other side.

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Digital IC Design

Steps followed to draw stick diagrams:

1. Draw the schematic diagram

2. Understand the nature of devices used (eg. nMOS or pMOS)
3. Use the exact colour code

Any Boolean expression can be represented by stick diagram.

Operator PMOS NMOS

Dot (.) Parallel Series
Plus (+) Series parallel
Digital IC Design

Steps for schematic:

1. Always start from the NMOS section (i.e. bottom to top approach)
2. Draw the transistors as per convention (“.” or “+”)
3. Label each transistor with the variables mentioned in the function
4. Label the power supply VDD and ground connection

Rules for Selecting the Euler’s path for the stick diagram

1. Represent each NMOS and PMOS by curvy line.

2. Select the patch such that no line is traversed twice.
3. Write the S and D terminals for each NMOS and PMOS transistor.
Digital IC Design

The 3-D View of a Design

Digital IC Design

Combinational MOS Logic

AOI and OAI Gates

OAI: OR-AND-Inverter Gate : Sum of Product Realization (Pull-Down nMOS)

AOI: AND-OR-Inverter Gate: Product of Sum Realization (DUAL, Pull up pMOS)

Digital IC Design

Combinational MOS Logic

AOI and OAI Gates

OAI: OR-AND-Inverter Gate : Sum of Product Realization (Pull-Down nMOS)

AOI: AND-OR-Inverter Gate: Product of Sum Realization (DUAL, Pull up pMOS)

Digital IC Design

Combinational MOS Logic

AOI and OAI Gates

OAI: OR-AND-Inverter Gate : Sum of Product Realization (Pull-Down nMOS)

AOI: AND-OR-Inverter Gate: Product of Sum Realization (DUAL, Pull up pMOS)

Digital IC Design

Combinational MOS Logic

AOI and OAI Gates

OAI: OR-AND-Inverter Gate : Sum of Product Realization (Pull-Down nMOS)

AOI: AND-OR-Inverter Gate: Product of Sum Realization (DUAL, Pull up pMOS)

Digital IC Design

Combinational MOS Logic

AOI and OAI Gates

OAI: OR-AND-Inverter Gate : Sum of Product Realization (Pull-Down nMOS)

AOI: AND-OR-Inverter Gate: Product of Sum Realization (DUAL, Pull up pMOS)

Digital IC Design

Combinational MOS Logic

Pseudo nMOS Gates

Digital IC Design

Combinational MOS Logic

Pseudo nMOS Gates

Digital IC Design

Combinational MOS Logic

Pseudo nMOS Gates

Digital IC Design

Combinational MOS Logic

Pseudo nMOS Gates

Digital IC Design

Combinational MOS Logic

Pseudo nMOS Gates

Digital IC Design

Combinational MOS Logic

Pseudo nMOS Gates

Digital IC Design

Combinational MOS Logic

Pseudo nMOS Gates

PUN: Pull Up Network

PDN: Pull Down Network
Digital IC Design

Combinational MOS Logic

Pseudo nMOS Gates

Digital IC Design

Combinational MOS Logic

Pseudo nMOS Gates: Power and size issues

Digital IC Design

Combinational MOS Logic

Pseudo nMOS Gates: Ratioed Logic

Digital IC Design

Combinational MOS Logic

Pseudo nMOS Gates-Example

Digital IC Design

Combinational MOS Logic

Pseudo nMOS Gates-Example

Digital IC Design

Combinational MOS Logic

Pseudo nMOS Gates-Example

Digital IC Design

Combinational MOS Logic

Pseudo nMOS Gates-Example

Digital IC Design

Combinational MOS Logic

Pseudo nMOS Gates-Example

Digital IC Design

Combinational MOS Logic

Pseudo nMOS Gates-Example

Digital IC Design

Combinational MOS Logic

CMOS One Bit Full-Adder

Homework: Draw the CMOS gate level diagram and stick diagram
Digital IC Design

Combinational MOS Logic

Pass transistors/gates or transmission gates

A and B are controlled by signal

Digital IC Design

Combinational MOS Logic

Pass transistors/gates or transmission gates

TG acts as a bi-directional switch between A and B are controlled by signal C

Digital IC Design

Combinational MOS Logic

Pass transistors/gates or transmission gates

When C is high (VDD) both MOSFETs are ON: current can pass from A to B
(low resistance)
Digital IC Design

Combinational MOS Logic

Pass transistors/gates or transmission gates

When C is low (0) both MOSFETs are OFF: current can’t pass from A to B
(high impedance)
Digital IC Design

Combinational MOS Logic

Pass transistors/gates or transmission gates

Substrate terminals of NMOS is grounded and PMOS is at VDD. Careful! with γ.

Note that source-to-substrate voltage of the nMOS is equal to the Vout

while for pMOS it is zero
Digital IC Design

Combinational MOS Logic

Operation of pass transistors/gates or transmission gates

❑ Let input A is at constant high voltage VDD.

Digital IC Design

Combinational MOS Logic

Operation of pass transistors/gates or transmission gates

❑ Let input A is at constant high voltage VDD.

❑ Control signal is also high (both TGs are ON).

❑ Vout is connected to a cap, C.

Digital IC Design

Combinational MOS Logic

Operation of pass transistors/gates or transmission gates

❑ For nMOS:
Digital IC Design

Combinational MOS Logic

Operation of pass transistors/gates or transmission gates

❑ For nMOS:

❑ Will turn off for VDD- VT,n <Vout

Digital IC Design

Combinational MOS Logic

Operation of pass transistors/gates or transmission gates

❑ For nMOS:

❑ Will turn off for VDD- VT,n <Vout

❑ Will go to saturation when VDD- VT,n >Vout
Here VGS is VDD
Digital IC Design

Combinational MOS Logic

Operation of pass transistors/gates or transmission gates

❑ For pMOS:

❑ Will be in the linear region for |VT,p| < Vout

❑ Will go to saturation when |VT,p| > Vout
Here VGS is 0.

❑ pMOS is always turned on.

Digital IC Design

Combinational MOS Logic

Operation of pass transistors/gates or transmission gates

❑ Total current:

❑ Equivalent resistance :
(for total: do parallel )
Digital IC Design

Combinational MOS Logic

Operation of pass transistors/gates or transmission gates

❑ Resistance in Region 1:
Digital IC Design

Combinational MOS Logic

Operation of pass transistors/gates or transmission gates

❑ Resistance in Region 2:
Digital IC Design

Combinational MOS Logic

Operation of pass transistors/gates or transmission gates

❑ Resistance in Region 3:
Digital IC Design

Combinational MOS Logic

Operation of pass transistors/gates or transmission gates

Digital IC Design

Combinational MOS Logic

Representation of TGs
Digital IC Design

Combinational MOS Logic

2 Input Multiplexor using TGs

❑ If S = 0, B passes, A fails
❑ If S = 1, B fails, A passes
Digital IC Design

Combinational MOS Logic

8 Transistors-XOR CMOS

❑ 2CMOS TGs
❑ 2 CMOS inverters
Digital IC Design

Combinational MOS Logic

6 Transistors-XOR CMOS
Digital IC Design

Combinational MOS Logic

3 Variable Boolean Function CMOS TG