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Unit 2 Electronic

The document outlines a practice sheet for B. Tech. 3rd semester students at Pranveer Singh Institute of Technology, focusing on Digital Electronics. It includes course outcomes related to digital systems, devices, and circuit design, along with a series of problems and design tasks for students to complete. Topics covered include Boolean expressions, multiplexers, adders, and combinational logic circuits.

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21 views2 pages

Unit 2 Electronic

The document outlines a practice sheet for B. Tech. 3rd semester students at Pranveer Singh Institute of Technology, focusing on Digital Electronics. It includes course outcomes related to digital systems, devices, and circuit design, along with a series of problems and design tasks for students to complete. Topics covered include Boolean expressions, multiplexers, adders, and combinational logic circuits.

Uploaded by

narayangupta8081
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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PRANVEER SINGH INSTITUTE OF TECHNOLOGY KANPUR

odd Semester Session 2024-25 Practice Sheet-2


th
B. Tech. 3 Semester
Digital Electronics (BOE-310)
CO Number Course Outcome

CO1 Define the concepts of Digital system (logic gates, Combinational Logic, Sequential Logic,
Synchronous & Asynchronous Sequential Circuits and memory).
CO2 Explain the concepts of various digital devices and logic families.

CO3 Apply the concepts of digital devices on various applications.

CO4 Analyze various digital circuits, Sequential Logic, Synchronous & Asynchronous Sequential of
different configuration.
CO5 Design various digital circuits, Sequential Logic, Synchronous & Asynchronous Sequential of
different configuration.

1. For the given function, write the Boolean expression in product of maxterm form
f(a,b,c)= ∑m(2,3,5,6,7).?
2. What is a data selector?
3. Mention the uses of decoders.
4. What is a priority encoder?
5. Write the logic equation and draw the internal logic diagram for a 4 to 1 mux?
6. Expand the function f (A, B, C) =A +B’C to standard SOP form?
7. Using k-map find minimum sop for the function.
F (a, b, c) = ∑ m (0, 1, 5, 6, 7)
8. Implement the given function in 4:1 mux f= ∑m(0,1,3,5,6)
9. Design a half adder?
10. Draw a combinational logic circuit, which can compare whether two bits binarynumbers are
same or not?
11. Design a half adder using NAND – NAND logic
12 . Design a 2-bit magnitude comparator?
13 Using 8 to 1mux, realize the Boolean function
T=F (w, x, y, z)= ∑ m (0,1,2,4,5,7,8,9,12,13)
14. Implement the Boolean function using 8:1 mux.
F (A, B, C, D) =A’BD’+ACD+B’CD+A’C’D.
15. Explain the operation of 4 to 10 decoder.
16. Implement the following multiple output combinational logic circuit using a 3-to8
decoder.
F1=∑ m (1, 2, 3, 5, 7)
F2=∑ m (0, 3, 6)
F3=∑ m (0, 2, 4, 6)
17. Design a 4-bit adder /subtractor-using logic gates and explains its operation.
18. Construct a combinational circuit to convert BCD to EX-3 code.
19 . Design A Full Adder And A Full Subtractor.
20. Design A Full subtractor with using two half subtractor.
21. Design A Full Adder with using two half adder .
22. Design A Full Adder circuit with using two half adder circuit .
23. Design A Full subtractor circuit with using two half subtractor circuit.
24. Implement the given function in 4:1 mux f= ∑m(0,1,3,5,8)
25. Design a half adder using NAND – NAND logic.
26. Explain how a full adder can be built using two half adders.
27. Design a half adder using at most three NOR gates.
28. Using 8 to 1 multiplexer, realize the Boolean function
T = f(w, x, y, z) = Σ(0,1,2,4,5,7,8,9,12,13)
29. Draw the logic diagram of full substractor and explain its operation.
30. Design a full adder circuit using only NOR gates only.

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