TMP61

SBOS921F – DECEMBER 2018 – REVISED NOVEMBER 2023

TMP61 ±1% 10-kΩ Linear Thermistor With 0402 and 0603 Package Options

1 Features 3 Description
• Silicon-based thermistor with a Get started today with the Thermistor Design Tool,
positive temperature coefficient (PTC) offering complete resistance vs temperature table (R-
• Linear resistance change across temperature T table) computation, other helpful methods to derive
• 10-kΩ nominal resistance at 25°C (R25) temperature and example C-code.
– ±1% maximum (0°C to 70°C) The TMP61 linear thermistor offers linearity and
• Wide operating temperature of –40°C to +150 °C consistent sensitivity across temperature to enable
• Consistent sensitivity across temperature simple and accurate methods for temperature
– 6400 ppm/°C TCR (25°C) conversion. The low power consumption and a small
– 0.2% typical TCR tolerance across temperature thermal mass of the device minimize self-heating.
range
• Fast thermal response time of 0.6 s (DEC) With built-in fail-safe behaviors at high temperatures
• Long lifetime and robust performance and powerful immunity to environmental variation,
– Built-in fail-safe in case of short-circuit failures these devices are designed for a long lifetime of high
– 0.5% typical long term sensor drift performance. The small size of the TMP6 series also
allows for close placement to heat sources and quick
2 Applications response times.
• Temperature monitoring Take advantage of benefits over NTC thermistors
– HVAC and thermostats such as no extra linearization circuitry, minimized
– Industrial control and appliances calibration, less resistance tolerance variation, larger
• Thermal compensation sensitivity at high temperatures, and simplified
– Display backlights conversion methods to save time and memory.
– Building automation The TMP61 is currently available in a 0402 X1SON
• Thermal threshold detection package, a 0603 SOT-5X3 package, and a 2-pin
– Motor control through-hole TO-92S package.
– Chargers
Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
DEC (X1SON, 2) 1.00 mm × 0.60 mm
TMP61 LPG (TO-92S, 2) 4.00 mm × 1.52 mm
DYA (SOT-5X3, 2) 1.60 mm × 0.80 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.
(2) The package size (length × width) is a nominal value and
includes pins, where applicable.
VBias 25

RBias IBias 20
Resistance (k:)

15
RTMP61 VTemp RTMP61 VTemp

10

5
-40 -15 10 35 60 85 110 135 160
Temperature (qC) 61_F

Typical Implementation Circuits Typical Resistances vs Ambient Temperature

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.4 Device Functional Modes............................................9
2 Applications..................................................................... 1 8 Application and Implementation.................................. 10
3 Description.......................................................................1 8.1 Application Information............................................. 10
4 Device Comparison......................................................... 2 8.2 Typical Application.................................................... 10
5 Pin Configuration and Functions...................................3 8.3 Power Supply Recommendations.............................16
6 Specifications.................................................................. 4 8.4 Layout....................................................................... 16
6.1 Absolute Maximum Ratings........................................ 4 9 Device and Documentation Support............................17
6.2 ESD Ratings............................................................... 4 9.1 Receiving Notification of Documentation Updates....17
6.3 Recommended Operating Conditions.........................4 9.2 Support Resources................................................... 17
6.4 Thermal Information....................................................4 9.3 Trademarks............................................................... 17
6.5 Electrical Characteristics.............................................5 9.4 Glossary....................................................................17
6.6 Typical Characteristics................................................ 6 9.5 Electrostatic Discharge Caution................................17
7 Detailed Description........................................................8 10 Revision History.......................................................... 17
7.1 Overview..................................................................... 8 11 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram........................................... 8 Information.................................................................... 18
7.3 Feature Description.....................................................9

4 Device Comparison
Table 4-1. Device Comparison
PART
R25 TYP R25 %TOL RATING TA PACKAGE OPTIONS
NUMBER
–40°C to 125°C X1SON / DEC (0402)
TMP61 10k 1% Catalog –40°C to 150°C SOT-5X3 / DYA (0603)
–40°C to 150°C TO-92S / LPG
Automotive Grade-1 –40°C to 125°C X1SON / DEC (0402)
TMP61-Q1 10k 1% –40°C to 150°C SOT-5X3 / DYA (0603)
Automotive Grade-0
–40°C to 170°C TO-92S / LPG
–40°C to 125°C X1SON / DEC (0402)
TMP63 100k 1% Catalog
–40°C to 150°C SOT-5X3 / DYA (0603)
Automotive Grade-1 –40°C to 125°C X1SON / DEC (0402)
TMP63-Q1 100k 1%
Automotive Grade-0 –40°C to 150°C SOT-5X3 / DYA (0603)
–40°C to 125°C X1SON / DEC (0402)
TMP64 47k 1% Catalog
–40°C to 150°C SOT-5X3 / DYA (0603)
Automotive Grade-1 –40°C to 125°C X1SON / DEC (0402)
TMP64-Q1 47k 1%
Automotive Grade-0 –40°C to 150°C SOT-5X3 / DYA (0603)

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5 Pin Configuration and Functions

± 1 2 + + 2 1 –

Figure 5-1. DEC Package 2-Pin X1SON Top View ID mark is identified as a dot in the ID area and it denotes pin 1.
Figure 5-2. DYA Package 2-Pin SOT-5X3 Top View

1 2

– +

1 2
– +
Front view is described as chamfers of TO-92S facing the user. Bottom view is described as pins coming out of the page.

Figure 5-3. LPG Package 2-Pin TO-92S Front View, Bottom View

Table 5-1. Pin Functions

PIN
TYPE DESCRIPTION
NAME NO.
– 1 Thermistor (–) and (+) terminals. For proper operation, ensure a positive bias where the +
—
+ 2 terminal is at a higher voltage potential than the – terminal.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Voltage across the device 6 V
Junction temperature (TJ) –65 155 °C
Current through the device 450 µA
Storage temperature (Tstg) –65 155 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM) per JESD22-A114(1) ±2000 V
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VSns Voltage Across Pins 2 (+) and 1 (–) 0 5.5 V
ISns Current passing through the device 0 400 µA
Operating free-air temperature (X1SON/DEC Package) –40 125
TA Operating free-air temperature (TO-92S/LPG Package) –40 150 °C
Operating free-air temperature (SOT-5X3/DYA Package) –40 150

6.4 Thermal Information

TMP61
THERMAL METRIC(1) (2) DEC (X1SON) LPG (TO-92S) DYA (SOT-5X3) UNIT
2 PINS 2 PINS 2 PINS
RθJA Junction-to-ambient thermal resistance(3) (4) 443.4 215 742.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 195.7 99.9 315.8 °C/W
RθJB Junction-to-board thermal resistance 254.6 191.7 506.2 °C/W
ΨJT Junction-to-top characterization parameter 19.9 35.1 109.3 °C/W
YJB Junction-to-board characterization parameter 254.5 191.7 500.4 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) For information on self-heating and thermal response time see Layout Guidelines section.
(3) The junction to ambient thermal resistance (RθJA ) under natural convection is obtained in a simulation on a JEDEC-standard, High-K
board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are
included in the PCB, per JESD 51-5.
(4) Changes in output due to self heating can be computed by multiplying the internal dissipation by the thermal resistance.

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6.5 Electrical Characteristics

TA = –40°C to 150 °C, ISns = 200 μA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
R25 Thermistor Resistance at 25°C(1) TA = 25°C 9.9 10 10.1 kΩ
RTOL Resistance Tolerance(1) TA = 25°C –1 1 %
TA = 0°C to 70°C –1 1
RTOL Resistance Tolerance(1) %
TA = –40°C to 150°C –1.5 1.5
TCR-35 T1 = –40°C, T2 = –30°C +6220
TCR25 Temperature Coefficient of Resistance T1 = 20°C, T2 = 30°C +6400 ppm/°C
TCR85 T1 = 80°C, T2 = 90°C +5910
TCR-35 % T1 = –40°C, T2 = –30°C ±0.4
Temperature Coefficient of Resistance
TCR25 % T1 = 20°C, T2 = 30°C ±0.2 %
Tolerance
TCR85 % T1 = 80°C, T2 = 90°C ±0.3
96 hours continuous operation
-1 0.1 1
RH = 85 %, TA = 130°C, VBias = 5.5V
600 hours continuous operation at TA = 150°C
-1 0.5 1.8
VBias = 5.5V, DEC Package
600 hours continuous operation at TA = 150 °C
ΔR Sensor Long Term Drift (Reliability) -1 0.2 1.2 %
VBias = 5.5V, DYA Package
1000 hours continuous operation at TA = 150 °C
-1 0.2 1.2
VBias = 5.5V, DYA Package
1000 hours continuous operation at TA = 150°C
-0.5 0.5 1.4
VBias = 5.5V, LPG Package
tRES (stirred liquid) Thermal response to 63 % (DEC Package) T1 = 25°C in Still Air to T2 = 125°C in Stirred Liquid 0.6 s
tRES (stirred liquid) Thermal response to 63 % (LPG Package) T1 = 25°C in Still Air to T2 = 125°C in Stirred Liquid 2.9 s
tRES (still air) Thermal response to 63 % (DEC Package) T1 = 25°C to T2 = 70°C in Still Air 3.2 s
tRES (still air) Thermal response to 63 % (LPG Package) T1 = 25°C to T2 = 70°C in Still Air 20 s

(1) Limits defined based on 4th order equation, tolerance will change with 'Sensor Long Term Drift' specification.

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6.6 Typical Characteristics

at TA = 25°C, (unless otherwise noted)

22 22
20 20
18 18
16 16
Resistance (k:)

Resistance (k:)
14 14
12 12
10 10
8 8
6 IBIAS = 10 PA 6
IBIAS = 50 PA VBIAS = 1.8 V
4 IBIAS = 100 PA 4 VBIAS = 2.5 V
IBIAS = 200 PA VBIAS = 3.3 V
2 2
IBIAS = 400 PA VBIAS = 5 V
0 0
-40 -20 0 20 40 60 80 100 120 140 160 -40 -20 0 20 40 60 80 100 120 140 160
Temperature (qC) TMP6
Temperature (qC) TMP6

RBIAS = 10 kΩ with ±0.01% tolerance

Figure 6-1. Resistance vs Ambient Temperature Figure 6-2. Resistance vs Ambient Temperature
Using Multiple Bias Currents Using Multiple Bias Voltages
6510 6340

6480

6450 6330

6420
TCR (ppm/qC)

TCR (ppm/qC)

6320
6390

6360
6310
6330

6300 6300
6270

6240 6290
10 50 100 200 400 0.9 1.25 1.65 2.5
Current Through TMP61, ISns (PA) d004
Voltage Across TMP61, VSns (V) d005

VSns = 1.8 V, 2.5 V, 3.3 V, and 5.0 V, RBias = 10 kΩ with

Figure 6-3. TCR vs Sense Currents (ISNS) ±0.01% Tolerance

Figure 6-4. TCR vs Sense Voltages, VSns

22 22
20 20
18 18
16 16
Resistance (k:)

Resistance (k:)

14 14
12 12
10 10
8 8
6 6
4 4
-40 qC 50 qC 125 qC -40 qC 50 qC 125 qC
2 2
25 qC 100 qC 150 qC 25 qC 100 qC 150 qC
0 0
0 50 100 150 200 250 300 350 400 450 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Current (PA) TMP6
Voltage (V) TMP6

. RBias = 10 kΩ ( ±0.01% tolerance)

Figure 6-5. Supply Dependence Resistance vs Bias Figure 6-6. Supply Dependence vs Bias Voltage
Current

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2.5 20
VBias
VSns 18
2
16

Resistance (k:)
1.5
Output (V)

14

12
1

10
0.5 0.6s
8

0 6
0 1.6 3.2 4.8 6.4 8 0 0.19 0.38 0.57 0.76 0.95 1.14 1.33 1.52 1.71
Time (Ps) d008
Time (s) d009

VSNS = 1 V Ambient material: stirred liquid

Figure 6-7. Step Response Figure 6-8. Thermal Response Time (DEC package)
12 13

12.5
11.5
20s
12
Resistance (k:)

Resistance (k:)
11
11.5

10.5 11

10.5
10
3.2s 10

9.5 9.5
3.39 4.38 5.37 6.36 7.35 8.34 9.33 10.32 11.31 0 20 40 60 80 100 120 140 160
Time (s) d010 Time (s) D016

Ambient condition: still air Ambient condition: still air

Figure 6-9. Thermal Response Time (DEC and DYA Figure 6-10. Thermal Response Time (LPG
Package) Package)
20

18

16
Resistance (k:)

14

12

10

2.9s
8

6
0 2 4 6 8 10 12 14 16 18
Time (s) d015

Ambient material: stirred liquid

Figure 6-11. Thermal Response Time (LPG Package)

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7 Detailed Description
7.1 Overview
The TMP61 silicon linear thermistor has a linear positive temperature coefficient (PTC) that results in a uniform
and consistent temperature coefficient resistance (TCR) across a wide operating temperature range. TI uses a
special silicon process where the doping level and active region areas devices control the key characteristics
(the temperature coefficient resistance (TCR) and nominal resistance (R25)). The device has an active area
and a substrate due to the polarized terminals. Connect the positive terminal to the highest voltage potential.
Connect the negative terminal to the lowest voltage potential.
Unlike an NTC, which is a purely resistive device, the TMP61 resistance is affected by the current across the
device and the resistance changes when the temperature changes. In a voltage divider circuit, TI recommends
to maintain the top resistor value at 10 kΩ. Changing the top resistor value or the VBIAS value changes the
resistance vs temperature table (R-T table) of the TMP61, and subsequently the polynomials as described in the
Design Requirements section. Consult the TMP61 R-T table section for more information.
Equation 1 can help the user approximate the TCR.

RT2 RT1
TCR
T2 T1 u R T2 T1
2 (1)

where
• TCR is in ppm/°C
Key terms and definitions:
• ISNS: Current flowing through the TMP61 device
• VSNS: Voltage across the two TMP61 terminal
• IBIAS: Current supplied by the biasing circuit.
• VBIAS: Voltage supplied by the biasing circuit.
• VTEMP: Output voltage that corresponds to the measured temperature. Note that this is different from VSNS. In
the use case of a voltage divider circuit with the TMP61 in the high side, VTEMP is measured across RBIAS.
7.2 Functional Block Diagram
VBias

RBias IBias

RTMP61 VTemp RTMP61 VTemp

Figure 7-1. Typical Implementation Circuits

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7.3 Feature Description

7.3.1 TMP61 R-T table
The TMP61 R-T table must be re-calculated for any change in the bias voltage, bias resistor, or bias current.
TI provides a Thermistor Design Tool to calculate the R-T table. The system designer must always validate the
calculations provided.
7.3.2 Linear Resistance Curve
The TMP61 has good linear behavior across the whole temperature range as shown in Typical Characteristics.
This range allows a simpler resistance-to-temperature conversion method that reduces look-up table memory
requirements. The linearization circuitry or midpoint calibration associated with traditional NTCs is not necessary
with the device.
The linear resistance across the entire temperature range allows the device to maintain sensitivity at higher
operating temperatures.
7.3.3 Positive Temperature Coefficient (PTC)
The TMP61 has a positive temperature coefficient. As temperature increases the device resistance increases
leading to a reduction in power consumption of the bias circuit. In comparison, a negative coefficient system
increases power consumption with temperature as the resistance decreases.
The TMP61 benefits from the reduced power consumption of the bias circuit with less self-heating than a typical
NTC system.
7.3.4 Built-In Fail Safe
The TMP6 family feature a positive temperature coefficient. During a short-to-supply condition, the thermistor
will have increased current and power dissipated. Due to the positive temperature slope, the TMP6 will increase
resistance and limit self-heating by design.
In contrast, a NTC would continually reduce resistance due to self-heating leading to a positive feedback of
increasing power dissipation and decreasing resistance.
7.4 Device Functional Modes
The device operates in only one mode when operated within the Recommended Operating Conditions.

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

The TMP61 is a positive temperature coefficient (PTC) linear silicon thermistor. The device behaves as a
temperature-dependent resistor, and may be configured in a variety of ways to monitor temperature based on
the system-level requirements. The TMP61 has a nominal resistance at 25°C (R25) of 9.82 10 kΩ with ±1%
maximum tolerance, a maximum operating voltage of 5.5 V (VSNS), and maximum supply current of 400 µA
(ISNS). This device may be used in a variety of applications to monitor temperature close to a heat source with
the very small DEC package option compatible with the typical 0402 (inch) footprint. Some of the factors that
influence the total measurement error include the ADC resolution (if applicable), the tolerance of the bias current
or voltage, the tolerance of the bias resistance in the case of a voltage divider configuration, and the location of
the sensor with respect to the heat source.
8.2 Typical Application
8.2.1 Thermistor Biasing Circuits

VBias
IBias
RBias

RT VTemp
RT VTemp

Figure 8-2. Current Biasing Circuit With Linear

Figure 8-1. Voltage Biasing Circuit With Linear Thermistor
Thermistor
VBias
IBias
RBias

RT RP VTemp
RT RP VTemp

Figure 8-4. Current Biasing Circuit With Non-Linear

Figure 8-3. Voltage Biasing Circuit With Non-Linear Thermistor
Thermistor

8.2.1.1 Design Requirements

Existing thermistors, in general, have a non-linear temperature versus resistance curve. To linearize the
thermistor response, the engineer can use a voltage linearization circuit with a voltage divider configuration, or
a resistance linearization circuit by adding another resistance in parallel with the thermistor, RP. The Thermistor
Biasing Circuits section highlights the two implementations where RT is the thermistor resistance. To generate an
output voltage across the thermistor, the engineer can use a voltage divider circuit with the thermistor placed at
either the high side (close to supply) or low side (close to ground), depending on the desired voltage response

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(negative or positive). Alternatively, the resistor can be biased directly using a precision current source (yielding
the highest accuracy and voltage gain). It is common to use a voltage divider with thermistors because of
its simple implementation and lower cost. The TMP61, on the other hand, has a linear positive temperature
coefficient (PTC) of resistance such that the voltage measured across it increases linearly with temperature. As
such, the need for linearization circuits is no longer a requirement, and a simple current source or a voltage
divider circuit can be used to generate the temperature voltage.
This output voltage can be interpreted using a comparator against a voltage reference to trigger a temperature
trip point that is either tied directly to an ADC to monitor temperature across a wider range or used as feedback
input for an active feedback control circuit.
The voltage across the device, as described in Equation 2, can be translated to temperature using either a
lookup table method (LUT) or a fitting polynomial, V(T). The Thermistor Design Tool must be used to translate
Vtemp to Temperature. The temperature voltage must first be digitized using an ADC. The necessary resolution
of this ADC is dependent on the biasing method used. Additionally, for best accuracy, tie the bias voltage (VBIAS)
to the reference voltage of the ADC to create a measurement where the difference in tolerance between the bias
voltage and the reference voltage cancels out. The application can also include a low-pass filter to reject system
level noise. In this case, place the filter as close to the ADC input as possible.
8.2.1.2 Detailed Design Procedure
The resistive circuit divider method produces an output voltage (VTEMP) scaled according to the bias voltage
(VBIAS). When VBIAS is also used as the reference voltage of the ADC, any fluctuations or tolerance error due
to the voltage supply are cancelled and do not affect the temperature accuracy (as shown in Figure 8-5). Use
Equation 2 to calculate the output voltage (VTEMP) based on the variable resistance of the TMP61 (RTMP61) and
bias resistor (RBIAS). Use Equation 3 to calculate the ADC code that corresponds to that output voltage, ADC
full-scale range, and ADC resolution.

Figure 8-5. TMP61 Voltage Divider With an ADC

§ RTMP61 ·
VTEMP VBIAS × ¨ ¸
© RTMP61+ RBIAS ¹ (2)

VTEMP n
ADC Code 2
FSR (3)

where
• FSR is the full-scale range of the ADC, which is the voltage at REF to GND (VREF)
• n is the resolution of the ADC
Equation 4 shows when VREF = VBIAS, VBIAS cancels out.

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§ RTMP61 ·
VBIAS u ¨ ¸
© RTMP61+ RBIAS ¹ 2n § RTMP61 · n
ADC Code ¨ ¸2
VBIAS R + R
© TMP61 BIAS ¹ (4)

Use a polynomial equation or a LUT to extract the temperature reading based on the ADC code read in the
microcontroller. Use the Thermistor Design Tool to translate the TMP61 resistance to temperature.
The cancellation of VBIAS is one benefit to using a voltage-divider (ratiometric approach), but the sensitivity of the
output voltage of the divider circuit cannot increase much. Therefore, this application design does not use all of
the ADC codes due to the small voltage output range compared to the FSR. This application is very common,
however, and is simple to implement.
A current source-based circuit, such as the one shown in Figure 8-6, offers better control over the sensitivity of
the output voltage and achieve higher accuracy. In this case, the output voltage is simply V = I × R. For example,
if a current source of 40 µA is used with the device, the output voltage spans approximately 5.5 V and has a
gain up to 40 mV/°C. Having control over the voltage range and sensitivity allows for full use of the ADC codes
and full-scale range. Figure 8-7 shows the temperature voltage for various bias current conditions. Similar to the
ratiometric approach, if the ADC has a built-in current source that shares the same bias as the reference voltage
of the ADC, the tolerance of the supply current cancels out. In this case, a precision ADC is not required. This
method yields the best accuracy, but can increase the system implementation cost.

Figure 8-6. TMP61 Biasing Circuit With Current Source

9
IBIAS = 50 PA
8 IBIAS = 100 PA
IBIAS = 200 PA
7 IBIAS = 300 PA
IBIAS = 400 PA
6
VTEMP (V)

0
-60 -40 -20 0 20 40 60 80 100 120 140 160
Temperature (qC) d013

Figure 8-7. TMP61 Temperature Voltage With Varying Current Sources

In comparison to the non-linear NTC thermistor in a voltage divider, the TMP61 has an enhanced linear output
characteristic. The two voltage divider circuits with and without a linearization parallel resistor, RP, are shown
in Figure 8-8. Consider an example where VBIAS = 5 V, RBIAS = 100 kΩ, and a parallel resistor (RP) is used
with the NTC thermistor (RNTC) to linearize the output voltage with an additional 100-kΩ resistor. The output
characteristics of the voltage dividers are in Figure 8-9. The device produces a linear curve across the entire

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temperature range while the NTC curve is only linear across a small temperature region. When the parallel
resistor (RP) is added to the NTC circuit, the added resistor makes the curve much more linear but greatly affects
the output voltage range.

Figure 8-8. TMP61 vs NTC With Linearization Resistor (RP) Voltage Divider Circuits
5
VNTC
VTMP61
4 VNTC with RP

3
VTEMP (V)

0
-60 -40 -20 0 20 40 60 80 100 120 140 160
Temperature (qC) d012

Figure 8-9. NTC With and Without a Linearization Resistor vs TMP61 Temperature Voltages

8.2.1.2.1 Thermal Protection With Comparator

Use the TMP61 device along with a voltage reference, and a comparator to program the thermal protection.
As shown in Figure 8-10, the output of the comparator remains low until the voltage of the thermistor divider,
with RBIAS and RTMP61, rises above the threshold voltage set by R1 and R2. When the output goes high, the
comparator signals an overtemperature warning signal. The engineer can also program the hysteresis to prevent
the output from continuously toggling around the temperature threshold when the output returns low. Either a
comparator with built-in hysteresis or feedback resistors may be used.

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Figure 8-10. Temperature Switch Using TMP61 Voltage Divider and a Comparator

8.2.1.2.2 Thermal Foldback

One application that uses the output voltage of the TMP61 in an active control circuit is thermal foldback. This
is performed to reduce, or fold back, the current driving a string of LEDs, for example. At high temperatures,
the LEDs begin to heat up due to environmental conditions and self heating. Thus, at a certain temperature
threshold based on the LED's safe operating area, the driving current must be reduced to cool down the LEDs
and prevent thermal runaway. The device voltage output increases with temperature when the output is in the
lower position of the voltage divider and can provide a response used to fold back the current. Typically, the
device holds the current at a specified level until a high temperature is reached, known as the knee point,
at which the current must be rapidly reduced in order to continue operation. To better control the temperature/
voltage sensitivity, the device uses a rail-to-rail operational amplifier. Figure 8-11 shows the temperature knee
point where the foldback begins. The set by the reference voltage (2.5 V) at the positive input, and the feedback
resistors set the response of the foldback curve. The foldback knee point may be chosen based on the output of
the voltage divider and the corresponding temperature from Equation 5 (110°C, for example). The device uses a
buffer between the voltage divider with RTMP61 and the input to the op amp to prevent loading and variations in
VTEMP.

Figure 8-11. Thermal Foldback Using TMP61 Voltage Divider and a Rail-to-Rail Op Amp

14 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TMP61

 TMP61
www.ti.com SBOS921F – DECEMBER 2018 – REVISED NOVEMBER 2023

The op amp remains high as long as the voltage output is below VREF. When the temperature goes above
110°C, the output falls to the 0-V rail of the op amp. The rate at which the foldback occurs depends on the
feedback network, RFB and R1, which varies the gain of the op amp, G, as shown in Equation 6. The foldback
behavior controls the voltage and temperature sensitivity of the circuit. The device feeds this voltage output into
a LED driver circuit that adjusts output current accordingly. VOUT is the final output voltage used for thermal
foldback and is calculated in Equation 7. Figure 8-12 describes the output voltage curve in this example which
sets the knee point at 110°C.

§ RTMP61 ·
VTEMP = VBIAS × ¨ ¸
© RTMP61+ RBIAS ¹ (5)

RFB
G=
R1 (6)

VOUT G× VTEMP + (1+ G) × VREF (7)

6

4
VTEMP (V)

0
0 25 50 75 100 125 150
Temperature (qC) D014

Figure 8-12. Thermal Foldback Voltage Output Curve

8.2.1.3 Application Curve

The TMP61 accuracy varies depending on the selected biasing circuit. This variation can be seen in Figure 8-13.
VTEMP is shown with either VBIAS at 2 V in a resistor divider circuit (RBIAS = 10 kΩ ±1%) or IBIAS at 200 µA.
Supply sources used are assumed to be ideal. The best accuracy is achieved using a direct current bias method.
7 5.6
VTemp (IBIAS= 200 PA)
6 VTemp (VBIAS = 2 V) 4.8
Error (qC) (IBIAS = 200 PA)
Error (qC) (VBIAS = 2 V)
5 4
VTEMP (V)

Error (qC)

4 3.2

3 2.4

2 1.6

1 0.8

0 0
-60 -40 -20 0 20 40 60 80 100 120 140 160
Temperature (qC) d011

Figure 8-13. TMP61 Voltage Output and Temperature Error Based on the Bias Method

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15

Product Folder Links: TMP61
TMP61
SBOS921F – DECEMBER 2018 – REVISED NOVEMBER 2023 www.ti.com

8.3 Power Supply Recommendations

The maximum recommended operating voltage of the TMP61 is 5.5 V (VSNS), and the maximum current through
the device is 400 µA (ISNS).
8.4 Layout
8.4.1 Layout Guidelines
The layout of the TMP61 is similar to that of a passive component. If the device is biased with a current source,
the positive pin 2 is connected to the source, while the negative pin 1 is connected to ground. If the circuit is
biased with a voltage source, and the device is placed on the lower side of the resistor divider, V– is connected
to ground and V+ is connected to the output, VTEMP. If the device is placed on the upper side of the divider, V+ is
connected to the voltage source and V– is connected to the output voltage, VTEMP.
8.4.2 Layout Example

Figure 8-14. Recommended Layout: DEC Package

16 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TMP61

 TMP61
www.ti.com SBOS921F – DECEMBER 2018 – REVISED NOVEMBER 2023

9 Device and Documentation Support

9.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
9.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.4 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (February 2019) to Revision F (November 2023) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Updated temperature support to 150°C..............................................................................................................1
• Updated Description section...............................................................................................................................1
• Updated Device Comparison Table.................................................................................................................... 2
• Added notes to pinout diagrams.........................................................................................................................3
• Changed minimum Junction Temperature from –40°C to –65°C in Absolute Maximum Ratings table ............. 4
• Changed Max Storage Temperature from 150°C to 155°C in Recommended Operating Conditions ............... 4
• Changed Max Ambient Temperature from 125 °C to 150 °C for DYA package in Recommended Operating
Conditions ..........................................................................................................................................................4
• Added 1000 hour Long Term Drift specification for DYA package......................................................................5
• Added LPG Thermal response........................................................................................................................... 5
• Updated Typical Characteristics curves............................................................................................................. 6
• Moved the Power Supply Recommendations and Layout sections to the Application and Implementation
section.............................................................................................................................................................. 16

Changes from Revision D (December 2019) to Revision E (February 2020) Page

• Updated Features list......................................................................................................................................... 1
• Updated Applications list.................................................................................................................................... 1
• Updated Description........................................................................................................................................... 1
• Changed Maximum temperature of DEC package in Device Comparison Table from 150°C to 125°C.............2
• Changed Max Junction Temperature from 150°C to 155°C in Recommended Operating Conditions .............. 4
• Added 'Long Term Drift ' for DYA package......................................................................................................... 5
• Changed min spec 'Long Term Drift' for RH = 86 % from 0.1 % to -1 %............................................................5
Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17
Product Folder Links: TMP61
TMP61
SBOS921F – DECEMBER 2018 – REVISED NOVEMBER 2023 www.ti.com

• Added typical spec 'Long Term Drift' for RH = 86 %...........................................................................................5

• Changed max spec 'Long Term Drift' for RH = 86 % from 0.8 % to 1 %............................................................ 5
• Changed min spec 'Long Term Drift' for DEC package from 0.1 % to -1 %...................................................... 5
• Added typical spec 'Long Term Drift' for DEC package'..................................................................................... 5
• Changed max spec 'Long Term Drift' for RH = 86 % from 1 % to 1.8 %............................................................ 5
• Added typical spec 'Long Term Drift' for LPG package...................................................................................... 5
• Changed max spec 'Long Term Drift' for RH = 86 % from 1.1 % to 1.4 %......................................................... 5
• Updated Overview section..................................................................................................................................8
• Added TMP61 R-T Table section........................................................................................................................9
• Updated Feature Description section................................................................................................................. 9
• Removed Transfer Tables...................................................................................................................................9
• Updated Application and implementation section to match TI data sheet standards....................................... 10
• Added link to Thermistor Design tool................................................................................................................10
• Removed Thermal Compensation section........................................................................................................11

Changes from Revision C (September 2019) to Revision D (December 2019) Page

• Removed preview notice from the SOT-5X3 package........................................................................................1

Changes from Revision B (July 2019) to Revision C (September 2019) Page

• Added preview SOT-5X3 package..................................................................................................................... 1

Changes from Revision A (June 2019) to Revision B (July 2019) Page

• Changed Application bullets............................................................................................................................... 1
• Increased ESD CDM Rating...............................................................................................................................4
• Removed 'Functional, Unspecified Performance' rows...................................................................................... 4
• Removed 'Functional, Unspecified Performance' rows...................................................................................... 4
• Added Thermal Information for LPG Package....................................................................................................4
• Added 'Long Term Drift' spec for LPG package..................................................................................................5
• Added transfer tables for the LPG package....................................................................................................... 9
• Changed Layout Example section ...................................................................................................................16

Changes from Revision * (December 2018) to Revision A (June 2019) Page

• Changed data sheet status from Production Mixed to Production Data.............................................................1

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

18 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TMP61

 PACKAGE OPTION ADDENDUM

www.ti.com 20-Aug-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TMP6131DECR ACTIVE X1SON DEC 2 10000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 EL Samples

TMP6131DYAR ACTIVE SOT-5X3 DYA 2 3000 RoHS & Green SN Level-3-260C-168 HR -40 to 125 1GK Samples

TMP6131DYAT OBSOLETE SOT-5X3 DYA 2 TBD Call TI Call TI -40 to 125 1GK
TMP6131LPGM ACTIVE TO-92 LPG 2 3000 RoHS & Green SN N / A for Pkg Type -40 to 150 TMP61 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 20-Aug-2024

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TMP61 :

• Automotive : TMP61-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Feb-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMP6131DECR X1SON DEC 2 10000 178.0 8.4 0.7 1.15 0.47 2.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Feb-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TMP6131DECR X1SON DEC 2 10000 205.0 200.0 33.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DEC0002A SCALE 11.000
X1SON - 0.5 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

1.05 B
A
0.95

PIN 1 INDEX AREA

0.65
0.55

0.50
0.41
C

SEATING PLANE
0.05
0.00 0.03 C

0.65

1 2
SYMM
0.55
2X
0.45
0.1 C A B

PIN 1 ID SYMM
(45 X0.125) 0.3
2X
0.2
0.1 C A B

4224506/A 08/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
DEC0002A X1SON - 0.5 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

2X (0.25) SYMM

SYMM
2X (0.5)

(R0.05) TYP
(0.65)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:60X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
METAL EDGE
METAL UNDER
EXPOSED SOLDER MASK
METAL
EXPOSED
METAL SOLDER MASK SOLDER MASK
OPENING OPENING

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4224506/A 08/2018

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
DEC0002A X1SON - 0.5 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

2X (0.3) (0.05)
SYMM

PCB PAD METAL

UNDER SOLDER PASTE

SYMM
2X (0.5)
1 2

(R0.05) TYP
(0.7)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:60X

4224506/A 08/2018
NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
DYA0002A SOT (SOD-523) - 0.77 mm max height
PLASTIC SMALL OUTLINE

1.7
1.5
A PIN 1
ID AREA

0.85
0.75 2
1
NOTE 3

1.3 0.3 2X 0 -10 0.7

B 2X TYP
1.1 0.1 0.5

2X 8 -10

0.77 MAX
C

SEATING PLANE

0.15
2X 0.05 C
0.08

SYMM

SYMM

0.35
2X
0.25
0.1 C A B
0.4 0.05
2X
0.2

4224978/C 11/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEITA SC-79 registration except for package height

www.ti.com
 EXAMPLE BOARD LAYOUT
DYA0002A SOT (SOD-523) - 0.77 mm max height
PLASTIC SMALL OUTLINE

SYMM
2X (0.67) (R0.05) TYP

1 2 SYMM
2X (0.4)

(1.48)

LAND PATTERN EXAMPLE

SCALE:40X

0.05 MAX 0.05 MIN

AROUND AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDERMASK DETAILS

4224978/C 11/2024

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DYA0002A SOT (SOD-523) - 0.77 mm max height
PLASTIC SMALL OUTLINE

2X (0.67) SYMM
(R0.05) TYP

1 2 SYMM
2X (0.4)

(1.48)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:40X

4224978/C 11/2024

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
LPG0002A SCALE 1.300
TO-92 - 5.05 mm max height
TRANSISTOR OUTLINE

4.1
3.9

3.25
3.05 0.51
3X
0.40 5.05
MAX
1 2
2.3 2 MAX
2.0

6X 0.076 MAX

15.5
2X
15.1

0.48 0.51
3X 3X
0.33 0.33
2X 1.27 0.05
2.64
2.44

2.68
2.28
1.62
2X (45 ) 1.42

1 2
(0.55) 0.86
0.66
4221971/B 06/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
LPG0002A TO-92 - 5.05 mm max height
TRANSISTOR OUTLINE

0.05 MAX (1.07) METAL 3X (R0.38) VIA

ALL AROUND TYP
TYP

(1.7) (1.7)

1 2
(R0.05) TYP (1.07)
(1.27)
SOLDER MASK
OPENING (2.54)

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE:20X

4221971/B 06/2022

www.ti.com
 TAPE SPECIFICATIONS
LPG0002A TO-92 - 5.05 mm max height
TRANSISTOR OUTLINE

0 1
13.0 0 1
12.4

1 MAX
21
18

2.5 MIN
6.5
5.5
9.5
8.5 0.25
0.15

19.0
17.5

3.8-4.2 TYP 0.45

6.55 12.9 0.35
6.15 12.5

4221971/B 06/2022

www.ti.com
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