Huber2008 (1)
Huber2008 (1)
Abstract - A systematic analysis of line current distortions of II. ANALYSIS OF LINE CURRENT DISTORTIONS
the DCM/CCM boundary boost PFC converter due to valley
switching and switching-frequency limitation is provided. When the boost converter, shown in Fig. 1, operates at the
Closed form expressions for the line current are derived. It is DCM/CCM boundary with a constant on-time Ton of boost
shown that if the switching frequency is limited and valley switch SB, the line current follows the line voltage. In fact,
switching is not maintained, the line current is more distorted line current iin is equal to the inductor current iLB averaged
with voltage mode control than with current mode control. The over a switching period Tsw, i.e.,
effects of line current distortions are demonstrated with both
simulation and experimental results. v T
iin = 〈iLB 〉 Tsw = in on (1)
2 LB
I. INTRODUCTION
where vin = 2 Vin, rms sin(ω L t ) . On-time Ton is determined
In low-power, off-line power supplies, a boost converter
as
operating at the boundary of discontinuous conduction mode
(DCM) and continuous conduction mode (CCM) is a popular 2 LB Po
Ton = , (2)
topology for implementing the front-end converter with ηVin2, rms
active power-factor correction (PFC) [1]-[6]. The major
benefit of the DCM/CCM boundary boost converter, where, η = Po / Pin .
compared to the CCM boost converter, is that the reverse- However, operating at the DCM/CCM boundary, switch SB
recovery losses related to the boost diode are eliminated. In turns on with hard switching, as shown in Fig. 2(a), resulting
addition, turn-on with zero-voltage switching (ZVS) or near in elevated turn-on losses. The turn-on losses can be
ZVS of the boost switch, also called valley switching, can be significantly reduced or even completely eliminated if the
easily achieved. A major drawback of the DCM/CCM boost turn-on instant of switch SB is delayed until its drain-source
converter is that its switching frequency, which changes as a voltage vDS resonates down to a valley (when vin > Vo/2) or to
function of line and load, varies over a wide range leading to zero (when vin < Vo/2), as shown in Fig. 2(b). This additional
excessive turn-off switching loss of the main switch, as well delay Td, which is due to the parasitic capacitances (e.g., Coss)
as excessive core and winding loss of the inductor. This resonating with boost inductor LB, increases the turn-off time
becomes a significant problem at light loads, where most of the switch and introduces line current distortions, i.e.
consumer products are required to meet the Energy Star
vin Ton 1
standards [7] and/or the 80-plus program [8]. Generally, iin = ⋅ . (3)
switching losses can be controlled by limiting the switching 2LB T ⎛ vin ⎞
1+ d ⎜
⋅ ⎜1 − ⎟
⎟
frequency. However, by limiting the switching frequency, Ton ⎝ Vo ⎠
the line current becomes distorted resulting in decreased
power factor (PF) and increased total harmonic distortion It follows from (3) that delay time Td related line current
(THD). In addition, ZVS of the main switch can be lost, distortions are more pronounced around the zero crossing of
which degrades the efficiency and leads to excessive i in Lin i LB LB DB
electromagnetic-interferance (EMI) noise and, therefore,
additional input filtration is needed.
This paper presents a systematic analysis of the line current C in Co R L VO
v in SB C oss v DS
distortions of the DCM/CCM boundary boost PFC converter
due to valley switching and switching-frequency limitation.
The effects of line current distortions are demonstrated with
both simulation and experimental results. Fig. 1 Simplified circuit diagram of PFC boost converter
t t
(a) (b) 0
Fig. 2 Key switching waveforms of DCM/CCM boundary operation 0 45 90 135 180
(a) without delay (b) with delay Td θ = ω Lt [ o]
the line voltage vin and at light load where Ton is minimal. Fig. 4 Normalized line current waveforms as a function of normalized
Normalized line current waveforms as a function of the delay time Td,norm at 230-Vrms line voltage and 385-V output voltage.
normalized delay time (Td,norm=Td/Ton) at 115-Vrms and 230- Using (2), the switching frequency is determined as
Vrms line voltages (nominal low-line and high-line voltages),
at 385-V output voltage, are presented in Figs. 3 and 4, Vin2, rms ⎛ vin ⎞
f sw = η ⋅ ⎜1 − ⎟⎟ . (6)
respectively. 2 LB Po ⎜⎝ Vo ⎠
The line current distortion can be quantitatively expressed
by the power factor, defined as It follows from (6) that, for example, at 230-Vrms line
Pin voltage, 385-V output voltage, and a constant load, the
PF = . (4) switching frequency over a half-line cycle varies more than
Vin, rms ⋅ I in, rms
six times, whereas a ten times change in load will lead to
Power factor values corresponding to the line current approximately a ten times change in the switching frequency.
waveforms in Figs. 3 and 4 are shown in Table I. It can be At light loads, the switching frequency can become very high
concluded from Table I that delay time Td related line current and, therefore, it is desirable to limit it in order to decrease
distortions are practically negligible. the switching losses, which include the boost switch turn-off
and, eventually, turn-on losses, gate drive loss, and the
When the boost converter operates at the DCM/CCM
inductor core and copper loss.
boundary with constant on-time Ton, the switching frequency
changes as When operating with a switching frequency limit,
1 ⎛ vin ⎞ generally, the boost switch can operate with or without valley
f sw = ⋅ ⎜1 − ⎟ . (5) switching. If operating with valley switching, the boost
Ton ⎜⎝ Vo ⎟⎠
switch can maintain valley switching or it can lose valley
switching after the onset of the switching frequency limit,
1 depending on the employed control method.
T d,norm = 0
If a switching frequency limit is implemented and the
0.5 boost switch always operates without valley switching, the
0.75
1 line current is determined as
5
i in,norm 0.5 ⎧ vinTon vin
⎪ 2L if > 1 − Ton f sw, max
B V o
⎪⎪
iin = ⎨ vinTon Ton f sw, max vin . (7)
0.25 ⎪ 2L ⋅ v
if
V
≤ 1 − Ton f sw, max
⎪ B 1 − in o
⎪⎩ Vo
0
0 45 90 135 180
Normalized line current waveforms as a function of the
θ = ω Lt [ o ] normalized on time (Ton,norm=Ton fsw,max) at 230-Vrms line
Fig. 3 Normalized line current waveforms as a function of normalized voltage and 385-V output voltage are presented in Fig. 5. It
delay time Td,norm at 115-Vrms line voltage and 385-V output voltage.
703
1 vGS
w/o SFL T on,norm = 0.155
t
0.2 (a)
0.75 0.3 i LB
0.4
t
i in,norm 0.5 Tswmin Tswmin
0.5
vGS
t
0.25 (b)
i LB
0 t
0 45 90 135 180
Tswmin Tswmin
θ = ω Lt [ o] Fig. 6 Key switching waveforms of DCM/CCM boundary boost with
Fig. 5 Normalized line current waveforms for different switching switching frequency limit (a) voltage mode control (b) current mode
frequency limits (SFLs) (i.e., as a function of normalized on time control.
Ton,norm=Ton fsw,max) at 230-Vrms line voltage and 385-V output voltage. suggested in [9], the additional power loss due to the snubber
should be noted that the switching frequency is typically is undesirable.
limited in the high line-voltage range. If a switching frequency limit is implemented and the
Power factor values corresponding to the line current boost switch operates with valley switching until the onset of
waveforms in Fig. 5 are shown in Table II. It can be seen in the switching frequency limit, the line current is determined
Table II that in the case where the switching frequency is as
limited in the entire half-line cycle, the power factor is
limited to 0.9369. ⎧ vinTon 1 vin
⎪ 2L ⋅ if > 1 − A1
The line current expression in (7) is obtained by neglecting Td ⎛ vin ⎞ Vo
the oscillation of the boost inductor current after the reset of ⎪ B
1+ ⋅ ⎜1 − ⎟⎟
⎪ Ton ⎜⎝ Vo ⎠
the boost inductor. If the oscillation of the boost inductor iin = ⎨ , (8)
current is also taken into consideration, it can be easily shown ⎪ vinTon Ton f sw, max vin
⋅ if ≤ 1 − A1
that the line current distortion depends on the control method ⎪ 2 LB vin Vo
⎪ 1−
used. When voltage mode control is used, the peak inductor ⎩ Vo
current depends on the initial value of the inductor current
during the resonant interval at the moment switch SB is turned
where
on because the on-time Ton is constant, as shown in Fig. 6(a).
Therefore, the peak inductor current and, consequently, the Ton f sw, max
A1 = . (9)
average value of the inductor current can change abruptly 1 − Td f sw, max
between two consecutive switching cycles, resulting in
significant line-current distortions. When current mode
If a switching frequency limit is implemented and valley
control is used, the peak inductor current is constant, and,
switching is always maintained, additional distortions in the
instead, on-time Ton changes, but only slightly, resulting in
line current are introduced, as follows from Fig. 7. In fact, if
approximately the same averaged value of the inductor
the first valley in the present switching period occurs just
current in two consecutive switching cycles, as shown in Fig.
after interval Tsw,min = 1/fsw,max, switch SB turns on at the first
6(b). Consequently, the line current is only slightly distorted.
valley; however, if the first valley in the next switching
By reducing the amplitude of the resonant current, e.g., by
period occurs just before interval Tsw,min, the turn-on of switch
selecting a switch with lower output capacitance, the line-
SB is delayed until the second valley (also called valley
current distortion can be further reduced. Although damping
skipping), resulting in an abrupt change in the averaged
of the resonance is possible using an RCD snubber as
inductor current and, therefore, in an abrupt change in the line
current. The line current waveform is determined as
TABLE I
POWER FACTOR VS NORMALIZED DELAY TIME AT NOMINAL
LOW-LINE AND HIGH-LINE VOLTAGES (Vo = 385 V) TABLE II
POWER FACTOR VS NORMALIZED ON TIME AT 230-Vrms
Vin,rms Td,norm = Td /Ton NOMINAL HIGH-LINE VOLTAGE (Vo = 385 V)
[V]
0 0.5 1 5 Ton,norm = Ton fsw,max ≤ 0.155 0.2 0.3 0.4 0.5
115 1 0.99965 0.99914 0.99703
PF 0.9369 0.9555 0.9828 0.9937 0.9979
230 1 0.99829 0.99515 0.97419
704
⎧ vinTon 1 v v GS
⎪ 2L ⋅ if in ≥ 1 − A1 t
⎪ B T ⎛ v ⎞ Vo Tsw1 Tsw2
1 + d ⋅ ⎜⎜1 − in ⎟⎟
⎪ Ton ⎝ Vo ⎠ T sw,min
iin = ⎨ (10)
⎪ vinTon ⋅
1
if A1 < 1 −
vin
≤ Ak i LB
⎪ 2 LB T ⎛ v ⎞ Vo
⎪ 1 + k ⋅ d ⋅ ⎜⎜1 − in ⎟⎟
⎩ Ton ⎝ Vo ⎠
t
where
v DS
Ton f sw, max
Ak = , k = 3,5,7,... . (11)
1 − k ⋅ Td f sw, max
t
Normalized line current waveforms for a 130-W, Fig. 7 Key switching waveforms of DCM/CCM boundary boost
with switching frequency limit and valley switching.
universal-input, 385-V output DCM/CCM boundary boost
PFC converter with LB = 230 μH and with 250-kHz switching
III. SIMULATION RESULTS
frequency limit are shown in Fig. 8 at 230-Vrms line voltage.
The solid-line and dash-line waveforms are for the cases To further illustrate the effect of switching frequency limit
where the valley switching is lost and where it is maintained and valley skipping on the line current waveform during the
after the onset of the switching frequency limit, respectively. entire line cycle, SIMPLIS™ simulations were performed.
Key normalized parameters of the line current waveforms in Figure 9 shows the line current waveform (in red) of a 130-
Fig. 8 are Ton,norm = Ton fsw,max = 0.2825 and W, universal-input, 385-V output, DCM/CCM boundary
Td,norm = Td /Ton = 0.422. The power factor for the line boost PFC converter with LB = 230 μH and with 250-kHz
current with valley switching always maintained is only switching frequency limit, at 230-Vrms line voltage, operating
slightly lower than the power factor for the line current with with current mode control and valley switching. The
valley switching lost after the onset of the switching switching frequency variation during the entire line cycle is
frequency limit, as shown in Fig. 8. also included in Fig. 9 (in red). It is shown in Fig. 9 that
switching frequency fsw is not firmly clamped to its limit due
The line current expression in (10) is obtained under the
to valley skipping, i.e., due to the fact that the circuit must
assumption that the valley skipping is monotonic. However,
wait for the next resonant valley before turning on. It can be
in a real circuit, in addition to the valley skipping, a jittering
seen in Fig. 9 that a discontinuity occurs in the line current
effect can be observed during a few switching cycles when
waveform whenever switching frequency fsw reaches its 250-
the switching period is approximately equal to Tsw,min, where
kHz limit. For comparison with the case without switching
the turn-on of switch SB randomly happens between two
frequency limitation, the corresponding line current
consecutive valleys. Besides the line current distortion, the
valley jittering may also result in audible noise. This valley
jittering and, consequently the audible noise, can be reduced 1
by using a sophisticated valley counting (also called anti-
w/o SFL
jittering) algorithm [10].
1 iin
w/o SFL [A] 0
fsw 300
[kHz]
0.25
200
100
0 0 4 8 12 16 20
0 45 90 135 180 t [msec]
θ = ω Lt [ o]
Fig. 9 Simulation of DCM/CCM boundary boost PFC with and without
Fig. 8 Normalized line current waveforms for the case without switching switching frequency limit (SFL);
frequency limit (SFL) (in red), and for the case with switching frequency • w/o SFL: PF=0.994, THD=0.9%, fsw,avg=245 kHz
limit where valley switching (VS) is lost (in blue) and where it is • with SFL: PF=0.9795, THD=4.4%, fsw,avg=197 kHz
maintained (in black) after the onset of switching frequency limit.
705
waveform and switching frequency variation are also QG=60 nC). Although gate drive loss PG is similar in all
presented in Fig. 9 (in black). It should be noted that in the cases, capacitive turn-on loss PCon is nearly three times higher
case where the switching frequency is not limited by the when valley switching is lost. However, performing a similar
control circuit, it is nevertheless limited by the effect of the simulation at 20% load (Fig. 11) shows that gate drive loss
filter capacitor at the output of the full-bridge rectifier, which PG nearly triples when the frequency is not limited, and
prevents the rectified line voltage to decrease to zero. capacitive turn-on loss PCon nearly triples when valley
switching is lost when operating with switching frequency
It follows from Fig. 9 that the line current waveform with
limit. In addition to an increased loss, the effect of losing
switching frequency limitation is more distorted than without
valley switching is also an increased conducted EMI, which
switching frequency limitation. Calculated PF and THD
may necessitate additional filtration, that further increases the
values are also included in Fig. 9.
loss.
The benefit of limiting the switching frequency is reduced
switching loss, both in the capacitive turn-on loss PCon and IV. EXPERIMENTAL RESULTS
gate drive loss PG of switch SB, as well as the core and copper
Experimental waveforms presented in Fig. 12 illustrate the
loss of the inductor. Using simulation, drain-source voltage
line current distortions when valley switching is not
vDS a moment prior to switch SB turn-on (i.e., VCon) can be
maintained and a maximum switching frequency limit is
sampled along with switching frequency fsw and used to
implemented with voltage-mode control. The experimental
determine both turn-on loss PCon and gate-drive loss PG
waveforms in Fig. 12 were obtained on a 150-W, universal-
during a line period TL, defined as
input, 385-V output DCM/CCM boundary boost PFC
1 TL 1 2 prototype circuit controlled by the NCP1601 voltage-mode
PCon =
TL ∫0 2
f sw CossVCon dt , (12) controller IC from ON Semiconductor. The line voltage was
200-Vrms, the switching frequency limit was 133-kHz, and
and valley switching was lost after the onset of switching
1 TL frequency limit. As shown in Fig. 12(a), the boost inductor
PG = VGG QG
TL ∫0 f sw dt , (13) current iLB waveform and, consequently, the line current
waveform, contains abrupt changes around the zero crossings
respectively, where, VGG is the gate-drive voltage and QG is of the line voltage. These non-monotonic distortions are due
the total gate charge. Simulated waveforms during a half-line to the abrupt increase in the peak of the inductor current, as
cycle and calculation results are presented in Fig. 10 for three illustrated in Fig. 12(b), which is a result of the inductor
cases: without switching frequency limit with valley current increasing from zero at the start of one switching
switching (in black); and switching frequency limit cycle, and then increasing from a positive value at the start of
fsw,max = 250 kHz, with (in red) and without (in blue) valley the next switching cycle.
switching. The simulation was performed at 230-Vrms line Experimental waveforms presented in Fig. 13 illustrate that
voltage and full load, i.e., 130 W (VGG=15V, Coss=100pF, and there is minimal line current distortion when valley switching
400 400
with SFL
loss of VS with SFL
300 300
loss of VS
vCon vCon
200 200
[V] [V] with SFL and VS
100 100
with and w/o SFL
0 with VS 0 w/o SFL, with VS
500 1000
w/o SFL
800
400 with VS
f sw 300
with SFL
loss of VS f sw
[kHz] with SFL
[kHz] 400 loss of VS
200
with SFL and VS
100 with SFL and VS
100
0 2 4 6 8 10 0 2 4 6 8 10
t [msec] t [msec]
Fig. 10 Simulation of drain-source voltage just prior to switch SB turn Fig. 11 Simulation of drain-source voltage just prior to switch SB turn on
on (i.e., VCon) and switching frequency fsw with and without switching (i.e., VCon) and switching frequency fsw with and without switching
frequency limit (SFL) and valley switching (VS) at full load; frequency limit (SFL) and valley switching (VS) at 20% load;
• w/o SFL and VS: fsw,avg=245 kHz, PCon=0.16 W, PG=0.24 W • w/o SFL and VS: fsw,avg=728 kHz, PCon=0.57 W, PG=0.66 W
• with SFL and VS: fsw,avg=197 kHz, PCon=0.15 W, PG=0.18 W • with SFL and VS: fsw,avg=230 kHz, PCon=0.24 W, PG=0.21 W
• with SFL and loss of VS: fsw,avg=209 kHz, PCon=0.41 W, PG=0.19 W • with SFL and loss of VS: fsw,avg=243 kHz, PCon=0.74 W, PG=0.22 W
706
Fig. 12 Key experimental waveforms of 150-W/385-V, universal input Fig. 13 Key experimental waveforms of 130-W/385-V, universal input
DCM/CCM boundary boost PFC with voltage mode control, 133-kHz DCM/CCM boundary boost PFC with current mode control, 180-kHz
switching frequency limit, and loss of valley switching after the onset of switching frequency limit, and loss of valley switching after the onset of
switching frequency limit (a) during a line cycle (b) zoomed in around switching frequency limit (a) during a line cycle (b) zoomed in around
instant T1. instant T1.
707
REFERENCES applications – an overview," IEEE Trans. Industrial
Electronics, vol. 52, no. 3, pp. 701-708, Jun. 2005.
[1] J.S. Lai and D. Chen, "Design consideration for power factor
correction boost converter operating at the boundary of [6] J.W. Kim, S.M. Choi, and K.T. Kim, "Variable on-time
continuous conduction mode and discontinuous conduction control of the critical conduction mode boost power factor
mode," IEEE Applied Power Electronics Conf. (APEC) Proc., correction converter to improve zero-crossing distortion,"
pp. 267-273, Mar. 1993. IEEE Power Electronics and Drive Systems Conf. (PEDS)
Proc., pp. 1542-1546, Nov. 2005.
[2] J. Sebastian, J.A. Cobos, J.M. Lopera, and J. Uceda, "The
determination of the boundaries between continuous and [7] Environmental Protection Agency (EPA) Energy Star
discontinuous modes in pwm dc-to-dc converters used as Program, http://www.energystar.gov/index.cfm?c=revisions.
power factor preregulators," IEEE Trans. Power Electronics, computer_spec
vol. 10, no. 5, pp. 574-582, Sep. 1995.
[8] 80Plus Program, http://www.80plus.org/
[3] J. Zhang, J. Shao, F.C. Lee, and M.M. Jovanović, “Evaluation
[9] K. De Gusseme, D. M. Van de Sype, A. P. M. Van den
of input current in the critical mode boost PFC converter for
Bossche, and J. A. Melkebeek, "Input-current distortion of
distributed power systems,” IEEE Applied Power Electronics
ccm boost pfc converters operated in dcm," IEEE Trans.
Conf. (APEC) Proc., pp. 130-136, Feb. 2001.
Industrial Electronics, vol. 54, no. 2, pp. 858-865, Apr. 2007.
[4] M. Gotfryd, "Limits in boost power factor corrector operating
[10] P. Preller, "A controller family for switch mode power
in border-line mode," IEEE Trans. Power Electronics, vol. 18,
supplies supporting low power standby and power factor
no. 6, pp. 1330-1335, Nov. 2003.
correction", Infineon Technologies AG, Application Note AN-
[5] M.M. Jovanović and Y. Jang, "State-of-the-art, single-phase, TDA 1684X, Jun. 2000.
active power-factor-correction techniques for high-power
708