UNLOCKING INNOVATION

WITH COST-OPTIMIZED
FPGAs AND ADAPTIVE SOCS
ELEVATE YOUR DESIGN WITHOUT
COMPROMISING ON PERFORMANCE
OR EFFICIENCY
 UNLOCKING INNOVATION WITH COST-OPTIMIZED FPGAS | 2

OVERVIEW 2
Overview
CURRENT TRENDS AND
CHALLENGES IN
ELECTRONICS DESIGN 3
With innovations like the Internet of Things (IoT),
THE PROGRAMMABLE LOGIC machine vision, and AI at the edge, developers need new
ADVANTAGE 5 architectures that are more flexible, energy efficient, and
low cost. This ebook clarifies the differences between
ADAPTIVE COMPUTING: FPGAs, adaptive SoCs, ASICs, and other standard
MORE THAN
PROGRAMMABLE LOGIC 6 processors to help innovators decide which approach is best
for their application.
THE AMD COST-OPTIMIZED
The primary focus of this ebook is to introduce readers
PORTFOLIO OF FPGAS 8
to cost-optimized FPGA and adaptive SoC technologies
and show how they can bring the flexibility of software
SPARTAN™ ULTRASCALE+
FAMILY 11 programmability to hardware design without compromising
performance or efficiency.
SELECTING THE RIGHT
PROGRAMMABLE DEVICE 13 The ebook will also introduce the future of AMD cost-
optimized devices and explore how the company’s
long-term commitment to a cost-optimized portfolio
SELECTING THE RIGHT
PARTNER 14 (COP) of low-density and mid-range FPGAs helps deliver
the advantages of programmable logic to nearly every
AMD – THE FPGA LEADER 15 application.

FPGAS FOR ARTIFICIAL

INTELLIGENCE AND
MACHINE LEARNING 16

COST-OPTIMIZED FPGA
APPLICATIONS 17

SUMMARY 18

MORE RESOURCES 19
 UNLOCKING INNOVATION WITH COST-OPTIMIZED FPGAS | 3

OVERVIEW 2
Current Trends and Challenges in Electronics Design
CURRENT TRENDS AND
CHALLENGES IN
ELECTRONICS DESIGN 3 Each wave of innovation opens the door to new applications AI at the Edge: One of the most important benefits enabled the same time, however, it has created new problems for
and new design challenges. These are some of the current by IoT is the availability of data to drive artificial intelligence developers to overcome, such as managing wired/wireless
THE PROGRAMMABLE LOGIC industry and technology trends driving the electronics (AI). As AI moves towards the edge, devices need to become connections, managing huge amounts of data, and securing
ADVANTAGE 5 industry today. smarter and more capable to implement or support AI data, to name a few. Developers will need to address many
further up the line. Low latency – from collecting sensor data of the following challenges in the coming years:
ADAPTIVE COMPUTING: TRENDS to processing it and acting on it – is required to provide real-
MORE THAN Flexibility: Adaptability is perhaps the most important
time responsiveness.
PROGRAMMABLE LOGIC 6 I/O: The benefits of being connected indicate that nearly design challenge developers must overcome. Programmable
every embedded device could be connected in the coming solutions allow developers to easily develop and later update
THE AMD COST-OPTIMIZED years. More I/O will be needed to read all the sensors these DESIGN CHALLENGES
systems once they are deployed. Developers need the same
PORTFOLIO OF FPGAS 8 devices will connect with. Consider that the sensor market With each technological advancement, new design flexibility to adapt system hardware over time to meet
for automotive applications alone was $34.59 billion in 2022 challenges arise. For example, consider the value the Internet changing application requirements. This includes being able
SPARTAN™ ULTRASCALE+ and is projected to more than double to $76.43 billion over has brought to nearly every industry since its inception. At to change hardware after deployment.
FAMILY 11
the next 10 years.1 Real-time responsiveness allows systems
to use data immediately to improve efficiency at every level.
SELECTING THE RIGHT
PROGRAMMABLE DEVICE 13 Energy Efficiency: Energy conservation has become
increasingly more important to consumers and businesses
SELECTING THE RIGHT over the past decade. This, and the high operating cost of
PARTNER 14
powering devices, has led to a trend to minimize power
consumption in every electronic device, especially connected
AMD – THE FPGA LEADER 15
devices that are always on. The most integrated devices,
sometimes referred to as a System-on-Chip (SoC), offer
FPGAS FOR ARTIFICIAL the added advantage of consolidating functionality onto a
INTELLIGENCE AND
MACHINE LEARNING 16 single device, reducing a system’s overall form factor while
contributing to decreased energy consumption.
COST-OPTIMIZED FPGA
APPLICATIONS 17 Security: The rise of cyberattacks—and their cost to the
bottom line—has made IoT security essential. However, the
true cost of data exposure can be difficult to measure. In
SUMMARY 18
addition to immediate costs, such as fines and recovery
costs, there is the impact of potential loss of customer trust
MORE RESOURCES 19
and overall brand damage.
 UNLOCKING INNOVATION WITH COST-OPTIMIZED FPGAS | 4

OVERVIEW 2 Managing I/O: With more sensors, more I/O is required. Data Pre-Processing: As AI becomes more relevant in edge
However, standard processors are limited in the available I/O deployment, systems need to be able to handle more
CURRENT TRENDS AND they provide. Developers need an architecture that supports data, faster, both for storage and processing. Standardized
CHALLENGES IN more I/O or one that consolidates multiple data sources to a architectures are often limited in the type of data and
ELECTRONICS DESIGN 3
single I/O channel. processing they can support efficiently. Developers need
adaptable architectures that can be customized to the
THE PROGRAMMABLE LOGIC Minimize Latency: Latency impacts both performance and application, data, and use-case at hand.
ADVANTAGE 5 power efficiency. To achieve real-time responsiveness,
systems need to be optimized at every level to minimize Future-Ready: The rapid pace of innovation has accelerated
ADAPTIVE COMPUTING: latency. The faster data can be collected, stored, and/or how often systems need to be updated. Instead of software
MORE THAN
PROGRAMMABLE LOGIC 6 transferred directly affects how quickly devices can respond being updated once a year, many systems need to be
and how much power they consume. updated much more frequently. The reasons for updates
THE AMD COST-OPTIMIZED vary, including:
Evolving Security: Security is a moving target. New
PORTFOLIO OF FPGAS 8
vulnerabilities are uncovered regularly, and any robust • Implementing bug fixes
security system needs to be able to evolve to protect against
SPARTAN™ ULTRASCALE+ • Adding new functionality
FAMILY 11 them. Furthermore, to be secure, connected systems must
protect not just their data but their code and operations as • Shoring up new security vulnerabilities

SELECTING THE RIGHT well. Security must also be properly implemented to avoid • Incrementally improving performance and efficiency
PROGRAMMABLE DEVICE 13 loading the main processing chain or draining system power. through continued algorithmic development
To achieve this, developers need an architecture that is both
• Logging and collecting new operating data for predictive
SELECTING THE RIGHT efficient and flexible.
maintenance
PARTNER 14
Energy Efficiency: To address energy efficiency, developers Given the complexity of many embedded applications, some
AMD – THE FPGA LEADER 15 are being asked to design more complex systems that use parts of the system may need updating weekly or even daily.
less power. Developers need architectures that are designed The bottom line is that updates are essential. However,
for energy efficiency. However, they also need the flexibility with a traditional processor architecture, only software can
FPGAS FOR ARTIFICIAL
INTELLIGENCE AND to balance performance and cost based on their specific be updated. This limits the types of changes that can be
MACHINE LEARNING 16 application needs. implemented after a system has been deployed. Developers
need flexible architectures that extend software adaptability
COST-OPTIMIZED FPGA Smaller Form Factor: Shrinking design size requires
to hardware. AMD adaptive computing solutions allow
APPLICATIONS 17 integration and consolidation of system functionality. Ideally,
engineers to update both software and firmware even after
developers need single-chip solutions that integrate all the
deployment.
SUMMARY 18 necessary capabilities on the same device. This not only
reduces system size, it can result in higher performance and
MORE RESOURCES 19 better energy efficiency since operations don’t incur the
latency and added power required to go off-chip. In addition,
reducing component count simplifies and speeds system
design.
 UNLOCKING INNOVATION WITH COST-OPTIMIZED FPGAS | 5

OVERVIEW 2
The Programmable Logic Advantage
CURRENT TRENDS AND
CHALLENGES IN
ELECTRONICS DESIGN 3 For many of these design challenges, programmable logic WHAT IS AN FPGA? elements could be duplicated in parallel to accelerate
has long served as a powerful technology that brings the processing. Because only the necessary functionality
Field programmable gate array (FPGA) technology has a long
THE PROGRAMMABLE LOGIC flexibility of software programmability to hardware design was implemented on the device, efficiency and power
history. Xilinx, now a part of AMD, produced one of the first
ADVANTAGE 5 without compromising performance or efficiency. consumption could also be optimized.
commercially viable FPGAs back in 1985. This device, the
Standardized devices, such as traditional processors, are XC2064, with its programmable gates and programmable
ADAPTIVE COMPUTING:
interconnects between these gates, contributed to launch
WHAT IS AN ADAPTIVE SOC?
MORE THAN fixed-function devices. This means they are locked into the
PROGRAMMABLE LOGIC 6 capabilities they have and the functionality they can support. the programmable logic market. Adaptive SoCs are devices built around an adaptive
In addition, fixed-function devices often have features that computing architecture and design methodology. These
Programmable logic allowed designers to implement system on chips are highly integrated to provide all the
THE AMD COST-OPTIMIZED are not needed for a particular application; however, these
PORTFOLIO OF FPGAS 8 custom hardware quickly and at a low cost. These first functionality required in a single chip. With such a system,
functions still take up die space and can consume power
chips revolutionized design, bringing software flexibility to developers can also leverage whole application acceleration
even though they are not being used.
SPARTAN™ ULTRASCALE+ hardware. Developers could test circuit designs on FPGAs, (WAA) and Dynamic Function eXchange (DFX).
FAMILY 11 Adaptive Hardware (Unconfigured) Adaptive Hardware (Configured) putting them into production systems to verify operation
AF1 AF2 and work out any bugs. When the design was approved, WAA is a design approach where developers optimize and
SELECTING THE RIGHT developers could move to a custom ASIC with confidence. accelerate processing across the entire application. Rather
PROGRAMMABLE DEVICE 13 AF3 AF5a This workflow accelerated how fast developers could bring than creating a chain of individually optimized subsystems,
complex products to market. the entire system is implemented in a manner where it
SELECTING THE RIGHT BF1 AF4 AF5b AF6
can be accelerated in concert with each of its components,
PARTNER 14 For many applications, the flexibility of programmable logic potentially yielding significant improvements.
BF2 BF3 BF4 BF5
was important enough to implement the FPGA in the final
AMD – THE FPGA LEADER 15 production system, bypassing a custom ASIC. FPGAs could DFX is an approach to design that reallocates system
Programmable logic allows developers to customize be reprogrammed in the field, enabling “hardware” circuits to resources that are currently not in use to another task
hardware for their particular application. Only the be updated as easily as software. that can use them. Similar to the way a micro controller
FPGAS FOR ARTIFICIAL
INTELLIGENCE AND functionality that is needed is implemented in the device. unit (MCU) can change functionality by running different
MACHINE LEARNING 16 In addition, custom logic, such as a data pre-processor, Since 1985, FPGA technology has evolved to integrate a wide software, DFX changes an FPGA’s functionality by
can be integrated into the processing chain to significantly variety of functionality and capabilities. For example, as gate reconfiguring sections of programmable logic while the rest
COST-OPTIMIZED FPGA accelerate system throughput. count increased, FPGAs were able to contain a complete of the design continues to run.
APPLICATIONS 17 embedded processor. This processor could be customized
for a specific application, enabling designers to optimize Next-generation FPGAs and adaptive SoCs continue to
SUMMARY 18 performance to meet real-time requirements. For functions integrate new capabilities that are essential for modern
where latency and throughput were critical, processing
MORE RESOURCES 19
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OVERVIEW 2
Adaptive Computing: More Than Programmable Logic
CURRENT TRENDS AND
CHALLENGES IN
ELECTRONICS DESIGN 3 embedded applications. The original FPGAs required SOFTWARE FLEXIBILITY existing functionality.
designers to work with hardware design tools similar to
To achieve high performance, ultra-low latency, or low Rather than take on the cost and delay of designing an ASIC,
THE PROGRAMMABLE LOGIC those used to layout a custom ASIC. With modern FPGA
power consumption, hardware acceleration is essential. For designers have the option to build their applications on an
ADVANTAGE 5 development tools, it's even possible to leverage FPGA
example, object detection on an assembly line and speech adaptive computing platform. Instead of utilizing fixed-
technology without writing low-level code.
recognition both require complex algorithms. The application function hardware – including coprocessors such as DSPs and
ADAPTIVE COMPUTING:
MORE THAN Rather than build systems from scratch, developers can architecture must be customized to achieve optimal GPUs – functionality is implemented using programmable
PROGRAMMABLE LOGIC 6 leverage an extensive AMD IP catalog. Developers can select performance and efficiency. Many designers optimize logic.
from a wide range of production-ready IP blocks to greatly processing by designing their own ASIC or SoC.
THE AMD COST-OPTIMIZED The core of adaptive computing is that processing must also
simplify and accelerate FPGA design.
PORTFOLIO OF FPGAS 8 When taking an ASIC approach, however, developers need be able to adapt to changes in the application requirements,
With these IP blocks, developers can implement functionality upwards of 18 months to implement a new design. In data, and algorithms used for processing. For example,
SPARTAN™ ULTRASCALE+ quickly and easily. All the necessary code has already been addition, legacy devices in the field are locked into their
FAMILY 11 written, tested, and proven in real-world applications.
Developers just need to drag-and-drop the blocks they
SELECTING THE RIGHT want. The development platform makes it easy to partition
PROGRAMMABLE DEVICE 13
functionality, build a fabric, and connect blocks to create
custom circuits that optimize performance.
SELECTING THE RIGHT
PARTNER 14 The AMD IP catalog includes more than 70 different IP
offerings, such as MicroBlaze™, MicroBlaze™ V based on
AMD – THE FPGA LEADER 15 RISC-V instruction set, Ethernet, 1/10/25GigE Vision, PCI
Express®, CAN, SPI, I2C, and more.
FPGAS FOR ARTIFICIAL
INTELLIGENCE AND With such a wide variety of IP blocks available, developers
MACHINE LEARNING 16 can quickly build custom systems optimized for their
applications. Full example designs are available as well, for a
COST-OPTIMIZED FPGA wide range of applications, including:
APPLICATIONS 17
• AMD MicroBlaze™ V Reference Design
SUMMARY 18 • PWM Controller Reference Design
• SPI Flash Controller Reference Design:
MORE RESOURCES 19
• UART Communication Reference Design

HARDWARE PERFORMANCE WITH

 UNLOCKING INNOVATION WITH COST-OPTIMIZED FPGAS | 7

SIDEBAR
OVERVIEW 2
AMD Vivado Design Suite: TM applications like AI and embedded vision continue to evolve,
and the algorithms underlying them are also changing.
FPGA vendors to provide hardened memory controllers to
optimize performance and power efficiency for FPGA-based
CURRENT TRENDS AND The Streamlined Production An adaptive computing platform, such as an FPGA or applications using external memory.
CHALLENGES IN
ELECTRONICS DESIGN 3 Development Platform for adaptive SoC, enables any changes to be carried forward to
ensure that the application continues to provide optimized
Below is a list of hardened resources:

THE PROGRAMMABLE LOGIC

FPGA Design performance and ultra-low latency long after it has been • Hardened LPDDR4x/5
deployed. The result is an architecture that provides real-
ADVANTAGE 5 • Hardened PCIe®
Quality design tools time hardware performance with the implementation
and expert support can flexibility of software. • Hardened UltraRAM
ADAPTIVE COMPUTING:
MORE THAN greatly simplify and • Hardened True Random Number Generator (TRNG)
PROGRAMMABLE LOGIC 6 accelerate design. OPTIMIZED PERFORMANCE WITH
HARDENED FUNCTIONS
THE AMD COST-OPTIMIZED Faster time to market
PORTFOLIO OF FPGAS 8 While a core capability of an FPGA is programmable logic,
can translate to a market
today’s FPGAs offer much more functionality through
advantage and to reduced
SPARTAN™ ULTRASCALE+ integration. There are certain commonly used functions that
development costs
FAMILY 11 are shared by many applications, including different types of
because products can be
processors, communication protocols, security capabilities,
designed and delivered quickly.
SELECTING THE RIGHT and memory controllers. A memory controller, for example,
PROGRAMMABLE DEVICE 13 Many FPGA vendors offer tools that are unfamiliar implements an industry-standard interface. As there is
to designers. In addition, these tools don’t have no need for customization for most applications, such
SELECTING THE RIGHT maturity or proven robustness, and they often have standardized functions can be implemented as hardened
PARTNER 14 only limited IP libraries available. blocks within a specific FPGA device.

AMD – THE FPGA LEADER 15 When designing your products, you don’t want A function implemented in programmable logic is known
to have to deal with multiple tools from different as a soft function. Hardened functions are standardized
FPGAS FOR ARTIFICIAL vendors to get from concept to final design. The capabilities integrated into an FPGA. A hardened processor,
INTELLIGENCE AND AMD Vivado™ Design Suite offers an end-to-end for example, is a processor core integrated alongside the
MACHINE LEARNING 16 FPGA’s programmable logic resources, while a soft processor
development environment from linting, to synthesis,
to place and route, to timing analysis and closure, is built using the FPGA's programmable logic.
COST-OPTIMIZED FPGA to debug and simulation. Additionally, AMD offers
APPLICATIONS 17 The advantage of using a hardened function is that it
worldwide technical support to further accelerate the
offers better performance and power efficiency than a soft
design process. Click here to learn more about the
SUMMARY 18 function. In addition, it has its own dedicated I/O and doesn’t
Vivado Design Suite.
consume any of the FPGA’s programmable logic resources.
MORE RESOURCES 19
There are a variety of hardened functions available, based
on application need. To date, AMD is one of only a few
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OVERVIEW 2
The AMD Cost-Optimized Portfolio of FPGAs
CURRENT TRENDS AND
CHALLENGES IN
ELECTRONICS DESIGN 3 COST-OPTIMIZED. HIGH I/O. LOW POWER.
THE PROGRAMMABLE LOGIC FPGAs have long been used in leading-edge applications for a wide range of applications. Tens of thousands of
ADVANTAGE 5 to achieve higher performance and efficiency than is developers rely on the AMD cost-optimized portfolio to
possible with traditional architectures. Because of their provide flexible design, accelerated performance, and power
ADAPTIVE COMPUTING: flexibility, FPGAs can also be used in many low- to mid-end efficiency.
MORE THAN
PROGRAMMABLE LOGIC 6 applications such as an industrial controller, I/O expansion,
board management & control, healthcare monitoring The cost-optimized portfolio spans multiple FPGA and
devices, etc. adaptive SoC families, across multiple process nodes from
THE AMD COST-OPTIMIZED
PORTFOLIO OF FPGAS 8 45 nm to 16 nm, and also includes select AMD Zynq™ 7000
AMD is committed to FPGAs. The cost-optimized portfolio FPGA devices, such as the AMD Zync™ Z7010 FPGA. See
provides a broad scope of programmable logic products diagram below.
SPARTAN™ ULTRASCALE+
FAMILY 11

SELECTING THE RIGHT

PROGRAMMABLE DEVICE 13

SELECTING THE RIGHT

PARTNER 14

AMD – THE FPGA LEADER 15

FPGAS FOR ARTIFICIAL

INTELLIGENCE AND
MACHINE LEARNING 16

COST-OPTIMIZED FPGA
APPLICATIONS 17

SUMMARY 18

AMD Cost-Optimized FPGA portfolio.

MORE RESOURCES 19
Source: https://www.avnet.com/wps/portal/apac/products/product-highlights/xilinx-cost-optimized-portfolio/
 UNLOCKING INNOVATION WITH COST-OPTIMIZED FPGAS | 9

OVERVIEW 2 ARCHITECTURAL FEATURES

The AMD cost-optimized portfolio includes architectures
CURRENT TRENDS AND
CHALLENGES IN designed specifically to reduce cost and power
ELECTRONICS DESIGN 3 consumption. Other important architectural features that
are available on select devices include:
THE PROGRAMMABLE LOGIC
ADVANTAGE 5 Flexible I/O: The AMD Spartan™ UltraScale+™ FPGA family
provides a higher ratio of I/O to logic resources. These
ADAPTIVE COMPUTING: I/O support 3.3V standards across a range of high-speed
MORE THAN differential signaling interfaces, enabling easier integration
PROGRAMMABLE LOGIC 6 with commonly used devices.

THE AMD COST-OPTIMIZED PCIe®: With support for either PCIe Gen 3 or Gen 4 Endpoint BENEFITS low-power applications that need extensive I/O capabilities.
PORTFOLIO OF FPGAS 8 and Root Port implementations, these devices can handle
FPGAs from the cost-optimized portfolio offer significant AMD Artix™ UltraScale+™ FPGA: Offering high data
several lanes of high bandwidth traffic for transferring data
benefits, including: throughput and DSP compute capabilities, this family of
SPARTAN™ ULTRASCALE+ on- and off-chip.
FAMILY 11 FPGAs provides up to 192 Gb of aggregate bandwidth for
Cost-Optimized Performance: This portfolio of FPGAs
Integrated Memory: Block RAM provides dedicated 36 Kb systems that need to process and move large sets of data.
balances feature set with affordability through a vast
SELECTING THE RIGHT memory blocks for extreme flexibility. Each block RAM has
selection of devices that cost-effectively meet the AMD Zynq™ UltraScale+™ FPGA: Integrates an Arm®
PROGRAMMABLE DEVICE 13 two read and write ports and can be implemented as a
requirements of a wide range of applications. processor with programmable logic in a single device for
single 36 Kb memory or two 18 Kb memories. UltraRAM, up
SELECTING THE RIGHT to 14 Mb, serves as an on-chip replacement for off-board a powerful mix of performance and flexibility to optimize
Power Efficiency: These FPGAs can be used to balance
PARTNER 14 memories, enabling better overall performance. embedded processing and deliver high levels of integration,
performance and power consumption to provide the
eliminating the need for an external scalar processor.
capabilities low-power applications need without
AMD – THE FPGA LEADER 15 Internal System Monitoring: An embedded ADC is capable
compromise. AMD Spartan™ 7 FPGA: Delivering superb performance per
of monitoring internal voltage rails and device temperature
for systems where safety, security, and reliability are watt, this family of FPGAs features smaller devices with
FPGAS FOR ARTIFICIAL Small Form Factor: Embedded applications often need to
INTELLIGENCE AND critical. high I/O for design flexibility for applications such as any-
fit within tight physical constraints. The cost-optimized
MACHINE LEARNING 16 to-any connectivity, protocol conversion, bridging, sensor
portfolio provides a variety of architectures that balance
fusion, and embedded vision.
physical size with logic resources.
COST-OPTIMIZED FPGA
APPLICATIONS 17 AMD Artix™ 7 FPGA: This architecture delivers outstanding
BROAD PORTFOLIO transceiver bandwidth for power-sensitive applications with
SUMMARY 18 Each of the families that make up the cost-optimized up to sixteen 6.6 Gb/s transceivers and DDR3 support.
portfolio deliver unique value:
AMD Zynq™ 7000 FPGA: For high-performance applications,
MORE RESOURCES 19 this architecture pairs single-chip application processors
AMD Spartan™ UltraScale+™ FPGA (covered in the next
chapter): Delivers the highest I/O-to-logic ratio in the COP with the flexibility of FPGA programmable logic, which can
portfolio1,2, making this architecture ideal for cost-sensitive, help to reduce BOM cost and die-to-die latency.
Please refer to footnote SUS-001, SUS-01
 UNLOCKING INNOVATION WITH COST-OPTIMIZED FPGAS | 10

OVERVIEW 2 INCREDIBLE SCALABILITY This expansive portfolio also provides scalability so being able to leverage existing IP as well as staying with
developers can move both up and down the portfolio as the AMD Vivado™ development platform.
The cost-optimized portfolio is an essential part of AMD
CURRENT TRENDS AND their own product lines evolve. If a higher-end system
CHALLENGES IN FPGA offerings. By supporting designs from very small
needs more capabilities, there’s often an FPGA available
ELECTRONICS DESIGN 3 to mid-range systems with the cost-optimized portfolio,
with the optimal balance of resources. Similarly, if an OEM
AMD ensures that developers have access to robust
wants to create a lower-end product, they can select a
THE PROGRAMMABLE LOGIC programmable logic technology for every application.
lower-end FPGA that offers the right balance of resources
ADVANTAGE 5
The extensive breadth of the AMD FPGA and adaptive for the job.

ADAPTIVE COMPUTING: SoC product porfolio is a critical part of how the company
Finally, the breadth of the portfolio means developers likely
MORE THAN supports developers. By providing many options, developers
PROGRAMMABLE LOGIC 6 won’t need to switch between product families when they
can right-size components to balance performance, price,
expand their own product lines. The ability to use the same
and power for their application. This means developers can
THE AMD COST-OPTIMIZED FPGA family across a line brings many benefits, including
ensure programmable logic resources are used efficiently.
PORTFOLIO OF FPGAS 8

SPARTAN™ ULTRASCALE+
FAMILY 11

SELECTING THE RIGHT

PROGRAMMABLE DEVICE 13

SELECTING THE RIGHT

PARTNER 14

AMD – THE FPGA LEADER 15

FPGAS FOR ARTIFICIAL

INTELLIGENCE AND
MACHINE LEARNING 16

COST-OPTIMIZED FPGA
APPLICATIONS 17

SUMMARY 18

MORE RESOURCES 19
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OVERVIEW 2
AMD Spartan™ UltraScale+™ FPGA Family
CURRENT TRENDS AND
CHALLENGES IN
ELECTRONICS DESIGN 3 COST-OPTIMIZED, HIGH I/O, LOW POWER, FPGAS WITH SECURITY FEATURES
THE PROGRAMMABLE LOGIC FAMILY FEATURES
ADVANTAGE 5
The AMD Spartan UltraScale+ FPGA family is built upon a
ADAPTIVE COMPUTING: proven 16 nm architecture, offering a high I/O count and an
MORE THAN advanced feature set:
PROGRAMMABLE LOGIC 6
• LPDDR4x/5 interface for high-throughput, low latency
THE AMD COST-OPTIMIZED memory access
PORTFOLIO OF FPGAS 8
• MIPI D-PHY to connect to the latest cameras and high-
resolution displays
SPARTAN™ ULTRASCALE+
FAMILY 11 • Compliant PCIe® Gen4 for standardized connectivity to
The latest addition to the AMD FPGA portfolio is the external systems
SELECTING THE RIGHT AMD Spartan UltraScale+ FPGA family. The Spartan FPGA
• State-of-the-art security features including NIST approved
PROGRAMMABLE DEVICE 13 families have a long history of providing efficient and
Post Quantum Cryptography (PQC) to protect connected
flexible programmable logic for size, power, and cost-
devices.
SELECTING THE RIGHT constrained applications. The first Spartan devices were
PARTNER 14 developed in 1998, shipped in 2000, and have played an
important role in many groundbreaking applications over
Will update next rev
AMD – THE FPGA LEADER 15 the years, including space missions.

FPGAS FOR ARTIFICIAL AMD understands that market and application needs MIPI D-PHY (Soft)
INTELLIGENCE AND change over time. For over 20 years, the Spartan family has HD I/O
MACHINE LEARNING 16 HD I/O XPIO
continued to evolve with new advances and innovations.
The latest iteration, the Spartan UltraScale+ family delivers
LPDDR4x/5 Transceivers
COST-OPTIMIZED FPGA even more capabilities than ever. Programmable
APPLICATIONS 17 Logic
BRAM PCIe Gen 4
The Spartan UltraScale+ family has been designed and
SUMMARY 18 cost-optimized for a wide range of embedded applications. UltraRAM MicroBlaze™ V (Soft) DSP
It is ideal for secure, lower power applications, including
MORE RESOURCES 19 embedded vision, industrial IoT, industrial networking, Security Clock Management
robotics, smart city, healthcare, AI at the edge, secure
communications, video, broadcast, and more.
 UNLOCKING INNOVATION WITH COST-OPTIMIZED FPGAS | 12

OVERVIEW 2 KEY BENEFITS many board-level components using a diverse set of reduce cost for I/O heavy, low-logic applications3. These
protocols/standards. For this reason, all nine AMD Spartan™ comprehensive I/O capabilities supporting 1.2V to 3.3V
The AMD Spartan™ UltraScale+™ FPGA family delivers many
CURRENT TRENDS AND UltraScale+™ FPGAs offer a high number of I/Os relative to enable the Spartan UltraScale+ family to seamlessly
CHALLENGES IN benefits to developers, including:
the amount of programmable logic. This enables developers integrate custom logic to interface with multiple sensors,
ELECTRONICS DESIGN 3
High I/O to Logic Ratio: An important factor in many to design systems that can aggregate a great deal of I/O devices, and external systems.
embedded applications is the ability to interface with at the edge within a small physical footprint, and helps to
THE PROGRAMMABLE LOGIC State-of-the-Art Security: Integrated capabilities offer
ADVANTAGE 5 protections against security threats so developers can have
confidence in the security capabilities and reliability of their
ADAPTIVE COMPUTING: designs. Multiple levels of security are available, including
MORE THAN
PROGRAMMABLE LOGIC 6 NIST-approved PQC, secure boot, encryption, and key
management.
THE AMD COST-OPTIMIZED Low Power: Spartan UltraScale+ devices are designed to
PORTFOLIO OF FPGAS 8
optimize system power, I/O performance and protection.

SPARTAN™ ULTRASCALE+ Mainstream Interface Support: The AMD Spartan™

FAMILY 11
UltraScale+™ FPGA family supports key standard interfaces,
including LPDDR4x/5, MIPI D-PHY, and PCIe® Gen4 to
SELECTING THE RIGHT streamline integration with existing systems. In addition,
PROGRAMMABLE DEVICE 13 INDUSTRIAL AND EDGE HEALTHCARE AND SCIENCES
these interfaces are hardened, helping to maximize their
• Factory Automation and Robotics • Medical Equipment
performance and efficiency at low power while conserving
SELECTING THE RIGHT
• IIoT Gateways and Edge Appliances • Imaging (Ultrasound, CT/MRI, Endoscopy) programmable logic resources.
PARTNER 14
• Smart City and Smart Grid
Quality Development Platform: The AMD Spartan™
AMD – THE FPGA LEADER 15 UltraScale+™ family is supported by the robust and easy-
to-use AMD Vivado™ development tools. Because many
FPGAS FOR ARTIFICIAL designers are already familiar with Vivado, developers can
INTELLIGENCE AND
MACHINE LEARNING 16 leverage the productivity benefits of the platform and its
vast portfolio of IP to accelerate design and bring their
COST-OPTIMIZED FPGA products to market quickly.
APPLICATIONS 17

SUMMARY 18

WIRED AND WIRELESS DATA CENTER AND CLOUD

MORE RESOURCES 19
• Wireless Infrastructure • Storage Acceleration
• Access Network and Connectivity • Data Center Interconnect
 UNLOCKING INNOVATION WITH COST-OPTIMIZED FPGAS | 13

OVERVIEW 2
Selecting the Right Programmable Device
CURRENT TRENDS AND
CHALLENGES IN
ELECTRONICS DESIGN 3 With such an extensive range of devices to choose from in Finally, one of the key advantages of the breadth of the cost- An often-overlooked consideration when estimating
the cost-optimized portfolio, it can seem daunting to figure optimized portfolio is that there is often a variety of similar resources requirement is the internal fabric or interconnect.
THE PROGRAMMABLE LOGIC out how to select an FPGA or adaptive SoC. A good starting devices with close variations in capabilities and capacity. The AMD uses a hardened interconnect for internal routing
ADVANTAGE 5 place is to determine whether an embedded processor last step, then, will be to right-size your selection to match within the FPGA. This results in outstanding programmable
is needed. A soft processor (IP-based) gives flexibility your final application requirements. Having ample choices logic resource utilization compared to devices that depend
ADAPTIVE COMPUTING: of choice and implementation. FPGAs with a hardened means you can select the optimal device that allows you to upon a soft interconnect. With a soft interconnect,
MORE THAN embedded processor (i.e., adaptive SoCs) are also available pay only for exactly what you need. resources that could be used as data resources must be
PROGRAMMABLE LOGIC 6
for high performance and power efficiency. used for the fabric.
OPTIMAL USE OF PROGRAMMABLE LOGIC
THE AMD COST-OPTIMIZED The next consideration is whether high-speed transceivers Thus, when comparing different architectures, it’s critical to
PORTFOLIO OF FPGAS 8 RESOURCES
are needed. For example, the AMD Artix UltraScale+ take the interconnect fabric into account. Developers that
FPGA offers high number of transceivers at lower device A key part of selecting the right FPGA is understanding focus solely on logic requirements will discover they need
SPARTAN™ ULTRASCALE+ densities. and accurately estimating how many programmable many more resources to interconnect the logic.
FAMILY 11
logic resources will be needed to implement the required
Next, estimate the number of logic resources required. functionality. However, there are important factors to The table below highlights key features and functionality
SELECTING THE RIGHT There is a resource estimator in the AMD Vivado™ Design consider when estimating resource allocation. of some of the many products in the AMD cost-optimized
PROGRAMMABLE DEVICE 13
Suite during the design implementation phase, where portfolio.
users can get an estimation of the utilization of various For example, devices with a good selection of hardened
SELECTING THE RIGHT FPGA resources, including logic cells, flip-flops, block RAMs, functions will not need to implement these functions
PARTNER 14
DSP slices, and I/O pins. The number of look-up tables using a device’s limited programmable logic resources. This
(LUTs) needed will help identity the best family and device enables developers to use smaller FPGAs, helping reduce
AMD – THE FPGA LEADER 15 overall power and size.
within that family. When sizing logic resources throughout
a project life cycle, it’s important to take into account
FPGAS FOR ARTIFICIAL
INTELLIGENCE AND scope and requirement changes that can increase the logic AMD Spartan™ 7 AMD Artix™ 7 AMD Artix™ AMD Spartan™ AMD Zynq™ 7000 SoC Zynq UltraScale+ MPSoC
resources that will be needed. FPGA FPGA UltraScale+™ FPGA UltraScale+™ FPGA Z-7007S, Z-7010, Z-7012S, ZU1, ZU2, ZU3, ZU3T
MACHINE LEARNING 16 Z-7014S, Z-7015, Z-70202

Logic Cells / System 102 215 308 218 85 157

At this point, requirements such as size, weight, and Logic Cells (K)
COST-OPTIMIZED FPGA
APPLICATIONS 17 power consumption will help finalize the decision-making Total RAM (Mb)* 5.4 16.0 15.2 26.79 5.9 21.2
process. Numerous technologies and options are available DSP Slices 160 740 1200 384 220 576

SUMMARY 18 to optimize the FPGA for key requirements. For example, Transceiver Count @ - 16 @ 6.6 12 @ 16.375 8 @ 16.375 4 @ 6.25 4 @ 6.0 and 8 @ 12.5
Speed (Gb/s)
AMD provides many devices in Integrated FanOut (InFO)
DDR Interface @ DDR3 @ 800 DDR3 @ 1,066 DDR4 @ 2,400 LPDDR4x/5 @ 4,266 DDR3 @ 1,066 DDR4 @ 2,666
or Chip-Scale Package (CSP) packaging, which reduces Speed (Mb/s) (Soft MC) (Soft MC) (Soft MC) (Hard MC) and (Hard MC) (Hard MC)
MORE RESOURCES 19 DDR4 @ 2,400 (Soft MC)
component board area and height when compared to flip-
PCI Express® Interface - Gen2x4 Gen4x4 Gen4x8 Gen3x8 Gen 3x8
chip packaging.
I/O Pins 400 500 304 572 252 466
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OVERVIEW 2
Selecting the Right Partner
CURRENT TRENDS AND
CHALLENGES IN
ELECTRONICS DESIGN 3 It's important to remember that there’s more to provide sample chips doesn’t necessarily mean they can
selecting an FPGA than just the chip. You are developing deliver production volumes in the time frame you require.
THE PROGRAMMABLE LOGIC a partnership with your supplier, and your success in the And if your supplier cannot gain sufficient traction quickly
ADVANTAGE 5 market depends upon whether your supplier can provide enough, their FPGA product line or even entire company
the devices you need, when you need them. may fail, putting your product line or even your company at
ADAPTIVE COMPUTING: risk.
MORE THAN Here are some key questions to ask when selecting your
PROGRAMMABLE LOGIC 6 FPGA partner: How long will AMD produce and support these components?

How complex are the development tools? A large number of new chips are introduced every year.
THE AMD COST-OPTIMIZED
PORTFOLIO OF FPGAS 8 Many of these chips are offered by startups or companies
An important part of choosing the right programmable new to a particular industry. However, new offerings that
logic device is the tool chain that enables you to exploit the
SPARTAN™ ULTRASCALE+ don’t achieve sufficient market penetration can disappear
FAMILY 11 capabilities of the silicon. Newcomers to the market offer as quickly as they appeared. Without a promise of product
FPGAs with tools that often haven’t been proven yet. These longevity, an OEM might find that a critical chip is no longer
tools can be frustrating to learn and use as there hasn’t
SELECTING THE RIGHT available just as their product begins to succeed in the
PROGRAMMABLE DEVICE 13 been time to refine them. market.
How scalable is the AMD FPGA family?
SELECTING THE RIGHT
PARTNER 14 FPGAs designed for highly specific applications can be too
narrow in scope and performance, and there are inherent
AMD – THE FPGA LEADER 15 risks in working within a limited portfolio of devices. For
example, if your application needs more or fewer I/O than
FPGAS FOR ARTIFICIAL the options available, you’ll either be forced to scale back
INTELLIGENCE AND performance or increase cost to find a device that fits your
MACHINE LEARNING 16
application. Without a broad availability of options, not
being able to right-size an FPGA for your application can
COST-OPTIMIZED FPGA
APPLICATIONS 17 cost in terms of longer development time, higher device
cost—or both.
SUMMARY 18
Can you keep up with my demand?

MORE RESOURCES 19 Supply chain reliability is crucial to market success. To

succeed, developers need partners they can trust, who can
keep up with market demand. Just because a supplier can
 UNLOCKING INNOVATION WITH COST-OPTIMIZED FPGAS | 15

OVERVIEW 2
AMD – The FPGA Leader
CURRENT TRENDS AND
CHALLENGES IN
ELECTRONICS DESIGN 3 For nearly 40 years, AMD has been a leader in FPGA COMPONENTS FOR THE LIFETIME OF YOUR AMD supports a 15+ year product life cycle, giving
technology (Xilinx, before the acquisition). From the PRODUCTS developers confidence in the availability of components
THE PROGRAMMABLE LOGIC cost-optimized portfolio to leading-edge adaptive SoCs, that are essential for the success of their long-life products.
When choosing a technology partner, it is important for
ADVANTAGE 5 AMD offers a broad range of FPGA and adaptive SoC When possible, AMD will announce extensions of life
developers to select a supplier who understands how
products. Our extensive portfolio of FPGAs brings the cycles years in advance, such as it has by extending the
important component availability is to their success.
ADAPTIVE COMPUTING: benefits of programmable logic to nearly every industry and product life cycle of all its AMD Zynq™ 7 Series FPGA devices
MORE THAN Automotive, industrial, medical, and other embedded
application. through at least 2035.
PROGRAMMABLE LOGIC 6 applications typically have a much longer product life cycle
As one of the world’s leading silicon manufacturers, AMD than consumer products. To give developers confidence
THE AMD COST-OPTIMIZED can provide the volume production and support developers that the components they rely upon will be available for
PORTFOLIO OF FPGAS 8 the life of their product, AMD is committed to product
need to achieve their success. AMD has a stable supply
chain designed to support mass production across a wide longevity.
SPARTAN™ ULTRASCALE+ range of applications. AMD also has corporate stability with
FAMILY 11
a proven track record. In other words, AMD has the stability
to back up its promises of product availability in volume
SELECTING THE RIGHT
PROGRAMMABLE DEVICE 13 quantities across a product’s life cycle.

These factors enable AMD to deliver superior product

SELECTING THE RIGHT quality backed by an excellent, responsive support team
PARTNER 14
and provide a reliable supply chain you can depend upon.

AMD – THE FPGA LEADER 15 By choosing to collaborate with AMD, customers are
choosing to work with the market leader4 and inventor of
FPGAS FOR ARTIFICIAL FPGA technology. They also gain a trusted partner that is
INTELLIGENCE AND committed to driving FPGA technology forward. With the
MACHINE LEARNING 16
launch of the AMD Spartan™ UltraScale+™ family, AMD
demonstrates its continued investment and commitment
COST-OPTIMIZED FPGA
APPLICATIONS 17 to the low-cost FPGA market.

SUMMARY 18

MORE RESOURCES 19

SOURCE: https://community.amd.com/t5/adaptive-computing/amd-extends-product-lifecycle-for-all-xilinx-7-series-devices/ba-p/563507. Roadmap subject to

change.
 UNLOCKING INNOVATION WITH COST-OPTIMIZED FPGAS | 16

OVERVIEW 2
FPGAs for Artificial Intelligence and
CURRENT TRENDS AND
CHALLENGES IN Machine Learning
ELECTRONICS DESIGN 3

THE PROGRAMMABLE LOGIC Artificial Intelligence (AI) and Machine Learning (ML) are eliminating unnecessary operations for enhanced efficiency.
ADVANTAGE 5 quickly becoming one of the most important trends in the When an AI algorithm is implemented in an FPGA, nodes
electronics industry. For embedded design, AI at the edge that “zero out” can be eliminated. This compresses or
ADAPTIVE COMPUTING: enables systems to use sensor data in innovative ways to collapses the algorithm in size without compromising
MORE THAN improve performance, productivity, safety, and reliability. As accuracy.
PROGRAMMABLE LOGIC 6
AI technology continues to evolve, it is likely that AI will be
Density: The combination of flexible data types and
integrated into many embedded devices.
THE AMD COST-OPTIMIZED compressed algorithms allows developers to implement
PORTFOLIO OF FPGAS 8 FPGAs are emerging as a cost-effective solution for AI in certain AI algorithms extremely efficiently.
embedded applications and at the edge. FPGAs offer the
SPARTAN™ ULTRASCALE+ Custom Implementation: Developers can tailor an FPGA
flexibility to support a wide range of data types, enhancing
FAMILY 11 to the AI network and data types an application requires.
adaptability for various applications. In addition, for edge
There are no wasted resources, thus minimizing silicon
applications requiring custom processing, programmable
SELECTING THE RIGHT cost, system footprint, and energy consumption.
PROGRAMMABLE DEVICE 13 logic enhances power efficiency through application-specific
control dataflow and memory hierarchy. Developers need Higher Efficiency: All these factors mean that many
access to a flexible set of resources that can be customized embedded AI algorithms can be implemented with much
SELECTING THE RIGHT
PARTNER 14 for the specific AI implementation their application fewer FPGA resources than would be required with a
requires. processor-based approach. Implementing systems with
AMD – THE FPGA LEADER 15 a few thousand LUTs on FPGAs can significantly reduce
To meet the size, cost, and power constraints of many
power consumption, providing an efficient alternative for
embedded and edge applications, the AMD cost-optimized
FPGAS FOR ARTIFICIAL specific use cases.
portfolio of FPGAs offers many benefits, including:
INTELLIGENCE AND
MACHINE LEARNING 16 With the efficiency of the AMD Spartan™ UltraScale+™
Flexible Data Types: There’s a great deal of innovation
FPGA architecture, it is possible to implement some AI
around data types used for AI. With an FPGA, there are no
COST-OPTIMIZED FPGA networks on a single chip.
APPLICATIONS 17 limitations on data type. Developers can create any data
type optimized for their applications, even data types that
are only one or two bits in size. The ability to choose the
SUMMARY 18
best data type for an application is a capability unique to
FPGAs.
MORE RESOURCES 19

Compressed Algorithms: FPGAs allow for streamlined

processing by optimizing the computation of AI algorithms,
 UNLOCKING INNOVATION WITH COST-OPTIMIZED FPGAS | 17

OVERVIEW 2
Cost-Optimized FPGA Applications
CURRENT TRENDS AND
CHALLENGES IN
ELECTRONICS DESIGN 3 AMD cost-optimized FPGAs are useful in a variety of applications, including machine vision, factory automation, and medical equipment.

THE PROGRAMMABLE LOGIC MACHINE VISION FACTORY AUTOMATION MEDICAL EQUIPMENT

ADVANTAGE 5

ADAPTIVE COMPUTING:
MORE THAN
PROGRAMMABLE LOGIC 6

THE AMD COST-OPTIMIZED

PORTFOLIO OF FPGAS 8

SPARTAN™ ULTRASCALE+
FAMILY 11

SELECTING THE RIGHT Machine vision technology is used in a variety of Factory automation is about automating manufacturing Portable medical equipment, like automated external
PROGRAMMABLE DEVICE 13 applications, including object detection and counting, processes to reduce costs and achieve greater efficiencies. defibrillators (AEDs), can help save lives in an emergency.
defect identification, character recognition, and robot Industry 4.0 makes these systems "intelligent" using The reliable operation of such equipment requires secure
SELECTING THE RIGHT guidance. industrial networking, AI, and robotics. wireless connectivity and access control, flexible I/O to
PARTNER 14 support a broad range of sensor types, and long-lasting
Machine vision using USB camera modules or frame Factory automation applications require connectivity over durability, given the long approval cycles required by the
AMD – THE FPGA LEADER 15 grabbers require high-performance I/O for high-resolution diverse communication and industrial Ethernet standards. FDA.
image sensing, and high-performance connectivity to They also require system-level adherence to safety
FPGAS FOR ARTIFICIAL devices that can efficiently operate in often space- standards, and must be effective at buffering and storing The cost-optimized AMD Spartan™ UltraScale+™ FPGA is
INTELLIGENCE AND constrained and battery-powered environments. data. an ideal choice for portable medical equipment, providing
MACHINE LEARNING 16 authenticated and encrypted firmware to help protect
The 16 nm-based, cost-optimized AMD Spartan™ The cost-optimized AMD Spartan™ UltraScale+™ FPGA from information and prevent tampering. It also supports a wide
COST-OPTIMIZED FPGA UltraScale+™ FPGA family is ideal for machine vision. It AMD is an ideal choice for factory automation applications. range of sensor types, thanks to its customizable I/O, which
APPLICATIONS 17 operates at a mere 3.3V and delivers high-speed sensor It delivers multiple IP options from AMD and its partners: helps to enhance the versatility of the AED devices. The
support, and a flexible camera interface to x86 processors-- EtherCAT, ProfNET/ProfiBUS, TSN and/or CAN. It also product also offers a 15-year life cycle, suitable for FDA-
SUMMARY 18 all in a small form-factor package. offers complex safety features, like Safe Torque Off (STO), regulated medical devices.
Safe Stop (SS1/SS2), and Safe Direction (SDI). It also uses
MORE RESOURCES 19 LPDDR4x/5 for external memory buffering.
 UNLOCKING INNOVATION WITH COST-OPTIMIZED FPGAS | 18

OVERVIEW 2
Summary
CURRENT TRENDS AND
CHALLENGES IN
ELECTRONICS DESIGN 3 With the launch of the new AMD Spartan™ UltraScale+™
FPGA family, AMD further expands the low-power offering of
THE PROGRAMMABLE LOGIC the cost-optimized portfolio of low-end to mid-range FPGAs.
ADVANTAGE 5 This new family, as well as the entire FPGA portfolio, enables
developers to address the many challenges that arise with
ADAPTIVE COMPUTING: new innovations, applications, and technologies.
MORE THAN
PROGRAMMABLE LOGIC 6 Programmable logic offers a powerful architecture that
brings the flexibility of software programmability to
THE AMD COST-OPTIMIZED hardware design without compromising performance or
PORTFOLIO OF FPGAS 8 efficiency. Rather than being locked in their capabilities
like fixed-function devices, FPGAs can adapt to the ever-
SPARTAN™ ULTRASCALE+ changing needs of the marketplace. The most flexible
FAMILY 11
devices are adaptive SoCs, highly integrated FPGAs that
provide a single-chip solution.
SELECTING THE RIGHT
PROGRAMMABLE DEVICE 13
AMD, through its acquisition of Xilinx, has been the leader in
FPGA technology for decades. With proven silicon, one of the
SELECTING THE RIGHT industry’s most streamlined development platforms, and
PARTNER 14
unmatched scalability, AMD FPGAs can give developers the
competitive edge they need to outperform their competition.
AMD – THE FPGA LEADER 15
AMD is committed to leading the FPGA industry. With
FPGAS FOR ARTIFICIAL continuing investment in new product families, AMD has an
INTELLIGENCE AND unmatched portfolio of programmable logic devices. As a
MACHINE LEARNING 16
trusted partner, AMD is able to deliver superb components,
backed by extended product availability.
COST-OPTIMIZED FPGA
APPLICATIONS 17
To learn more about AMDs cost-optimized portfolio of
FPGAs, please visit: www.amd.com/cost-optimized.
SUMMARY 18
To learn more about AMD Spartan™ UltraScale+™ FPGAs,
MORE RESOURCES 19 please visit: https://www.amd.com/spartan-ultrascale-
plus.
 UNLOCKING INNOVATION WITH COST-OPTIMIZED FPGAS | 19

OVERVIEW 2
MORE RESOURCES
CURRENT TRENDS AND
CHALLENGES IN • Cost-Optimized Portfolio (xilinx.com)
ELECTRONICS DESIGN 3
• AMD Spartan™ 7 FPGA Family (xilinx.com)
THE PROGRAMMABLE LOGIC
ADVANTAGE 5 • AMD Artix™ 7 FPGA Family

• AMD Artix™ UltraScale+™ FPGA Family

ADAPTIVE COMPUTING:
MORE THAN
PROGRAMMABLE LOGIC 6 • AMD Zynq™-7000 SoC Family

• AMD Zynq™ UltraScale+™ MPSoC Family

THE AMD COST-OPTIMIZED
PORTFOLIO OF FPGAS 8
• Boards & Kits for Cost-Optimized Designs
SPARTAN™ ULTRASCALE+ • AMD Spartan™ UltraScale+ FPGA Family
FAMILY 11

SELECTING THE RIGHT

PROGRAMMABLE DEVICE 13
ENDNOTES
SELECTING THE RIGHT 1. SUS-001. Based on AMD internal analysis December 2023, comparing the total I/O to logic cell ratios in the AMD
PARTNER 14 product datasheets for Spartan™ UltraScale+™ FPGAs to previous generations of AMD cost-optimized FPGAs.
2. SUS-01. Based on AMD internal analysis December 2023, comparing the total IO to logic cell ratio in the AMD prod-
AMD – THE FPGA LEADER 15 uct datasheets for Spartan™ UltraScale+™ FPGAs to previous generations of AMD cost-optimized FPGAs.
3. SUS-09. Based on datasheet comparison of the AMD Spartan UltraScale+ SU10P FPGA to the Spartan 7 7S50 FPGA
FPGAS FOR ARTIFICIAL and calculating cost savings per I/O based on AMD list prices as of February 2024, for user designs requiring at least
INTELLIGENCE AND 200 GPIO. Prices subject to change, results may vary.
MACHINE LEARNING 16
4. SUS-12. Revenue data, Omida Competitive Landscape Tool CTL Quarterly Semiconductor Market Share, November
2023.
COST-OPTIMIZED FPGA
APPLICATIONS 17

SUMMARY 18

MORE RESOURCES 19
© Copyright 2024 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo, AMD
MicroBlaze, Vivado, Zynq, UltraScale+, Spartan, Artix, Virtex, Vivado,, Kintex, and other designated
brands included herein are trademarks of Advanced Micro Devices, . Other product names used in this
publication are for identification purposes only and may be trademarks of their respective companies.
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