PBL3
FPGA DESIGN & VERILOG
Assoc. Prof. Dr.‐Ing Nguyen Van Cuong
Welcome to The PBL3-FPGA DESIGN & VERILOG
Our Team
Instructor: Assoc. Prof. Dr.-Ing Nguyen Van Cuong
Ph. D. and Postdoc. in Munich, Germany;
Visiting Scholar in UW- Seattle, USA
Mobile: 0913488658;
E-mail: ngvancuong2000@gmail.com
TA
Lab Supervisor:
SYLLABUS
The first stop in your journey to learn the art of
electronic design automation (EDA)!
Use Hardware Description Languages (HDLs)
to design, verify, and validate digital logic.
Prototype digital systems using FPGA platform.
The main topics covered in the course:
1. Introduction: Digital Logic design with Verilog, FPGA and
EDA software
2. Fundamentals of Sequential Logic Design
3. Logic Design with Behavioral Models of Combinational and
Sequential Logic
4. Design and Synthesis of Datapath Controllers
5. Algorithms and Architectures for Digital Processors
6. Architectures for Arithmetic Processors
7. Final Project: Embedded System Design using FPGA
+ Altera: Quartus II
+ Xilinx: ISE webpack 14.7, Vivado
+ Mentor graphics: ModelSim PE Student Edition
By the end of this quarter you will be able to:
1. Use Hardware Description Languages (HDLs) to
design, verify, and validate digital logic
2. Synthesize HDLs into hardware using the same tools
used in industry.
3. Analyze design tradeoffs and use design tools
commonly used in industry
4. Participate in process of working to design a digital
system in a team environment.
General Information
•Allow at least 48 hours for a response to your email
•Required textbook:
1. Samir Palnitkar, Verilog HDL A guide to Digital Design
and Synthesis,
2. Ciletti, Michael D., 2011, Advanced Digital Design
with the Verilog HDL, Prentice Hall, 2nd ed
Exams:
There will be one in-class midterm and a final
project in teamwork.
No make-up exam will be given
The exams are normally closed-book, closed-note,
and closed homework.
A two-pages write-up sheet will be allowed.
Evaluation and Grading
The final grade consists of:
On-going assessment (Class participation,
HW): 20% (10% + 10%)
Lab: 20%.
Midterm: 20%.
Final Project 40%
ECE 351
Verilog HDL
Week 01
Introduction to Verilog
Chapter 1: Introduction, Hierarchy, and
Modelling Structures
OBJECTIVES
Identify the components of Verilog models,
including modules, instances, and ports
Correct the syntax for each of the components of
Verilog models
Statethe relationships among the different
components of Verilog models
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Overview
Evolution of Computer-Aided Digital Design
Emergence of HDLs
Typical Design Flow
Importance of HDLs
Popularity of Verilog HDL
Trends in HDLs
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Hardware Description Languages
Hardware Description Languages, or HDLs, are languages
used to design hardware.
Similar to procedural programming languages (e.g., C)
Digital hardware only
An HDL can also be used to describe the functionality of
hardware as well as its implementation.
Leads to simulation
Allows functional verification
Hardware Description Languages (cont.)
Describe hardware modules at varying levels
of abstraction (more later …)
Structural description
Textual replacement for schematic
Hierarchical composition of modules from primitives
Behavioral/functional description
Describe what module does, not how
Synthesis step generates circuit for module
Simulation semantics are included
Levels of Design Abstraction
Levels of abstraction for VLSI circuit design:
Levels of Design Abstraction
Levels of abstraction for VLSI circuit design:
Levels of Design Abstraction
Levels of abstraction for VLSI circuit design:
Levels of Design Abstraction
Levels of abstraction for VLSI circuit design:
Levels of Design Abstraction
Levels of abstraction for VLSI circuit design:
HDLs
Why HDLs ?
The complexity of logic circuits has increased
dramatically in the past few decades
Other forms of EDAs are no longer effective
HDLs offer a consistent and efficient method for
both design and synthesis
HDLs are relatively easy to learn
Why HDLs ? (cont.)
M1 M2
M3
X
M4
Why HDLs ? (cont.)
Why HDLs ? (cont.)
History of HDLs
The first HDL was ISP*,
invented by C. Gordon
Bell and Alan Newell at
Carnegie Mellon
University (CMU) and
described in their book
Computer Structures
published in 1972.
Gordon Bell
* Instruction-set Processor language
Alan Newell
History of HDLs (cont.)
ISP was the first HDL to
use the term register-
transfer level (RTL).
This term came from the
use of ISP in describing
the behavior of the PDP-8
computer as a set of DEC PDP-8
registers and logical
functions describing the
transfer of data from
source register to
destination register.
HDLs
ISP (circa 1971) - Simulation, but no synthesis
ABEL (circa 1983) - developed by Data-I/O
Targeted to programmable logic devices
Not good for much more than state machines
HDLs
Verilog (circa 1985) - developed by Gateway (absorbed
by Cadence)
Similar to Pascal and C
Delays is only interaction with simulator
Fairly efficient and easy to write
IEEE standard
HDLs (cont.)
VHDL (circa 1987) - DoD sponsored standard
emphasis on re-use and maintainability
Simulation semantics visible
Very general but can get verbose
IEEE standard
Updated in 1993
The current trend is to move towards the two leading standards,
VHDL and Verilog HDL.
Other options available: BlueSpec, SystemC
HDL Overview
Hardware description languages (HDLs)
Textual descriptions of digital logic
Description languages, not Programming
languages!
Allow modeling and simulating the functional
behavior and timing of digital hardware
Synthesis tools take an HDL description and
generate a technology-specific netlist (real
hardware representation)
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thread
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Multi-Threading
#include<stdio.h>
int And(int a, int b);
int Or(int a, int b); int Not(int a);
void main()
{
///where main body of code will go
}
int And(int a, int b)
{
int output; if(a==0 && b==0) output=0; if(a==1 && b==0) output=0; if(a==0 &&
b==1) output=0; if(a==1 && b==1) output=1; return (output);
}
int Or(int a, int b)
{
int output; if(a==0 && b==0) output=0; if(a==1 && b==0) output=1; if(a==0 &&
b==1) output=1; if(a==1 && b==1) output=1; return (output); }
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Overview (cont.)
The great advance: a single language
could be used to describe the function
of the design and also to describe the
implementation.
This allows the entire design process
to take place in a single language, and
thus a single representation of the
design.
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Key features of Verilog
Supports various levels of abstraction
Behavior level
Register transfer level
Gate level
Switch level
Simulate design functions
Different Levels of Abstraction
Systems design is the process of defining the
architecture, components, modules, interfaces, and data
for a system to satisfy specified requirements
Architectural / Algorithmic Level System
Implement a design algorithm in
Algorithm
high-level language constructs.
Architecture
Register Transfer Level
Describes the flow of data Register Transfer
Level
between registers and
how a design process Gate Level
these data.
Transistor Level
Different Levels of Abstraction
Gate Level
Describe the logic gates and the
interconnections between them.
System
Switch (Transistor) Level Algorithm
Describe the transistors and Architecture
the interconnections
between them. Register Transfer
Level
Gate Level
Transistor Level
Simplified Hardware Design Flow
Verilog
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@=at
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module twoinmux(out, in1, in2, sel);
input in1, in2, sel;
output out;
wire selb;
supply1 pwr;
supply0 gnd;
pmos (selb, pwr, sel);
nmos (selb, gnd, sel);
cmos (out, in1, selb, sel);
cmos (out, in2, sel, selb);
endmodule
selb=!sel
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The testbench uses the high-level structure of Verilog to generate test
data, output response observation, and handshaking between signals in
the design.
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Verilog Module Styles
Modules can be specified different ways
Structural – connect primitives and modules
RTL – use continuous assignments to specify combinational
logic
Behavioral – use initial and always blocks to describe the
behavior of the circuit, not its implementation
A single module can (and often does) use more than one
method.
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Structural Example: Majority Detector
Structural models specify interconnections of primitives
and modules.
Synthesis tools may still optimize your design!
module majority (major, V1, V2, V3) ;
output major ;
input V1, V2, V3 ; V1 N1
A0
V2
wire N1, N2, N3;
and A0 (N1, V1, V2), V2 N2 major
A1 Or0
A1 (N2, V2, V3), V3
A2 (N3, V3, V1);
or Or0 (major, N1, N2, N3);
V3 N3
A2
V1
endmodule majority 44
RTL Example: Majority Detector
RTL models use continuous assignment statements to
assign Boolean expressions to signals.
If an input value changes, the value of the assignment is
immediately updated. This is combinational hardware,
not software.
module majority (major, V1, V2, V3) ;
output major ; V1
input V1, V2, V3 ; majority major
V2
assign major = (V1 & V2) V3
| (V2 & V3)
| (V1 & V3);
endmodule
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Behavioral Example: Majority Detector
Behavior models specify what the logic does, not how to
do it (simulation versus hardware)
Tools try to figure out what hardware is implied by the
described behavior – Not all behaviors can synthesize!
module majority (major, V1, V2, V3) ;
output reg major ;
input V1, V2, V3 ;
always @(V1, V2, V3) begin V1
if ((V1 && V2) || (V2 && V3)
|| (V1 && V3)) major = 1; V2 majority major
else major = 0;
end
V3
endmodule
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