ee MIA AL TT ICuInS ate me Me SEQUENTIAL ciRcullS —L SS —____ pe evs S = > —> obtal cireutts ave, those — ocho output | levels at = any Snatant time = ave deperseot act only on the levels present at the fnputs ot tat time, buf also “on the stote of the ctreurt. teed back “The Post history fs provided by bock 48 the Snput from the output Sequential cireutts are thus made of aod menor} elements. combinahonal circufts outputs soputs menor ss elemnek® Bleck diageam of sequential circuit Sequential cfreutts ore + counters, Shift veoisters , Serial adders, Seqpence geraoters , logic fang ton generate.>The efor” Shore Gy Ee” memes ele, at cae’ Given me defines -the. presedt « Ste. oF the sequential ctreut& - ae ‘the present state and the external Toputs determine the autputs and the next atake of the seqweotial — cfreutt- Comporisan between Combfoaional and Sequential CiveuteES Combinational ctreufts combinational output voriables at- any of -time ave dependent only on the Present fopect vaxtables . ‘Io ctreufts, the fostant 2 Memory untt is not fa combfnationo-L requtred ctreutts - 5» Combinational etreutts are faster bemuse the delay ‘lw the fnput and -the cutput is due -to propagation deloy of gates cola sequen tial — ctreuk tS sequential etreufts , the output variables depe- ndent not ooly 09 present Soput uorfables, but also o0 the present state, ie on the past history of the To —] Syst Store the past histosy to of the Yoput uariables TO Sequential ckreutts. |3- Sequential circuits are slower than combinational circuits. 7.Yes combinational dreutks axe L casy to design 4. sequential civeutts @ axe Compara tively harder tp design Claset-tications of ie Dequential ctreusts ee Synchronous —> depend'4 09 clock “The = maximum operating stgrols elements Upon actuation of clock Sigal. a- Agyne brooous — > doesn't depends on clock. Synchronous A synchronous i Prout ol circuits Sequential circu s Sequentio} frou | + Io Synchronous ctreuttS , ||. In ronoS — Rreults, snerrory elements are ee elements are either Gnitehed FFS (time delay clocked FE fe- elements: = eveusts , hn synehncneus ctreu 2. fo asynchronous cXyveutt ic +the change ‘in Top Chonge $n input signals can atfect memor J con affect —memasy elements ot an fagtant of téne. 3. Because of the absente of the clock , asynchronous eed OF thy Spee. a lock, clepery cfreutts — can operate —aster on tne delays Fnvolved than Syochsonous cfreuttS ae lection Easier an decian fy Mann letrewteve i ' Ee eee coon tee hatch: An unclecked flep-Hop ts called @ lateh , fs mame %s because the cukpuly of the unclecked flip. top lakehes on to a | or 2° : Immediately after the fnputs 15 applied SHR Lateh : (WoR- gate SR Lotch (acktve-hiqn) ] fs called > “the Simplest type of {lip-tlop an S-R Latch. re SR Latch has two joputs Sand R end — 00 outputs Q@ and @B. => ft con be constructed using either soo cross~ coupled — NAND gates or == two cross coupled NoR. gptes- > vsing +wo NOR getes , eo acttve — Wian sR latch Com be constructed and using +0 NAaND gates an active —Low s-R latch can be constructed » > The came of the latch S-R (6©) SET-RESET) 85 dexived -From the ames of Its Topubs.: aa ant @ a | ee gs 26 ope 7 alos - Logic symbol c Qs Ss a State Lape diagraro iS O ue == o/o ' 1 of) ° oO Reset ol1 1 oO ,]o oO 1 set 1 {0 ' 1 1 1,0 Je nualid ! TONG 10 4 | x Truth table ¢ SET=.0, RESET=0 2 “This is “the normal ell state of the NOR latch and ‘it hos no cHfeck on the output state. Qand | wit wemoiN {in whatever State they were prior to the occurence of this Goput: conditton . SET=0, RESETSI 2 This will alwayg¥eet Q= 0 SET=1, RESET=0: “this wll alway ~wset G=e) SeT=!., RESET=) 4 Q= g=0 so the ~esulting — oubput State fs Unpredictable.1 Pe NAND qete SR. lolch Cactive-low SR latch) « Ss a feT=LS [ee state] ofo ' J} oa a o]) ° ! gek Q of) ) 1 | - 2, t /o ° iB Reset fo I oO hes diagraso uly 0 0 a 1 1 } i -truth table > “the operation of this latch %s -the reverse operation of the Nor gate latch of ‘the discussed conifer. “that fs hy ft ts called an octive -loo «= S-R_ latch > the SET orl RESET fnputs are Sorerally fn the HIG state ond one of them xesgting J went to ortl be pulsed low , whenever we change the lotch outputs .‘Gated Sr PRE f *Goted Latches C clocked Fp ~ Flep) : : 7 TUtp. Flop ~— > A tip flop fs the basic memosy element used to Store one bit of foformations Tt con Store a 0°er al. “the mame flip-flop fs because this circuit —shtfts back = and fort, bekseen Fs too stable states upon application of propey Foputs» or we can soy -Hlip- flop is a Simp logte cfreure + > Flip-flops ore beste butldtog blocks for | sequential ctrcutkes as a > A lp-tlop , hnoon more formally bistable multtvibrator, has tenn Stable stotes - Tt's skates can be changed by applying the proper trig qe "4 signal . > Applications 2 Data Storage ° counting i © Troster of data data cooversion: etc, ® frequency diviston « posallel-to-sertat ¢ Serial — to — poxalled<<< Goted S-R late desextbed earlier, > In -the — latches the dubpute Lime “the Topit condition, can change state are changed. go, “thay ore called asyochnopous tatches. ant >A gated Foput- -the SR etch requires an EWABLE (EN) its S and R_ frputs — will control of the only when the is HIQH- —+ wheo the State Flep--Hop ENABLE ENABLE Ys low , othe foputs become fnettective and 0 change of stote con tabe Place. “The . ENABLE foput way be a clekh. so, a gated S-R latch {fs also called a elecked e-R latch or eee eae synchronous 'g-R Lotchy Stoce this type of tlip-Hop responds to the Changes fo fnputs only as long ag the clock fs Hiatt, “these types of Flip-flops one called leve| triggered tlpdlops.Seo : 4 EN =a hee —_len ar R : —._ * Logie dtagra> Logic syrokol. EN |S|R an av] State T éfo | oO [ o r fofo] 4 \ Nc t Ol oO oO 1 foludiu 3 (fReset I tlo oO ¢ i 1 }o 1 | set ' to : ; i elt - Genolid e o | x/x[o 0 ie o_| xix] 4 | : seve forms “Trath ‘oble L A ae a I ] “lo | ae | i ‘ ; Prey aia 7 See eee : ‘0 0 ' : : 7 : rt! © Eg i 5 ° Moa : TmGoted p= lateb = oD EN wane forms ¢ —— ESS eo ee eee _ eN—| Gq : LS a g se Logic diagraro Logie Bee) En | D | 80. [Gori] state t ° oO 0 1 fo fi p_| Rese I 1 ‘fo YT ce { ij | i © |.% 7},O ]? Joe | } elapeee J x i | | a ales of | A 4 Ee fi. + Edge - Tetagered Plip- Flops -_ © —_“C =Sh— = system fs dttficult to > An: asynchronous desigo and trouble shoot - ~~ To Synehrono4ss systems >. the exact Hemes at which ony output can change states ~ are determined by signal commonly colled tte clock. i m be © posrttve sedge a > clocked flép-tlops posttive. “eiggered Or negative edge triggered : edge triggered Http Hop & rane be are those Sy which: State trans%tions ’ take place only at the — posftive— going edge of the check pulse, and negative : edge tigger Slipdtleps are those fn. ‘which \ state transitions! rtatee. place: ool at the negative — going e age of clock signal => Postitve ~ edge tetggerion fs %ndteated by @ triagg) at the clock terminal of he flip-flop . 2 megatteve. — edge triggering 13 fndvcated by a ‘triangle wth bubble at the clock. terminal ofthe PF Ex 3 Sk, Sab ate fas RK gppt tp-tlop Edge — gered Sue fle 5 aoa" uf cls] R]Gn/ S| ste B g BP eyo fefo] pe —-+>c ea n o|o \ \ 8 R A” of1 0 o ew «| ol bf jee n t}o jo ! get a 1 ]0o t t Ml fae fou} x uid soo! * Sefel: |e xX ui ° Oo |0 x 1x Nc o1 y Lit logic diagrar Froth table yoave forms chara cleus. Lqpatto now ao x j fr My FT Ss oO oT ALAA, 5 Haas \ a = 1 ut / - fee tej tia ts sy, ' i Peete x R feel i Ly, Gort = S-& re | | 1 tof Pot S+R4n ! - 1 Oh! we \ y eee 1 ci Gort = St R Oy - > can ieee ! 4 >ti Pdge~ “tg eve D flip—tlo o (Cp means Datel’) 6 ete ek —fog- are tis rm el gle 2| | RRye SPS ee and _ also > The s- -flip-flep fs - very vergattle the most widely used + > The functioning of the sth -flep-flop fs SR $Utp-Flop , except | fdeotical to that of ‘the line thot of | that §t has no ‘ovalid state the SR -fltp—tloP. | OS Aart Codie. Sgrote A & fey d fog rar eT ‘Tut Table ¢ cw | 3_| Gn| Gav Stole chovacteristie, 29° 4 |lolo Tolls oO, ae = Es a}oli |e@]o ° : : c Leg ate [i fo} ee’ | carl et A-| 1 [2 lo ie set a” t_ {0 I! 1 T@pa1 3h + kGq oti ryt o 1] x oaahe A tf{etis}o von x |x o ° 1 2 viw ! 1 NcEde. triggered To liptlep ;- > A T--ANtptlop bas a single control Foputy, labelled T ~for toggle . > phen TT ts HIGH, the Hip-tlop — toggles on every new clock pulse» +> when T fs Low, the Hip-Slop remains in whatever state 7b was.,betore. 31.8 ne rite Cc act = oC a be ih Lexie Sqerbol le T Bq att | state chooacte istic. EgP Q 0 oO o *\o }1 | » \ D 1 % \ \ ° ®|x]° ° Ine Bn = T8ot+T Sy 0 x I l “ruth table,> Asyrelnonous — Yoput’s The s-R,D and J-K inputs ore SY rebronous they edfect on the flip-flop ‘inputs , because ouput fg, sycchoniaed wrth, the Clock Fnput - Most Te -ftip-flops also have one or more aasqnchroneus Fopuks - “These asyoebronous fnputs oftect — the -Llip- flop output Yodependently oF the Synchronous Yoputs ond the — clock input - “These asynchroneus Fnputs can be used na SET the flip-fep te» the! stoke or Reset the sip top e the 0 State at any time svegasdless of the — conditions ‘ok the other = tops» > “the fsypehrrenous ‘inputs oormatly labelled. PRESET @) SET and CLEAR @D) RESET. > gf the asyochronoug Fnputs are active —Low , the game __ 1S indicated ae PRE and ak. PRE Zn.) FF Operation oO Oo NOT cut 7 a i ° = ° ! @=! \ | | decked operatcre Logic dia gro of a baste 3-K -faptlep with achive. low PRESET and ecLEAR PRE i. PRE 0 a] 8 ° —_orc a- V rt — Ore ‘ CLR Truth table logic sqrobol . TE Fhp_ttop with active uray PRESET and CLEAR 31g nalsKace around condition + > Er sh Flip-flop width of pulse fg +o tong » for g=n=1 the state of +tlip-tiop will keep on chong ing arom 0 1 1 to 0, Otol and so on, at the end of the Cock pulse ts state wilt be vncertain, This phenomenon fs called the Yace around comikton - —> the oubpuls Q ond SG will chorge on thely > > > => own tf the deel pulse width tp fe too . e es % 50) ve ¥ tora ompored with the propagation celoy *. of eh AAND qe: To overcome this problem Master-slave Miptlop', ave Jnbrodueced. “The waster —Slave + lip—tHop cetuollay contains eno feep-ftopS — a master -ftpflop and a slave Flip—tlop - Comtrol inputs ove applied +o master ~SUp-tlop. On the Yising edge of the clock pulse, the level © the control Inputs axe used +t°. + deberentae the output of the emater - © > On the falliog edge ot the clock Pulse, the state of the master is transferred to the sbve, whose outputs OC & and @: S- Master— slave 3% flip-flop >wone-forms “— SS = * Far] 7 | i 5 L a wet i ho BOLE gto 2 of i A a i ‘ od BQ) | i —o | ley a + an ry | i. & | = b nd oo? oi ft ieee . o F clyenee ey ar | : 7 | eee- Filip: Flop Esecttatton Tables -- © —> -for. design of _ Sequential elreuk bs _22citakion tobles of __ Sup Hops are required. hate > Bxtitatlen table of a tUp—flop "ean be obtained rom its -trth table. > 3 indicates’ the ‘oputs reputed to be applied to the 4tip-flep jo take tt from “the Presen state -o the neat state» 3-R flip-flop r ‘ , 7 ets] 5 | R | @n'| Soe a” \ oo o | o + ~ |O{o°] 1 1 a | oU oO. o 4 a _|oe}L \ O- vy ft po ° foo epee eee: ay o oid 7 te eeepc) aright ExcPoation table S=0, R= either o oT! SoR=xTHe table oe Flep-ftop lt Eacitahon table . Excitotion toble ._ + Coovession f ltp- Flops *— Soneinen’, of | Pip PkPs > ourfte down treth -toble of oequtred flip-flop excitoabtons OF actuod- aod write down tep-flop -froc ‘oubpuls of peas aunts Block dragramof cooversiod 0f-flip-Hop to Yh fliptlop “- | Nes : : tlip- flop Ont) scpues, S eee) 0 ° x T x 6 0 ° xX © ® \ 1 | Oo ! x LO | \ \ 7 ° } Pe 11 ; 0 \ | rooversian ane) Conversion of S-R D -ftip-Hop ce eo eee = = Bxterned TP's-p 7 @ comvlersion table, an : an o\_o o\_o. eee o] 1] . |e! a© comersion of 0 Hip Tee Bates | Ps | nes] PUpHop Ps] amen 89 Qari D 0 fe e = i o lo ' : t of 2 2 : or : o ® 1 lo ° ; : \ 1 t ie [ 1 ' e. - ida x 7 G Litt S 34 R89 Lo gi ee doagran :@ (3 # f & Ww ih A Externod PS Nes fuptlop ilpls tres dD ao Sn x 5 ° 0 Oo Qe x ) ° cy ( t oO 4 { x ! | \ x [Oo | Logic dagran, !© DP Fep—ftop to THe flip-flop 7_ _ ee eS External PS 1 Nig! -PUp--tlop . TUpls ‘pls , 7. ‘| 2 80 Qn) © To Jo ° 6 ° \ ° I 0 D0 \ | o oO © 5 \ °o ) ' e ° 4 =f © , 4 t o i 1 t ) Lo ci cf dkeagras@: Fw ftlop-Hlop to T_tlp-tlop -_ . = Sa V Bxternol ps Nes f -Flip-flop,]* FUP TS . ipls =e an Snr | > K oO © o i= 2 oO: ‘. i aes ee 1 |x \ | 0 : conversion “table .BDeoovert D--flip- flop +o 7 flip-flop - 7 4 | Gon | © J 0 [e} Oo oO 0 | \ \ ; oO \ 1 A 1 1 o ° conversiontable a 7 &n e Bn Logic a fe : @) comere TF -fip— 1 ftip—Hop bo Qnvi a D 5 -Hup—lop : Komp -\oa Cc - -|ooSHIFT, REGISTERS: s A xegistey fs a set ‘of Flip- Flops used to Store binary data. > “The storage capacity of register is the eae ta number of bits (Sand os) oF digital dot Tt con yetain. Te hesaira of data in registers ¢ rod be sevial or Ppodallet. —> In sexfot leading » data ts +trangfered Tato the ~vegister fo sextal -torm ie, one bft at a beme, > Faq ponallel \eading , the data fg transttered Foto the — yegister fn pasallel for mn wading thot all the FFS ave “triggered fnto -thery new stakes at the Same fre. “> shift registers ore a | type of logte cfreutts closely xelaked to Counters. > they one ose. Lasfcally for the stmage and transfer of — digitcl date.—> “The > A shtft registey fsa “very Senportank digital. burldeng bloc» TE has Sqnumerable applicalon® basie difference bekween shett register and counter 7g thot, a shift seqistey hes 79 Specttied Sequnce of states except fn certain Specialized very applications , whereas a counber has a spectteed sequence of Stakes. Rutter Register -— er es Te > =| => > Some vrepisters do ating more thon storing @ \btoory word - The butler regishes ts “the stmplest of — vegisters. Be Stmply stores the Hnasy word - The buffer mou be a comtolled buffer. Nast of +he butter registers use 0 Ftep—tlop.a. Yo % aude [ a Ds 4, xe D3 G3 Ds | Fr en. | FFs Fry ee Logie diagsaro of a 4-bte bulferseqisters 84934.8, = Ry kz kr, os 7» “Cootrolled Bulter Register so OkD Logie diagram of a 4-bit controlled butler gona —a > when cIR=0 all the PRs ore RESET and the oukpul- becomes @ =0000 : = wheo cR=1 the register is ready for action, > wpAd fs the control input - when — LoAD is HIGH the dota brts xX cas reach the Topuss of EFS. > when LoAD is LOW , -the x-brtsS cant ~ A number of FFs connected ether such that data way be shifted . @ato and shifted cut of them ts called a - shift register... > ‘Thee axe oer basic types of ehitt ~registe (> Seviol-tn, gextol-out shift ~regisber : ® sexiot 1 serfol goo IP : + Pe Re dota olP Sexfal-in, seviat-out , Shift sught, shift aegistey x seria aes ap “Qe 4, 4, bs Sa——os_g/—Jou 8 FF, | PRS Pay L om Be ge 4-bit sexfat-in, sextal-out , shift - ought, gist ore tae oe“© sextot-t ‘ alin, sevfal-out, shifb-left shitk neqistey gecto’ gore poe Sexfot ged t+ oueeee ae Joka TIP -—— | cqvol-ouk, shiftclett shift G-b?t = Sevfat-fo , Zl megister extol —¢ Sevfol in, Ponallelout ¢hift _seqistor: aes of o aK shitt xeqiste L-BE Sevfal-to , pevallel—oubRN ete? | © Panallel-ta , Berialcovk shite nego" eee sb J J gee @_ — Porallelin , Porctletoouk ahift ouegisters Poroblel dete tp © — Retate- ough © Retote- lef — Shift regis kes E Ponallet fo, Panoliesouk shitt segister - shift mr|gister :. Bidirectional shift meqistey —— oo Ee oo THY ouk— eb + re 19 1 A bid trecktonal. in—4 ook} Sp shift nregistey data bits is one fo which the can be shifted from left +o née he or from suighk to left. ~The “follewing Hiqure Shows the logie diagrarn of AE serfat-tn, Seefal-out , bidtveetionall ohitt megister: Right | ete es the ede signal. . 4 sgplee = : { | Gy Gr Kad Gd D 3, eo 38, ie, 83 Dy Sy a FF FPL FFs FR, Ae [| | oo Logie ltagraen of g-bit biditechonal vegisier -> when Right | cert isat, the logic CiveutE* Werks ag a shift register - —s when Right | TIE is ao, ft wos aso shifb- left shift negister- & Unt versal ‘Shite ‘Register L —~ The register has the capability of beth shifts CRieht g left) and — posallel load iS enlled: a5 untversal Shift —megisters. —> “The most general shitt register has “the pole” Copo. bilikies, tA clear central. to clear = -the vegtotex +p 0. ee A clack fnpat toy Synchronige the eperations, 3B. Shif- aught cestrol to enable -the shift - aight operation and sertal ‘iopae and 1 outpub — lines associated with the shift- sug Ge A Shift- left control to enable the shitt—lesk operattoo and the — gertal Topa and oukpu- Itnes assocfated witth the shift —left.S- A parallel — lead control +o enable a fonallel stanley and the n iopuk lines assoctaked wt “the fomallel tranerfer. G- 9 Pesallet output lines. +. A control state thet leaves the Gerfoxmation io the wegister unchanged an the presence oF the clock. > A universal shit negistev mao be oo vtog multiplexers —> The 4b%t universal shift register having four roulkipleyers, have +80 * Comenon Selection {Ip' S, and S&. — > “the selection fnputS control the mode of operatio 9 of function — wheo Fnformnation trane-fhenned Slectioo fnpuks on the Ponatlet ‘opuke the negistes according oe... the entries - SiS0= 11 the binary lines 7S to the regi Stey Simultaneously dusting “the next clock edge.p>. when 33200 , there is no change 19 “the daka. q aN when SiSoz0l, terminat 1 of the coultt plexey of the o inputs have a path 4o the D foputs Fuip—flps- This causes a shtft- ought operaho % wht the Serfal foput trans ferred tote +Uip-flopery, wh s = eX SiS0=10, Qg ghefe- lett operation wesults Tt wrt the otter — sexfal foput 979 foto lip-flop FF, ponallel ops Ay Ao ro cleot FRY q ERs en, | a goed [Lg serel fox Sit ett Ppurollee spl. 4-bit Goiversal Shift owaister -: - “Afunctenal eee ies oO Mode contro! Registev operation No change Shtet aight Shift left S\ Paallel load : shift O “Time delays. servtat | Ponallet dota conuersion Be mo4 counters - a Unfuersal asynchronous ee -transmnitter (UART). Mi cro procerroy device syste :COUNT ERS —> A digital counter is & set of Flip-dlops whose States chonge in -vespoose to pulses to the counter: 2 ale FFs are — fntexconnected such that a - | deme 1s the ok the fetal number of upto that me, oppied at the — foput their combined binary equivalent pulses that hove occured = The counter 75 Used to count pulses. counters oat be (2) Asypersso7e gs cornters pubromUs — CoH ters, @ = Asyochronous couoters algo called as ripple — eer : wotey - (OY) Serves Counters PP pe a = Synchronous awenters a ve clocked a ch that coch FR in “RA Gere fe ‘triggered ak thre Saene time._ Comparigon of Counters Syochrosous Sa A synchyonous counters this connected that the FF dyives the Of the of the | In Counter i> Sach output of tix the clock -for ted Q- All the clocked FFS axe nok Simultaneously c 3: Design ond fmplement- akon is very sieople even for more number of States. Gs Hatin drawback of these counters fg their low speed as the ‘through before cleek is Peopegated Q& number of pes tt yveaches the last Re FFs are & way Second FE, the output] Second the clock ard so on. Synchronous counters In this +yPe of there connection between the outpur of -fersk FF counter fs 90 st and — clock input of next FF and so on. 2. all the clocked FFs are Simultaneously 3. Design and implement— akon becomes tedious as the states and — complew of increases, ounber G. Stoce elects 19 to all the FFs simultenecusl the otal Propogation detoy applied Ts equal to the Propogahion delay oF only ore ER. ipere thea ave -faster,> Design oF mod-6 asypchrencus counter using > > these tree a | A mod-6 counter has six states 000, GOI, O10, ON, 100, and IDI. when the sixth Pulse is applied , the counter tem porori ly qoes to \lo. tote, bub Tenmediotty wesets tO 000 because Of the feedback provided. Zt ts a Sdivide- by-6 counter’ y Jo the sense that Tk divides the foput clock Frequnocey by G- Tt xcequives 3 Fp feps. Possible cut of — which only Six ave ubliaed. tp flop's hove Cteht States , and the Femadoing two States MO and Il ave ‘ovalfd »‘Desige of a mod-10 asynchronous counter Using, T FES? A med-l0 counter 18 @ decade couoter. TE Ss also called a Bcd countey or a divide —by- lo counter: Tt veqplres our PFs - So, these ore 16 possible stated, oub of uhich ten ave valid and -rempining six ave tovolid. > The ceuoter has lo stable states , 0000 throug’ (00h ce Tt couots fee o+09. rn \ aster putse couot— k p fos R \ 84 83%98 eo ooo) iN to q oe ee] GSI oe v 3 = ‘ oo 0} oo > © Oo 10 al o= a! ¢ 3 0} 4 9.4} e 13[——t3] © 1 98 ol xt be PEEL XT S oO 10} & 3] ul 6 o 1 to e oud) 8 1 © 0 © 9 ‘o , oo | R Bu Qa 0 © 0 064 i, =| 3 @s * 4] PRL PEs Fe | ae ee oe | ft Logic eda ” a Asypetwenais shedeo coneter sing Tee Dypebronars | Cousters - | > Synchronous counters axe counters fy which all the FFs are ‘niggexed Simul taneously by the cloch - fnput pulses. > 54 the - synchronous counter 18 a — shortend - medulus countey FE sutfey trom the Problem of leck-owk. “That fy » the counter not = gelf- Start - ~~ > #& set —- Saal counter 15 one that worl eveotually enter ‘Hs Proper Sequence of states vyegacdle ss of Sts initial state.—> The counter can be made setf- Starting by So destaning f+ that it goes to a iculax ' ang 8 panki state wherever %t enters an fnvalid state. > th same Procedne can be used “for counkey S$ ot any number of bits and ony ovbt brary Sequence . The. only vestriction on the sequence is thok-_, Ft cannot contain. the Same stake more than ence within one complete cycle before repeatig Stself. SS Design of Sypchrooeus counters + le Q: a ae) ieee number of flip-flops + Sased on the desesption of the problem , determine the requixed number ot -tlip=Hops state - diagram Drow the stake diagram Showing all the possible States choice of tlip-flops and éxcftation tables . Minimal Eupressions for excitations. Logic diagram.pa , DESaN of @ Synchronous Mad-6 Counter “using Ie FFs z SEPIL The number of flip-flops +3 for med-6 counter the Sequence Ts 000, 001, O10, ott, 100, lol, O00---- Stepa ° Stete diagraes (oo oe (08) CD) (Om 19) SEP 3s Type of Flep—flop ‘nd the gxeftation stable: } aA ae Required excttation ") Bs 6, Sil 85 GS hha Bk sy [ Oo. 0 0 Oo oO ! ox ox \x oo 1 oto ox 1x KI ot 0 o1 | ox xO VX ou} en \x xl x) 109 ,o!l \xo ox 1x ro t foood |X¥t = ox xl Cucttotion “able.Step 4s mfinienal Exe pressions K-mnaps -for exci babory Tg, Ks ) Ty ke, Tam hy = 6" @9 | op or iN lo Qs \_00, 01 1 ar Oo] ot laa) 1 } o}| x{[x[x)L* t Seppe] = LEG!: Sees: ae diagraco 38 > Desfan of a Synchronous a-bit up-down counter gsing Ts FPS | StEPLD = Number of Flip-Flops vequired a . 10, 1) aad % states (000,001,010, O11, 100,101, alt the states ore ualid. and down oY mode signal M fs vequtved - when Mz=i Fb counts Up. when M=0 if counts down. medes , a control > Foy Selecking up SEP 27 State diagram.@ Ole ie x -- kw yp Hom eK MAK Slaton. x ot ex 2 -¥ ¥-- x, 5 a thes ex = og — Mm RT RO- Ol] pl-o On MX Ke KH OO KKM KE | el os - aS Xe KR KK RK KX -— GD ODDAP wl 9 SP 999 KX KR KEK? Sy 7887-8 o--00--o¢ S| #f*o°0-9- -0 -o0-0--¢ wee OLChlUlLDeLLhlC LF uy ee el x —~9-0- 5-9- " L* 1 aul a -7-9007° gloo- - © 2° d eo e777 9908 ATT gle ° [=] HW O10 a gjeo2°0o © -+—!at Be -ol__tt 1a, att Tt aS yoo},or to = 3 1 3 2 al sla é oof {It x my ol t alee : =] 1% CU Ee Dae Pas px [Kk % 2] F3aff 13]P vy] 8 q 1 2 : 10 x Kw Kw & q 7 10 T= 9, t 29M hg = Q,6,M + @,9.N K-Map fos Ta g- feMop fol ae 1 2 xK-map for T, QS "0 ot ogy at z off [1 Te : q s "I oT) oft ay t RPK* Design of a synchronous BCD Countey a “Toh_PFs 3-6 PF Steptz “The number of flip-flops 4: BeD counter fs cothi bul a ned op counter. TE is a decade counter. Tt has to stake& (e000 trough toot). stepay state dia.gran : - ou: The tyre of Hip-Hop | and excttatioo fable: PS N.S Required excitations ] Bu 83 O29, 84939281 | 7 Ky Sky ke SH omotodo o-oo] os ox OX aX coe! oc ue oY OX 1k XI eo e oo | ox ox xO {Lyx oO 1! © to od oO x 1X xl ef ie Ge Gy re Gio | Ol | oO ox 0 i. ST G61 | oO oO | Va 0.x XO “oO ty ee Ce et Xl XT \ Deo 0 lik 0 Oy Oy Ix ro ! O00 0 0 x | OX Ox x|k-maps ter Sine a Mintmal xpressions : ae @ Qo?! er OA\ oo Ol tt _ tp Sy to OO eal ae eg te] Tall *) a ‘ai x |X es oo| ae aif € aq o ol x ep xe] oe x [ey | X o) TI], Wy A ory y =P sh, wi% xf pe fv) « pe tp | x eee a-a} ble ya Fa |] to 1} XTX | we x 1% wo |x x L = = 8 Tg= 9 Jy = Gs 8,8, Ry : . ' or ot LL Lo Qk) —2 4 3 2 00 7 K \I% ul|s aly «¢ o1 i KUL D 3 5 \y y |X px K o n to} 1D : x %Stepas ke emap’S @e\ io oft as i = 2 ays 3 oe oo] * {|X y 2 ae ee 7 ci 6 s 7 ol SNe offi sf x | x | <5 my 8] sf a nb ely ety Toa def x x ay yf a Ve v0 x {ibd mye sl ‘ be = ed dhe 2 Q, agree OL Lu 10, a Z oo} [|X . l 7 ®\ t nyt of [xe it Lad | Steps s: tegic diagram .> pesign of synebronous Modulo- 6 Gray Sede. - =~ oe —— = ‘ countey : COUNLEY 5 Number of -Ftip-Hops 24 StePI. of modulo—6@ Gray the Coe sequence code coudtey $$ 000, OO!, OI!) 10, 10, Tl. SEEPR? state diagram cay 000, PS NS ] Required excitations T G3 8291 8368.8, | T30de wl ro 0 © oo} o oO i GO) ol) o : oO oO. o10 oO oO I or OJ 11 ® \ o (oO ve OF tr 0 6 tt 1) oo0 \ \ iSepa Mininal Expsessions \e8 ae a oo a4 oO. Wy 10 a o 6! “ oO xu Na 83+ 929+ BL8, Steps Logic diagraro O29) “ B39) =_ ) Pa oN BS > ash i 5H —— Ups 3 2 wm pe eae rp PG ae Si- ie : __toe ‘Register Counters m4 shett wegistey counters axe obtained from serfal-in, serial- oul shift vreqisters by Providing ~feedbock trom the out pu of the last FR to the ‘input of “+he _-tivet FF- +> these devices ove called counters becouse they exhibit a dpecthied Sequence of States . > “The most widely used shite reqioter counte is the slog counter as well as the twisted a) counter - “Rig Counter ; _— > The FFs ove amanged 08 to @ normal shift nati te the Q@_ outpub of each Shoge connected to the D fopat of the ext Stoge » but the @ output of the lost EF is connected back to the D foput- of the erst FR such That the array of Fro ts aeworged to 9 vind, therene, the came sing counter .a ‘ a counter rege diagrarn of a 4-bit sing Couns dee a ising Br 4lp--Hlops ] ' C fs, 3 {88 3, 8, 5 Bul fh ee C4 FP rep FF oe Or feat] Pe Ray Sa ilaal fe =y S Owe bogie chagrarm ot a g-bk ae countey using Sq flip-flop ” 2 : 3 o 2 2 1000 State d iagran oO oO \ oO oO oO 1 oO: ted xing counter Ciohm 309 counter . a SSS > Ris counter fg obtained = from a Serial -fo gexial- out shift neq ister by Providing feedbacks from the Soverted output of the lst fF to the D Sopuk- of he fysk FR > The Q@ ottpul of each stage is connected to -the op foput of @Q outpuk of the last stage to the D iopuk of first stag?, therefore , eounokey - the name esisted wi us bogie diagroo of 4-bit rO7 usin DOA Logic diagra of Gb wing count using 3-6 -tiip- Hep. - aa8.9.93 84 “Renin diagracn ot a_4-bit “twhsted x ng countey-3ya) design a countey with the following wepeated binaa sequence + 0, 2%) 6. osin O- FIipFlo 4 q 3 PFlop Step :- Wo: of flipflops: the counter has 5 stable States O214,6 (ooo, C01, oto, 100, 110), St sequires 3 FlipFlops which has eight States in which yemMaini 3 are onused stotes- These unused “states MUSE go to 00 apes the nee cloch pulse- go, no dort coxes- step &:- State Diagzam A step 3 ¢ The type of = flipflop and excitation “Table Ps NS Requized Excitations @® % % a Og By 9, o0o°0 o Oo} O° ro) ' oo | o 1 90 oO | oO Oo 1 6 1o°0 \ oO oO Oo 1 | oOo 0 oO Oo ° {oo tae) } | Oo ( 01 | 000 ° Oo oO no) 0° 0 Oo ° ° o °9O °Step Wi- The Minimal Expressfons 4- fox D3 for Og ahs 8) AY" 00 1 aN bo, 01 uo ° ° - ° oy of lat] 2[* Tia Ss Fl 6 im! =] APs D3 > Q, 8,8 + 9, @,@, Dy = 9, 2, + @% @ @, fox p, these fs no minimization possible $, > B38, Step st dogic — Biagzam :-Write , deginitions of teuth table, State toble, Excitationtable ‘chowactesi stic Table a . Tsuth+table t- The tsuth table of gq logic system descuibes the Outputs of the System for a given dnputs: The Anput s and utputs axe Sed +0 abel the columns of teuth table, Inputs +o the ciraxit With —wWWs representing all possible ond — the cosxesponding — ©utputs State igble~ A table descaibing the behaviour of a Sequenti -al — ctreutt aos a function of stable Snternat conditions- States— and dnput variables - Excitation Table 8- An , Excitation table Shows the minimum necessary to generate state = when the current State is input that aze Q particulad neat Known. characteristic tables- The characteristic table hag the Contso) 4mput CD os T) as the first column, the cussent state as the middie caluma, and tne Nexvt State as the last © coloumn. 44° usuatty tetls how the Control bit ePpect, the cussent State to ptoduce the Next State. write the diggevences, between catch and Pip-#lop no | Paxometex |__FUtprtop Latch N 1) | Basic principte Flipelop Utilizes | atch follows a 7 an edge ty(qq- devel triggering ji Approach. ering approchSNO Parameter Flip flop datch a) clock signal The cloc The clock Signal 1S signal fs present absent~ ou i 3) pesigned using you . on 4 can design design * fk using using Latches sogic gates: along with clocts 4H has compara- é hos O 4) Operating at : a 4 fost speed stow — opesatting ar speed Opesating Speed 5) sor King FlIpFlops worls atotches operate using the onty using binosy Sle binary a(pic and clock signas 8) Types F-Wjs+e, 0,7 Ty $-8,0) T Flip Flops catcher 4) Fauttt FlipFlops stay tthe Latches protected agaist ave vesponsit to ANY -foutt any. Occuryin 9 foull on enable pin.Te 1414 & Lom etipeter) at at ee Cla PRs 1 Qa :Q, yt |B 12 _ vol [a : t gf ~@ Z 1} 18} 13] Ls sfleJ/ i cig; = Ol cis) PR, @ GaN Tc 1u76 s+ (3-¥ Hiprlor) Ik 1@) (@ GND aw QQ aq. at te] [es] [a | | ig] [1] [0 4 — HL LI (I | Uy ¢cIR \Q| 7 PRG an I |] le ia t 7 a I =a —— ' | a 3 | y =] 2] 4 L fas (PRC = Vee Adlh AcIk APRTc 1415 8- 4 BH Bt-stable datch Te 1@ ag BG 1-2 GND 39 30, HO wi fs| [ul fal [al [ud] el 19 SS Le pale a Wo ic ably Lh ih | art all) {= ee del 2l@IEsl cs 7] (110. 9D. (3MC | Mec 13D GD. . Le Te WGI s- Y- bit wvipple- type decade counter anges ne On Q@® ae a Qe ty [re fro 4 g ' | Ldn Sa Rp a Q Li | A , B Ali) _2ol2) cn ¥ 7 | ( al 3 q | 5 6 | j Inpuk Ret) RAY NO Vee Rg td &y (a) &Ic 1493 g- Y-bit Binasy Counter efscutt- Tp a Me On Ro cen fi Ju Tio | Sp Te 1u93 ( 8 ie Is? fea RM) RQ) Ne Vee Ne fc Te 74lal s- Monostable muttivibrator usithy schmitt - trigger tles