The IBM System/360
The idea of an Instruction Set Architecture to express computation
Managing complexity with abstraction layers
Application Software
Operating System (OS)
Instruction Set Architecture (ISA)
Hardware
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IBM’s predicament and gamble
Model Year(s) Domain Notes on instruction set • What is the problem?
• Instructions: 18-bit length
Scientific • Data: 18- or 36-bit sign-magnitude, fixed-point
IBM 701 1952
computing numbers
• Two programmable registers
• The “gamble” would
• Instructions: 5-character length cost 100s of billions of
IBM 1953- Business data • Data: Variable-length character strings
dollars in today’s
702 1955 processing • Two programmable registers (512 characters
each)
money
• Instructions: 36-bit length
• Data: Support for floating point
• Several programmable registers, with different
IBM Scientific
704
1954
computing
lengths • What was the gamble?
• The high-level languages FORTRAN and LISP first
developed for this machine
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The gamble: Architecture of the IBM System/360
Gene Amdahl Gerrit Blaauw Fred Brooks
By Perry Kivolowitz. CC BY 3.0 By HandigeHarry. Public Domain By SD&M. CC BY-SA 3.0
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The four IBM System/360 innovations
From the paper abstract:
1. An approach to storage which permits and exploits very large capacities, hierarchies of speeds, read-
only storage for microprogram control, flexible storage protection, and simple program relocation.
2. An input/output system offering new degrees of concurrent operation, compatible channel operation,
data rates approaching 5,000,000 characters/second, integrated design of hardware and software, a
new low-cost, multiple-channel package sharing main-frame hardware, new provisions for device
status information, and a standard channel interface between central processing unit and
input/output devices.
3. A truly general-purpose machine organization offering new supervisory facilities, powerful logical
processing operations, and a wide variety of data formats.
4. Strict upward and downward machine-language compatibility over a line of six models having a
performance range factor of 50
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What’s next?
• A look at the IBM System/360 and how it established the ISA as an
interface that abstracts the hardware
• A summary of important design decisions made in the IBM System/360
• A reflection on the impact of the IBM System/360
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Design objectives
“The functions of the central processing unit (CPU) proper are specific to its application only a minor fraction
of the time.”
Inter-model compatibility
A definition of “strictly program compatible” from the paper:
A valid program, whose logic will not depend implicitly upon time of execution and
which runs upon configuration A, will also run on configuration B if the latter
includes at least:
• the required storage,
• the required I/O devices, and
• the required optional features
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A general-purpose
machine structure
Each block shows how a model might be
configured.
• Model 30 is smaller/slower/cheaper than the
Model 70
Note the registers; every model has:
• Sixteen 32-bit general-purpose registers
• Four separate 64-bit floating point registers
Note the changes in width:
• Data flow width: Model 30’s 8-bit vs Model
70’s 64-bit
• Storage width: Model 30’s 8-bit vs. Model
70’s 64-bit
Amdahl, Gene M., Gerrit A. Blaauw, and Frederick P. Brooks. "Architecture of the IBM System/360." IBM Journal of Research
and Development 8.2 (1964): 87-101.
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Size of a character
Size of a float
Memory alignment
Register model
Design decisions
An evaluation of trade-offs
The size of a character
• Remember: memories are still “small” – the size of data matters
• The size of a character is the minimum addressable element
• Alphanumeric characters need 6 bits
• Decimal digits need 4 bits
• The 6-bit character • The 4-/8-bit character
• Wastes 2 bits on decimal digits • 4 bits used for decimal digits
• Used in IBM 702-7080 and 1401-7010 • 8 bits used for alphanumeric (2 bits
families wasted)
• Used in the IBM 650-7074 family
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The size of a floating-point number
• The size of a floating-point number impacts the
• time to perform operations like addition and multiplication (larger is longer)
• precision of represented numbers (larger is more precise)
• 48-bit floating point • 32-/64-bit floating point
• No option between “low” and “high” • The client decides on the
precision speed/space versus tradition trade-
off
• 32-bit is “single precision”
• 64-bit is “double precision”
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The alignment of data in memory
• Different models have different widths, so different preferences for alignment
• Model 30 would prefer 8-bit alignment
• Model 70 would prefer 64-bit alignment
• Recall that memory is byte addressable (size of a character is 8 bits)
• The adopted rule: Each fixed field must begin at a multiple of its field length
• e.g., all memory addresses of doubles (64 bits = 8 bytes) are found at multiples of 8
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Pushdown stack versus addressed registers
Pushdown stack Addressed registers
• Operands to an operation are implicit • Operands to an operation are explicit
e.g, Z = X + Y in a stack architecture: e.g., Z = X + Y in a System/360 model:
push X # stack[top++] = mem[X] Load R1, X # R1 = mem[X]
push Y # stack[top++] = mem[Y] Add R2, R1, Y # R2 = R1 + mem[Y]
add # stack[top++] = stack[--top] + stack[--top] Store R2, C # mem[C] = R2
pop Z # mem[Z] = stack[--top]
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Other design decisions
• Addresses are in binary, not decimal
• Several design decisions that allowed for an “operating system” to work
• Asynchronous operation of I/O (via interrupts)
• Supervisor calls
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Conclusion
What are the implications?
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The design decisions “stuck”
The “small” decisions The “big” decisions (gambles)
• The 8-bit byte • Separate the instruction set architecture from
• Byte-addressable memory its hardware implementation
• 32-bit words, 32-bit floats, 64-bit doubles • Ensure binary compatibility across models
with different specs
• Addressed general-purpose registers
• The Basic Operating System BOS/360
released in 1965 (a year after the
System/360)
• DOS/360, its successor, was the most widely
used OS in the world
The IBM Telum II Processor
Introduced at Hot Chips 2024:
• Eight 5.5 GHz cores
• Ten 36 MB L2 caches
• An I/O accelerator
• An AI accelerator
• Backwards compatible with the IBM
System/360!
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