MOS Transistor Operation

Gate
S/D S/D

Channel
width (W)
Oxide

n+ Channel Length (L) n+

Substrate (p-Si)

¾ MOS is four-terminal device

¾ if the fourth terminal is not shown it is assumed to be
connected to the appropriated voltage (lowest and highest
supply voltage value for NMOS and PMOS, respectively)

Prof. Gaetano Palumbo 1

VG < Vto VG > Vto

Oxide Oxide
n+ Depletion region n+ n+ n+

Substrate region (p) p Inversion layer (channel)

¾ The diffusion junction are reverse-biased (to achieve this

condition the bulk voltage must in NMOS be always lower
than the other node voltages)
¾ A gate voltage greater than the Threshold Voltage,
Voltage Vto, is
needed to create a surface inversion
¾ The depth of the inversion layer is independent from gate
voltage

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 VG > Vto
0 < VD < VDSsat
VS = 0
ID

Oxide
Source Drain
n+ n+

¾ When the inversion layer is established an n-type conduction

channel between source and drain is formed
¾ For small drain voltage a current proportional to drain voltage
fl
flows i the
in h channel:
h l linear
l b h i (linear
behavior (li or triode
i d region)
i )
¾ in the linear region the MOS acts like a voltage-controlled
resistor (the control input is the gate node)

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VG > Vto
VD = VDSsat
VS = 0
ID

Oxide
Source Drain
n+ n+
p Pinch-off p
point

¾ The linear region holds until the drain voltage reaches the VDSsat
value
¾ Under this condition the inversion layer at the drain is reduced
to zero: Pinch-off
h ff point
i
¾ This condition is the border between the linear and the
saturation region

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 VG > Vto
VD > VDSsat
VS = 0
ID

Oxide
Source Drain
n+ n+
p Pinch-off point

¾ Beyond the pinch-off point (VD>VDSsat) a depleted surface

region forms adjacent to the drain: Saturation region

¾ The depleted surface grows toward the source with increasing

drain voltage the effective channel length is reduced

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VG > Vto
VD > VDSsat
VS = 0
ID

Oxide
Source Drain
n+ n+
p Pinch-off point

¾ The pinched-off (depleted) section absorbs most of the excess

voltage drop VDS-VDSsat.
¾ Electrons arriving from the source through the channel are
injected into the drain-depletion region and are accelerated
toward the drain in this high electric field

Prof. Gaetano Palumbo 6

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 MOS Threshold Voltage
¾ It is due to 4 physical component

1) the
th workk function
f ti diff
difference b t
between th gate
the t andd the
th
channel (built-in potential of the MOS structure)
2) the voltage needed to change the surface potential
3) the voltage to offset the depletion region charge
4) the voltage to offset the fixed charge in the silico-oxide
interface (and in the gate oxide)
Q Q
Vt = φms − 2φF − B − ox
Cox Cox
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¾ The Flat-Band voltage,VFB,is the built-in offset across the

MOS structure, it is

Q Q
VFB = φms − ox Vt = VFB − 2φF − B
Cox Cox

¾ VFB, φF and Cox (=εox/tox) are technology parameters

¾ QB depends on the source-bulk voltage

QB = − 2qNAεsi − 2φF +VSB

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 (
Vt =Vto +γ −2φF +VSB − −2φF )

¾ Vto, is the threshold voltage for VBS=0

Q
Vto = VFB − 2φF − B0
QB0 = − 2qNAεsi − 2φF Cox

2qεsiNA
¾ γ is the body-effect coefficient γ=
Cox

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MOS Current-Voltage characteristic

¾ Use of the gradual channel approximation

¾ reduce
d th analysis
the l i tot a one-dimensional
di i l current-flow
t fl problem
bl
¾ the approximation is heavy for small-geometry MOS

VG > Vto
0 < VD < VDSsat
VS = 0
ID

Oxide
Source Drain
n+ n+
y
p x

y=0 y=L

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¾ Assume the threshold voltage, Vto, constant along the channel
from y=0 to y=L (this is an approximation since the channel
voltage is not constant)
¾ Assume the electric field component, Ey, along the y-
coordinate is dominant compared to the one along the x-
coordinate, Ex (allows to reduce the current flow only to the y-
dimesion)
¾ The channel voltage, VC(y),with respect to the bulk is: VC(0)=0
and VC(L)= VD

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¾ The total mobile electron charge in the surface inversion layer,

QI(y), is QI ( y ) = −Cox ⋅ [VG − Vc ( y ) − Vto ]

y=L Channel
y=0 Channel length = L width = W

dy Drain end

Source end
Inversion layer (channel)

¾ Assuming all mobile electrons with a constant surface

mobility, μn, the incremental resistance, dR, is (the minus sign is for

the negative polarity of QI(y)) dy

dR = −
W ⋅ μ n ⋅ QI ( y )

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 Applying Ohm’s law along y-direction and then integrating
from 0 to L
L VDS
ID
dVc = I D ⋅ dR = −
W ⋅ μ n ⋅ QI ( y )
⋅ dy ∫ I D ⋅ dy = −W ⋅ μn ∫ QI ( y ) ⋅ dVc
0 0

VDS
I D ⋅ L = W ⋅ μ n ⋅ COX ∫ (VG − Vc − Vto ) ⋅ dVc
0

μ ⋅C W 2
I D = n ox ⋅ ⋅ [ 2 ⋅ (VG − Vto )VDS − VDS ] Linear region
2 L

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¾ The current voltage curves are inverted parabolas for each

constant VG
¾ The peak of the parabolas is at VDS = VG-Vto . Pinch-off occurs
¾ The theoretical behavior of the drain current is decreasing after
the peak, but it is unrealistic and the current is ideally constant

For VDS > VG-V

Vto = VDSsat
DS

μ ⋅C W
I D = n ox ⋅ (VG − Vto ) 2 Saturation region
2 L

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 μ ⋅C W
I D = n ox ⋅ ⋅ [ 2 ⋅ (VGS − Vt )VDS − VDS
2
] Linear region
2 L

μ ⋅C W
I D = n ox ⋅ (VGS − Vt ) 2 Saturation region
g
2 L

ID ID
VD V D VS Depletion
VG VG VG
VB VB Vto<0 ID

VS V D VD
VS
VG
ID VB

¾ μn, Cox are technological parameter, VS

¾ Vt is both technological and electrical parameter

¾ W/L is the design parameter

Prof. Gaetano Palumbo 15

PMOS Current-Voltage characteristic

μ p ⋅ Cox W
ID = ⋅ ⋅ [ 2 ⋅ (VSG + Vt )VSD − VSD
2 =
]
2 L
μ ⋅C W
Linear region
g
= p ox ⋅ ⋅ [ 2 ⋅ ( VGS − Vt ) VDS − VDS
2
]
2 L

μ p ⋅ Cox W
ID = ⋅
(VSG + Vt ) 2 = Saturation region
2 L
μ ⋅C W
= p ox ⋅ ( VGS − Vt ) 2 ID
2 L ID
VS VS VD
VG VG VG
VB VB
VD VD VS
ID

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 Channel Length Modulation
VG > Vto
VD > VDSsat
VS = 0
ID
L ' = L − ΔL
ΔL
O id
Oxide
1− ≈ 1 − λ ⋅ VDS
Source Drain
n+ n+ L
y
p

y=0 L' L
0.01 V-1 < λ < 0.05 V-1
ΔL (20 V < 1/λ < 100 V )
μ C W
I D ( sat ) = n ox ⋅ (VG − Vto ) 2 (1 + λVDS )
2 L

¾ λ is function of the length L. It is is higher for lower L

¾ More accurately ΔL ∝ VDS − VDSAT

Prof. Gaetano Palumbo 17

Short channel MOS

¾ Due to the high Electric field μn is not constant

μno
μn =
VDS + η (
1+ VGS − Vt )
Ey L

Longitudinal field Vertical field

μ
¾ In saturation VDS= VDSsat θ = 1 + η ≈ 1 = no
EyL Ey L vmax L
θ = 0.01 ÷0.8
C μ no W
I D ( sat ) = ox ⋅ ⋅ (VG − Vto ) 2 (1 + λVDS )
2 1 + θ (VGS − Vt ) L

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 Sub-threshold MOS
¾ If VGS ≈ Vt the transistor is not completely off: Subthreshoil
region (or weak inversion)

VGS ⎛ −VDS ⎞
W nVT ⎜ ⎟
ID = Kx e ⎜1 − e T
nV
⎟
L ⎜ ⎟
⎝ ⎠

¾ Exponential model like bipolar transistor

¾ Kx process parameter,
¾ n≈1.5

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