International Journal for Modern Trends in Science and Technology

Volume: 03, Issue No: 07, July 2017

ISSN: 2455-3778
http://www.ijmtst.com

HDL Implementation of New Performance

Improved CSLA Gate Level Architecture
S.Sai Kiran1 | M.Srinivasa Rao2

1PG Student, Department of ECE, Vasireddy Venkatadri Institute of Technology, Nambur, Andhra Pradesh, India.
2Assistant Professor, Department of ECE, Vasireddy Venkatadri Institute of Technology, Nambur, Andhra Pradesh, India.

To Cite this Article

S.Sai Kiran and M.Srinivasa Rao, “HDL Implementation of New Performance Improved CSLA Gate Level Architecture”,
International Journal for Modern Trends in Science and Technology, Vol. 03, Issue 07, July2017, pp.-338-344

ABSTRACT
In this brief, the logic operations involved in conventional carry select adder (CSLA) and binary to excess-1
converter (BEC)-based CSLA are analyzed to study the data dependence and to identify redundant logic
operations. We have eliminated all the redundant logic operations present in the conventional CSLA and
proposed a new logic formulation for CSLA. In the proposed scheme, the carry select (CS) operation is
scheduled before the calculation of final-sum, which is different from the con-ventional approach. Bit patterns
of two anticipating carry words (corresponding to cin = 0 and 1) and fixed cin bits are used for logic
optimization of CS and generation units. An efficient CSLA design is obtained using optimized logic units.
The proposed CSLA design involves significantly less area and delay than the recently proposed
BEC-based CSLA. Due to the small carry-output delay, the proposed CSLA design is a good candidate for
square-root (SQRT) CSLA. A theoretical estimate shows that the proposed SQRT-CSLA involves nearly 35%
less area–delay–product (ADP) than the BEC-based SQRT-CSLA, which is best among the existing
SQRT-CSLA designs, on average, for different bit-widths. The application-specified integrated circuit (ASIC)
synthesis result shows that the BEC-based SQRT-CSLA design involves 48% more ADP and consumes 50%
more energy than the proposed SQRT-CSLA, on average, for different bit-widths.

Index Terms: Adder, arithmetic unit, low-power design.

Copyright © 2017 International Journal for Modern Trends in Science and Technology
All rights reserved.

early years carry look ahead adder used to

I. INTRODUCTION overcome the delay it will produce all produce all
VLSI stands for Very large scale integration the carries at time but it requires more circuitry,
which refers to those integrated circuits that next those are replaced by carry select adders
contain more than 107 transistors. Designing such using dual RCAs. In this sum is generated for
circuit is difficult and that design needs to Cin=1 and Cin=0, depends on input carry one sum
overcome the VLSI design problem like Area, is passed as final sum using multiplexer. The
Speed, Power dissipation, Design time and problem is again, it requires more circuitry because
Testability.In digital adders, the speed of addition it requires two full adders at each stage of three
is limited by the time required to propagate a carry bits addition.That is replaced by one RCA and one
through the adder.The sum for each bit position in add-one circuit. There again the same problem that
an elementary adder is generated sequentially only is eliminated by this proposed system CSLA using
after the previous bit position has been summed BEC.The basic idea of this work is to use Binary to
and a carry propagated into the next position.The Excess-1 Converter (BEC)instead of RCA with Cin=

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 S.Sai Kiran and M.Srinivasa Rao : HDL Implementation of New Performance Improved CSLA Gate Level Architecture

1 in the regular CSLA to achieve lower area and

power consumption.
The Ripple Carry Adder (RCA) provides the most
compact design but takes longer computing time. If
there is N-bit RCA, the delay is linearly
proportional to N.Thus for large values of N the
RCA gives highest delay of all adders. The Carry
Look Ahead Adder (CLA) gives fast results but
consumes large area. If there is N-bit adder, CLA is
fast for N≤4, but for large values of N its delay
increases more than other adders.So for higher
number of bits, CLA gives higher delay than other Figure 2.1. 4-bit BEC
adders due to presence of large number of fan-in
and a large number of logic gates.The Carry Select 2.2 Delay and Area Evaluation Methodology
Adder (CSA) provides a compromise between small 2.2.1 Modified 16-Bit CSLA
area but longer delay RCA and a large area with To optimize the area and power we are using BEC
shorter delay CLA.In rapidly growing mobile for RCA with Cin=1 for the 16-bit CSLA is shown in
industry, faster units are not the only concern but the Figure 4.3. The structure is again divided into
also smaller area and less power become major five groups, and the delay and area estimation of
concerns for design of digital circuits. In mobile each group are shown.
electronics, reducing area and power consumption
are key factors in increasing portability and battery
life. Even in servers and desktop computers power
dissipation is an important design constraint.
Design of area- and power-efficient high-speed
data path logic systems are one of the most
substantial areas of research in VLSI system
design. In digital adders, the speed of addition is
limited by the time required to propagate a carry (a) (b)
through the adder.

II. MODIFIED 16-BIT CARRY SELECT ADDER

2.1 Introduction
In order to reduce the area and power
consumption of the regular CSLA, we will use BEC
instead of the RCA with Cin=1, which is our main
idea of the work. An n+1 -bit BEC is required to (c)
replace the n-bit RCA. Figure 2.1 and Table 4.1
shows a structure and the function table of a 4-b
BEC and Figure 4.2 illustrates how the basic
function of the CSLA is obtained by using the 4-bit
BEC together with the multiplexer (mux). One
input of the 2:1 mux gets as it input (A3, A2, A1,
and A0) and another input of the mux is the BEC
output. There by we get two possible partial results
in parallel and according to the control signal Cin
the mux is used to select either the BEC output or
the direct inputs. When the CSLA with large (d)
Figure 2.2. Delay and area evaluation of modified CSLA: (a)
number of bits are designed, the BEC logic stems group2 (b)group3 (c) group4 and (d) group5 .H is a half adder.
from the large silicon area reduction.

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 S.Sai Kiran and M.Srinivasa Rao : HDL Implementation of New Performance Improved CSLA Gate Level Architecture

The steps leading to the evaluation are given Therefore, two copies of ripple-carry adder act as
here. carry evaluation block per select stage. One copy
1) In the Figure 2.2 (a) i.e. the group2 consist of 1 evaluates the carry chain assuming the block
FA and 1 HA for Cin=0 in one 2-bit RCA. We are carry-in is zero, while the other assumes it to be
using a 3-bit BEC instead of another 2-bit RCA one. Once the carry signals are finally computed,
with Cin=1 which adds one to the output the correct sum and carry-out signals will be
consideration of delay values of Table 1, the arrival simply selected by a set of multiplexers. The 4-bit
time of selection input the s3(t=9) is harder than adder block is RCA Systems are one of the most
the arrival time of selection input c1(time(t)=7) of substantial areas of research in VLSI system
2:1 mux and c3(t=10) and later than the design. In digital adders, the speed of addition is
s2(t=4).The s3 and mux and partial c3 (input to limited by the time required to propagate a carry
mux) and mux are responsible for getting the sum3 through the adder. The sum for each bit position in
and final c3 (output from mux).The sum2 depends an elementary adder is generated sequentially only
on c1 and mux. after the previous bit position has been summed
2) The arrival time of data inputs from the BEC‟s is and a carry propagated into the next position.The
always lesser than the arrival time of mux CSLA is used in many computational systems to
selection input for the remaining group‟s. The alleviate the problem of carry propagation delay by
arrival time of mux selection input and the mux independently generating multiple carries and then
delay will decides the delay of the remaining select a carry to generate the sum. However, the
groups. CSLA is not area efficient because it uses multiple
3) The area count of group2 is determined as pairs of Ripple Carry Adders (RCA) to generate
follows: Gate count = 36(FA + HA + Mux + BEC) partial sum and carry by considering carry input
FA = 1(1*9 = 9) HA = 1 (1*5 = 5) AND = 1 and, then the final sum and carry are selected by
NOT = 1 the multiplexers (MUX).
XOR = 2 (2*4 = 8) The carry-select adder generally consists of two
Mux = 3 (3*4 = 12) ripple carry adders and a multiplexer. Adding two
4) Similarly, the Table 4.4 shows the estimated n-bit numbers with a carry-select adder is done
maximum delay and area of the other groups of the with two adders (therefore two ripple carry adders)
modified CSLA. in order to perform the calculation twice, one time
By considering only 11 increases in gate delays, with the assumption of the carry being zero and the
it is clear that the proposed modified CSLA saves other assuming one. After the two results are
56 gate areas than the regular CSLA, which is clear calculated, the correct sum, as well as the correct
by comparing Table 1 and Table 2.To further carry, is then selected with the multiplexer once
evaluate the performance, we have resorted to the correct carry is known. The number of bits in
ASIC implementation and simulation. each carry select block can be uniform, or variable.
In the uniform case, the optimal delay occurs for a
Table 1 Delay and area count of modified CSLA groups
block size of n variable, the block size should have
Group Delay Area a delay, from additional inputs A and B to the carry
out, equal to that of the multiplexer chain leading
Group2 13 36 into it, so that the carry out is calculated just in
time. The delay is derived from uniform sizing,
Group3 16 54 where the ideal number of full-adder elements per
block is equal to the square root of the number of
Group4 19 72 bits being added, since that will yield an equal
number of MUX delays.Two 4-bit ripple carry
Group5 22 90 adders are multiplexed together, where the
resulting carry and sum bits are selected by the
carry-in. Since one ripple carry adder assumes a
2.2.2 OPERATION :
carry-in of 0, and the other assumes a carry-in of 1,
Carry Select Adders (CSA) is one of the fastest
selecting which adder had the correct assumption
adders used in many data-processing processors to
via the actual carry-in yields the desired result. A
perform fast arithmetic functions. The carry-select
16-bit carry-select adder with a uniform block size
adder partitions the adder into several groups,
of 4 can be created with three of these blocks and a
each of which performs two additions in parallel.
4-bit ripple carry adder. Since carry-in is known at

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 S.Sai Kiran and M.Srinivasa Rao : HDL Implementation of New Performance Improved CSLA Gate Level Architecture

the beginning of computation, a carry select block send to the output. Multiplexers are mainly used to
is not needed for the first four bits. The delay of this increase the amount of data that can be sent over
adder will be four full adder delays, plus three MUX the network within a certain amount of time and
delays.A 16-bit carry-select adder with variable bandwidth. A multiplexer is also called a data
size can be similarly created. Here we show an selector. An electronic multiplexer makes it
adder with block sizes. This break-up is ideal when possible for several signals to share one device or
the full-adder delay is equal to the MUX delay, resource, for example one A/D converter or one
which is unlikely. The total delay is two full adder communication line, instead of having one device
delays, and four MUX delays. per input signal.
Addition is the heart of computer arithmetic, In digital circuit design, the selector wires are of
and the arithmetic unit is often the work horse of a digital value. In the case of a 2-to-1 multiplexer, a
computational circuit. They are the necessary logic value of 0 would connect to the output while a
component of a data path, e.g. in microprocessors logic value of 1 would connect to the output. In
or a signal processor. There are many ways to larger multiplexers, the number of selector pins is
design an added. The Ripple Carry Adder (RCA) equal to where is the number of inputs.A 2-to-1
provides the most compact design but takes longer multiplexer has a Boolean equation where and are
computing time. If there is N-bit RCA, the delay is the two inputs, is the selector input, and is the
linearly proportional to N. Thus for large values of output
N the RCA gives highest delay of all adders. The
Carry Look Ahead Adder (CLA) gives fast results 3.1 WHY WE REPLACED REGULAR CSLA WITH
but consumes large area. If there is N-bit adder, MODIFIED CSLA?
CLA is fast for N≤4, but for large values of N its  Regular CSLA has 2 ripple carry adders (RCA)
delay increases more than other adders. So for in each module for performing addition
higher number of bits, CLA gives higher delay than depending on carry.
other adders due to presence of large number of  Using 2 RCAs in each module increases the
fan-in and a large number of logic gates. The Carry number of transistors.
Select Adder (CSA) provides a compromise between  Increase in number of transistors leads to
small area but longer delay RCA and a large area increase in area and power consumption.
with shorter delay CLA.In rapidly growing mobile
industry, faster units are not the only concern but 2nd RCA in each module can be replaced by
also smaller area and less power become major binary to excess one converter which performs the
concerns for design of digital circuits. In mobile same operation with less number of transistors
electronics, reducing area and power consumption which leads to modified CSLA which is area
are key factors in increasing portability and battery efficient and low power consumption
life. Even in servers and desktop computers power
dissipation is an important design constraint.
Design of area- and power-efficient high-speed IV. DEVELOPED ADDER DESIGN
data path logic systems are one of the most The developed CSLA is based on the logic
substantial areas of research in VLSI system formulation given in (5a)–(5g), and its structure is
design. In digital adders, the speed of addition is shown in Fig. 3(a). It consists of one HSG unit, one
limited by the time required to propagate a carry FSG unit, one CG unit, and one CS unit. The CG
through the adder. The sum for each bit position in unit is composed of two CGs (CG0 and CG1)
an elementary adder is generated sequentially only corresponding to input-carry „0‟ and „1‟. The HSG
after the previous bit position has been summed receives two n-bit operands (A and B) and generate
and a carry propagated into the next position. half-sum word s0 and half-carry word c0 of width n
Among various adders, the CSA is intermediate bits each. Both CG0 and CG1 receive s0 and c0
regarding speed and area. from the HSG unit and generate two n-bit full-carry
words c01 and c11 corresponding to input-carry „0‟
III. MULTIPLEXER and „1‟, respectively.The logic diagram of the HSG
In electronics, a multiplexer (or MUX) is a device unit is shown in Fig. 3(b). The circuits of CG0 and
that selects one of several analog or digital input CG1 are optimized to take advantage of the fixed
signals and forwards the selected input into a input-carry bits. The optimized designs of CG0 and
single line multiplexer of 2n inputs has n select CG1 are shown in Fig. 3(c) and (d), respectively.The
lines, which are used to select which input line to CS unit selects one final carry word from the two

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 S.Sai Kiran and M.Srinivasa Rao : HDL Implementation of New Performance Improved CSLA Gate Level Architecture

carry words available at its input line using the calculation. Instead, one can select the required
control signal cin. It selects c01 when cin = 0; carry word from the anticipated carry words {c0
otherwise, it selects c11. The CS unit can be and c1} to calculate the final-sum. The selected
implemented using an n-bit 2-to-l MUX. However, carry word is added with the half-sum (s0) to
we find from the truth table of the CS unit that generate the final-sum (s).Using this method, one
carry words c01and c11 follow a specific bit can have three design advantages:
pattern.If c01 (i) =„1‟,then c11(i) =1,irrespective of 1) Calculation of s01 is avoided in the SCG unit; 2)
s0(i) and c0(i), for 0 ≤ i≤ n − 1. This feature is used the n-bit select unit is required instead of the (n +
for logic optimization of the CS unit. The optimized 1) bit; and 3) small output-carry delay. All these
design of the CS unit is shown in Fig. 5(e), which is features result in an area–delay and
composed of n AND–OR gates. The final carry word energy-efficient design for the CSLA
c is obtained from the CS unit.The MSB of c is sent
to output as cout, and (n − 1) LSBs are XORed with The developed architecture has been simulated
(n − 1) MSBs of half-sum (s0) in the FSG [shown in and synthesized on FPGA XC3S400K using XILINX
Fig. 3(f)] to obtain (n − 1) MSBs of final-sum(s). The ISE-12.4 tool.The performance of three proposed
LSB of s0 is XORed with cin to obtain the LSB of adders are evaluated and they are implemented
s.The proposed logic formulation for the CSLA is using VHDL.
given as

V. SIMULATION & SYNTHESIS RESULTS FOR

DEVELOPED 16BIT CSLA.

The simulation result of our designed 16bit carry

select adder is shown below

Figure 4 Simulation result for developed 16 bit CSLA

From the above simulation result of proposed

carry select adder 16 bit the operands a,b are
inputs with cin whereas c10&c11 are carry outputs
Figure 3.(a) Proposed CS adder design, where n is the input when cin =0 or cin=1.The final sum is s and final
operand bit-width, and [∗] represents delay (in the unit of inverter
delay), n = max(t, 3.5n + 2.7).(b) Gate-level design of the HSG. (c)
carry is c. As we are adding two 16 bits we obtain
Gate-level optimized design of (CG0) for input-carry = 0. (d) 32 bits as output with one carry bit.
Gate-level optimized design of (CG1) for input-carry = 1 (e)
Gate-level design of the CS unit. (f) Gate-level design of the
final-sum generation (FSG) unit.

In the case of the BEC-based CSLA, c11

depends on s01, which otherwise has no
dependence on s01 in the case of the conventional
CSLA.The BEC method therefore increases data Table 2 Device utilization summary for developed 16bit CSLA
dependence in the CSLA. We have considered logic
expressions of the conventional CSLA and made a
further study on the data dependence to find an
optimized logic expression for the CSLA.We find
that a significant amount of logic resource is spent
for calculating {s01, s11}, and it is not an efficient
approach to reject one sum-word after the

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 S.Sai Kiran and M.Srinivasa Rao : HDL Implementation of New Performance Improved CSLA Gate Level Architecture

5.1 RTL SCHEMATIC VI. CONCLUSION

Thus logic operations involved in conventional
carry select adder (CSLA) and binary to excess-1
converter BEC-based CSLA are reduced and
analyzed to study the data dependence and to
identify redundant logic operations. Here
eliminated all the redundant logic operations
present in the conventional CSLA, BEC- CSLA and
Figure 5 RTL schematic for developed 16bit CSLA proposed a new logic formulation for CSLA. In the
5.2 COMPARISON CHARTS OF PERFORMANCE developed scheme, depending on the initial carry
PARAMETERS OF EXISTING MODELS AND the total operation decides the operation of two
DEVELOPED MODEL individual blocks which itself generates the two
The performance of FPGA is realized based on final sum‟s and carry individually. Here the main
synthesis report the Device Utilization summary advantage is the output doesnot require any
and Comparison of different adders are discussed multiplexer. Only one block it-self works initially
in this chapter. By observing the results, the on input carry so totally half of the logic
developed carry select adder is having high implementation is automatically reduced.An
performance than the existing modified carry efficient CSLA design is obtained using optimized
select adder. We can clearly observe the logic units. The developed CSLA design involves
improvement in the area,power and delay significantly less area and delay than the present
product for developed carry select adder. BEC-based CSLA. The architecture has been
5.2.1 COMPARISION TABLE FOR EXISTING AND verified on XILINX Spartan - 3E and respective
DEVELOPED 16 BIT ADDER synthesis result shows that the developed
S.
SQRT-CSLA involves nearly 35% less
N PROPOSE
o Logic Available RCA BEC D CS area–delay–product (ADP) and consumes 50% less
Utilizatio energy than the developed CSLA, on average, for
n
different bit-widths like 8, 16 and 32 bit
Used Used Used widthsthan the BEC-based SQRT-CSLA.

No of VII. FUTURE SCOPE

1. slices 28 26 17
Now a day‟s Carry Select Adder (CSLA) used in
3584 many data-processing processors to perform fast
arithmetic functions.The speed of Proposed CSLA
No of
greater than Modified SQRT CSLA, but the area
2. LUTS 46 46 32
and power reduced compared to modified SQRT
7168 CSLA. So,proposed SQRT CSLA can be replaced by
Modified SQRT CSLA,where the area and power
3. No of IOBS 50 50 50
major constraints than speed. In future by using
97 more and more sophisticated fabrication
techniques area can be minimized.
Maximum
4. delay(ns) 19.59 16.42 10.43
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