module DE2_CCD (

//////////////////////// Clock Input ////////////////////////

input CLOCK_27, // 27 MHz

input CLOCK_50, // 50 MHz

input EXT_CLOCK, // External Clock

//////////////////////// Push Button ////////////////////////

input [3:0] KEY, // Pushbutton[3:0]

//////////////////////// DPDT Switch ////////////////////////

input [17:0] SW, // Toggle Switch[17:0]

//////////////////////// 7-SEG Dispaly ////////////////////////

output [6:0] HEX0, // Seven Segment Digit 0

output [6:0] HEX1, // Seven Segment Digit 1

output [6:0] HEX2, // Seven Segment Digit 2

output [6:0] HEX3, // Seven Segment Digit 3

output [6:0] HEX4, // Seven Segment Digit 4

output [6:0] HEX5, // Seven Segment Digit 5

output [6:0] HEX6, // Seven Segment Digit 6

output [6:0] HEX7, // Seven Segment Digit 7

//////////////////////////// LED ////////////////////////////

output [8:0] LEDG, // LED Green[8:0]

output [17:0] LEDR, // LED Red[17:0]

/////////////////////// SDRAM Interface ////////////////////////

inout [15:0] DRAM_DQ, // SDRAM Data bus 16 Bits

output [11:0] DRAM_ADDR, // SDRAM Address bus 12 Bits

output DRAM_LDQM, // SDRAM Low-byte Data Mask

output DRAM_UDQM, // SDRAM High-byte Data Mask

output DRAM_WE_N, // SDRAM Write Enable

output DRAM_CAS_N, // SDRAM Column Address Strobe

output DRAM_RAS_N, // SDRAM Row Address Strobe

output DRAM_CS_N, // SDRAM Chip Select

output DRAM_BA_1, // SDRAM Bank Address 0

output DRAM_CLK, // SDRAM Clock

output DRAM_CKE, // SDRAM Clock Enable

//////////////////////// Flash Interface ////////////////////////

inout [7:0] FL_DQ, // FLASH Data bus 8 Bits

output [21:0] FL_ADDR, // FLASH Address bus 22 Bits

output FL_WE_N, // FLASH Write Enable

output FL_RST_N, // FLASH Reset

output FL_OE_N, // FLASH Output Enable

output FL_CE_N, // FLASH Chip Enable

//////////////////////// SRAM Interface ////////////////////////

inout [15:0] SRAM_DQ, // SRAM Data bus 16 Bits

output [17:0] SRAM_ADDR, // SRAM Address bus 18 Bits

output SRAM_UB_N, // SRAM High-byte Data Mask

output SRAM_LB_N, // SRAM Low-byte Data Mask

output SRAM_WE_N, // SRAM Write Enable

output SRAM_CE_N, // SRAM Chip Enable

output SRAM_OE_N, // SRAM Output Enable

//////////////////////// I2C ////////////////////////////////

inout I2C_SDAT, // I2C Data

output I2C_SCLK, // I2C Clock

//////////////////////// VGA ////////////////////////////

output VGA_CLK, // VGA Clock

output VGA_HS, // VGA H_SYNC

output VGA_VS, // VGA V_SYNC

output VGA_BLANK, // VGA BLANK

output VGA_SYNC, // VGA SYNC

output [9:0] VGA_R, // VGA Red[9:0]

output [9:0] VGA_B, // VGA Blue[9:0]

//////////////////////// GPIO ////////////////////////////////

inout [35:0] GPIO_0, // GPIO Connection 0

inout [35:0] GPIO_1 // GPIO Connection 1

);

// CCD

wire [9:0] CCD_DATA;

wire CCD_SDAT;

wire CCD_SCLK;

wire CCD_FLASH;

wire CCD_FVAL;

wire CCD_LVAL;

wire CCD_PIXCLK;

reg CCD_MCLK; // CCD Master Clock

wire [15:0] Read_DATA1;

wire [15:0] Read_DATA2;

wire VGA_CTRL_CLK;

wire AUD_CTRL_CLK;

wire [9:0] mCCD_DATA;

wire mCCD_DVAL;

wire mCCD_DVAL_d;

wire [10:0] X_Cont;

wire [10:0] Y_Cont;

wire [9:0] X_ADDR;

wire [31:0] Frame_Cont;

wire [9:0] mCCD_R;

wire [9:0] mCCD_G;

wire DLY_RST_0;

wire DLY_RST_1;

wire DLY_RST_2;

wire Read;

reg [9:0] rCCD_DATA;

reg rCCD_LVAL;

reg rCCD_FVAL;

wire [9:0] sCCD_R;

wire [9:0] sCCD_G;

wire [9:0] sCCD_B;

wire sCCD_DVAL;

// sobel

wire [9:0] DISP_R;

wire [9:0] DISP_G;

wire [9:0] DISP_B;

wire [9:0] GrayscaleR;

wire [9:0] GrayscaleG;

wire [9:0] GrayscaleB;

wire [9:0] VGA_out_R;

wire [9:0] VGA_out_G;

wire [9:0] VGA_out_B;

wire [9:0] Sobel_edge;

assign LCD_ON = 1'b1;

assign LCD_BLON = 1'b1;

assign TD_RESET = 1'b1;

assign FL_DQ = 8'hzz;

assign SRAM_DQ = 16'hzzzz;

assign OTG_DATA = 16'hzzzz;

assign LCD_DATA = 8'hzz;

assign SD_DAT = 1'bz;

assign I2C_SDAT = 1'bz;

assign ENET_DATA = 16'hzzzz;

assign AUD_ADCLRCK = 1'bz;

assign AUD_DACLRCK = 1'bz;

assign AUD_BCLK = 1'bz;

// For Sensor 1

assign CCD_DATA[0] = GPIO_1[0];

assign CCD_DATA[1] = GPIO_1[1];

assign CCD_DATA[2] = GPIO_1[5];

assign CCD_DATA[3] = GPIO_1[3];

assign CCD_DATA[4] = GPIO_1[2];

assign CCD_DATA[5] = GPIO_1[4];

assign CCD_DATA[6] = GPIO_1[6];

assign CCD_DATA[7] = GPIO_1[7];

assign CCD_DATA[8] = GPIO_1[8];

assign CCD_DATA[9] = GPIO_1[9];

assign GPIO_1[11] = CCD_MCLK;

assign CCD_FVAL = GPIO_1[13];

assign CCD_LVAL = GPIO_1[12];

assign CCD_PIXCLK = GPIO_1[10];

assign LEDR = SW;

assign LEDG = {5'b10000, ~KEY[3], ~KEY[2], ~KEY[1], ~KEY[0]};

assign VGA_CLK = ~CCD_MCLK;

// To Display

assign DISP_R = SW[0] ? morphologic :

SW[17] ? GrayscaleR :

SW[16] ? Sobel_edge :

SW[15] ? Bin_image :

VGA_out_R

);

assign DISP_G = SW[0] ? morphologic :

SW[17] ? GrayscaleG :

SW[16] ? Sobel_edge :

SW[15] ? Bin_image :

VGA_out_G

);

assign DISP_B = SW[0] ? morphologic :

SW[17] ? GrayscaleB :

SW[16] ? Sobel_edge :

SW[15] ? Bin_image :

VGA_out_B

);

// Judgement of SW[14], [13], [12]

wire [2:0] button3 = {SW[14], SW[13], SW[12]};

always @ (button3) begin

case (button3)

3'b000 : morphologic = fDilation;

3'b001 : morphologic = fErosion;

3'b010 : morphologic = fDilation_sobel;

3'b011 : morphologic = fErosion_sobel;

3'b100 : morphologic = fDilation_gray;

3'b101 : morphologic = fErosion_gray;

3'b110 : morphologic = fOpening_bin;

3'b111 : morphologic = fClosing_bin;

endcase

end

// RGB

assign VGA_out_R = Read_DATA2[9:0];

assign VGA_out_G = {Read_DATA1[14:10],Read_DATA2[14:10]};

assign VGA_out_B = Read_DATA1[9:0];

// Binary

wire [9:0] BIN_THRESHOLD;

assign BIN_THRESHOLD = {3'b0, SW[7], SW[6], SW[5], SW[4], 3'b100};

wire mvalue_Binary;

wire [9:0] Bin_image;

// Gray

assign GrayscaleR = VGA_out_G;

assign GrayscaleG = VGA_out_G;

assign GrayscaleB = VGA_out_G;

CCD_MCLK <= ~CCD_MCLK;

always@(posedge CCD_PIXCLK) begin

rCCD_DATA <= CCD_DATA;

rCCD_LVAL <= CCD_LVAL;

rCCD_FVAL <= CCD_FVAL;

end

VGA_Controller vga0 (

// Host Side

.oRequest(Read),

.iRed(DISP_R),

.iGreen(DISP_G),

.iBlue(DISP_B),

// VGA Side

.oVGA_R(VGA_R),

.oVGA_G(VGA_G),

.oVGA_B(VGA_B),

.oVGA_H_SYNC(VGA_HS),

.oVGA_V_SYNC(VGA_VS),

.oVGA_SYNC(VGA_SYNC),

.oVGA_BLANK(VGA_BLANK),

// Control Signal

.iCLK(VGA_CTRL_CLK),

.iRST_N(DLY_RST_2)

);

Reset_Delay reset0 (

.iCLK(CLOCK_50),
 .iRST(KEY[0]),

.oRST_0(DLY_RST_0),

.oRST_1(DLY_RST_1),

.oRST_2(DLY_RST_2)

);

CCD_Capture capture0 (

.oDATA(mCCD_DATA),

.oDVAL(mCCD_DVAL),

.oX_Cont(X_Cont),

.oY_Cont(Y_Cont),

.oFrame_Cont(Frame_Cont),

.iDATA(rCCD_DATA),

.iFVAL(rCCD_FVAL),

.iLVAL(rCCD_LVAL),

.iSTART(!KEY[3]),

.iEND(!KEY[2]),

.iCLK(CCD_PIXCLK),

.iRST(DLY_RST_1)

);

RAW2RGB rgb0 (

.oRed(mCCD_R),

.oGreen(mCCD_G),

.oBlue(mCCD_B),

.oDVAL(mCCD_DVAL_d),

.iX_Cont(X_Cont),

.iY_Cont(Y_Cont),

.iDATA(mCCD_DATA),

.iDVAL(mCCD_DVAL),

.iCLK(CCD_PIXCLK),
 .iRST(DLY_RST_1)

);

Sdram_Control_4Port sdram0 (

// HOST Side

.REF_CLK(CLOCK_50),

.RESET_N(1'b1),

// FIFO Write Side 1

.WR1_DATA({sCCD_G[9:5], sCCD_B[9:0]}),

.WR1(sCCD_DVAL),

.WR1_ADDR(0),

.WR1_MAX_ADDR(640*512),

.WR1_LENGTH(9'h100),

.WR1_LOAD(!DLY_RST_0),

.WR1_CLK(CCD_PIXCLK),

// FIFO Write Side 2

.WR2_DATA({sCCD_G[4:0], sCCD_R[9:0]}),

.WR2(sCCD_DVAL),

.WR2_ADDR(22'h100000),

.WR2_MAX_ADDR(22'h100000+640*512),

.WR2_LENGTH(9'h100),

.WR2_LOAD(!DLY_RST_0),

.WR2_CLK(CCD_PIXCLK),

// FIFO Read Side 1

.RD1_DATA(Read_DATA1),

.RD1(Read),

.RD1_ADDR(640*16),

.RD1_MAX_ADDR(640*496),

.RD1_LENGTH(9'h100),

.RD1_LOAD(!DLY_RST_0),

.RD1_CLK(VGA_CTRL_CLK),
 // FIFO Read Side 2

.RD2_DATA(Read_DATA2),

.RD2(Read),

.RD2_ADDR(22'h100000+640*16),

.RD2_MAX_ADDR(22'h100000+640*496),

.RD2_LENGTH(9'h100),

.RD2_LOAD(!DLY_RST_0),

.RD2_CLK(VGA_CTRL_CLK),

// SDRAM Side

.SA(DRAM_ADDR),

.BA({DRAM_BA_1,DRAM_BA_0}),

.CS_N(DRAM_CS_N),

.CKE(DRAM_CKE),

.RAS_N(DRAM_RAS_N),

.CAS_N(DRAM_CAS_N),

.WE_N(DRAM_WE_N),

.DQ(DRAM_DQ),

.DQM({DRAM_UDQM,DRAM_LDQM}),

.SDR_CLK(DRAM_CLK)

);

I2C_CCD_Config ccd_config0 (

// Host Side

.iCLK(CLOCK_50),

.iRST_N(KEY[1]),

.iExposure(SW[11:8]),

// I2C Side

.I2C_SCLK(GPIO_1[14]),

.I2C_SDAT(GPIO_1[15])

);
Mirror_Col mirror0 (

// Input Side

.iCCD_R(mCCD_R),

.iCCD_G(mCCD_G),

.iCCD_B(mCCD_B),

.iCCD_DVAL(mCCD_DVAL_d),

.iCCD_PIXCLK(CCD_PIXCLK),

.iRST_N(DLY_RST_1),

// Output Side

.oCCD_R(sCCD_R),

.oCCD_G(sCCD_G),

.oCCD_B(sCCD_B),

.oCCD_DVAL(sCCD_DVAL)

);

// Sobel edge detection

Sobel sobel0 (

.CLOCK(VGA_CTRL_CLK),

.RESET_N(DLY_RST_2),

.input_data(VGA_out_G),

.iDVAL(Read),

.thresh({SW[3:1],2'b10}),

.output_data(Sobel_edge)

);

// binary

bbinary binary0 (

.CLOCK(VGA_CTRL_CLK),

.RESET_N(DLY_RST_2),

.input_data(VGA_out_G),

.iDval(Read),
 .thresh(BIN_THRESHOLD),

.oDval(mvalue_Binary),

.output_data(Bin_image)

);

// dilation from binary

wire mvalue_dilation;

wire [9:0] fDilation;

Ddilation dilation0 (

.CLOCK(VGA_CTRL_CLK),

.RESET_N(DLY_RST_2),

.input_data(Read),

.iDATA(Bin_image),

.oDVAL(mvalue_dilation),

.output_data(fDilation)

);

// dilation from Sobel

wire mvalue_dilation_sobel;

wire [9:0] fDilation_sobel;

Ddilation dilation1 (

.CLOCK(VGA_CTRL_CLK),

.RESET_N(DLY_RST_2),

.input_data(Read),

.iDATA(Sobel_edge),

.oDVAL(mvalue_dilation_sobel),

.output_data(fDilation_sobel)

);

// dilation from gray

wire mvalue_dilation_gray;
wire [9:0] fDilation_gray;

Ddilation dilation2 (

.CLOCK(VGA_CTRL_CLK),

.RESET_N(DLY_RST_2),

.input_data(Read),

.iDATA(VGA_out_G),

.oDVAL(mvalue_dilation_gray),

.output_data(fDilation_gray)

);

// erosion from binary

wire mvalue_erosion;

wire [9:0] fErosion;

Eerosion erosion0 (

.CLOCK(VGA_CTRL_CLK),

.RESET_N(DLY_RST_2),

.input_data(Read),

.iDATA(Bin_image),

.oDVAL(mvalue_erosion),

.output_data(fErosion)

);

// erosion from Sobel

wire mvalue_erosion_sobel;

wire [9:0] fErosion_sobel;

Eerosion erosion1 (

.CLOCK(VGA_CTRL_CLK),

.RESET_N(DLY_RST_2),

.input_data(Read),

.iDATA(Sobel_edge),

.oDVAL(mvalue_erosion_sobel),
 .output_data(fErosion_sobel)

);

// erosion from gray

wire mvalue_erosion_gray;

wire [9:0] fErosion_gray;

Eerosion erosion2 (

.CLOCK(VGA_CTRL_CLK),

.RESET_N(DLY_RST_2),

.input_data(Read),

.iDATA(VGA_out_G),

.oDVAL(mvalue_erosion_gray),

.output_data(fErosion_gray)

);

// Closing from binary

wire mvalue_closing_bin;

wire [9:0] fClosing_bin;

Eerosion erosion3 (

.CLOCK(VGA_CTRL_CLK),

.RESET_N(DLY_RST_2),

.input_data(Read),

.iDATA(fDilation_sobel),

.oDVAL(mvalue_closing_bin),

.output_data(fClosing_bin)

);

// Opening from binary

wire mvalue_opening_bin;

wire [9:0] fOpening_bin;

Ddilation dilation3 (
 .CLOCK(VGA_CTRL_CLK),

.RESET_N(DLY_RST_2),

.input_data(Read),

.iDATA(fErosion_sobel),

.oDVAL(mvalue_opening_bin),

.output_data(fOpening_bin)

);

SEG7_LUT_8 seg0 (

.oSEG0(HEX0),

.oSEG1(HEX1),

.oSEG2(HEX2),

.oSEG3(HEX3),

.oSEG4(HEX4),

.oSEG5(HEX5),

.oSEG6(HEX6),

.oSEG7(HEX7),

.iDIG(Frame_Cont)

);

endmodule