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Biasing method of MOSFET:
Fixed bias Configuration
Figure 2.2.1 Fixed bias circuit
Diagram Electronic Tutorial
• Dc bias of a FET device needs setting of 𝑉𝐺𝑆 to give desired 𝐼𝐷.
• For a JFET, drain current is limited by the saturation current𝐼𝐷𝑆𝑆.
• Since the FET has such a high input impedance that no gate current flows and the dc voltage
of the gate set by a fixed battery voltage.
• Fixed dc bias is obtained using a battery 𝑉𝐺𝐺. This battery ensures that the gate is always
negative with respect to the source and no current flows through the resistor 𝑅𝐺 and gate
terminal i.e. 𝐼𝐺 = 0.
• The battery provides a voltage 𝑉𝐺𝑆 to bias the n-channel JFET, but no resulting current is
drawn from the battery 𝑉𝐺𝐺. The dc voltage drop across 𝑅𝐺 is equal to 𝐼𝐺𝑅𝐺 i.e.0 volt.
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ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY
Figure 2.2.2 Fixed bias circuit
Diagram Electronic Tutorial
Graphical Analysis
A graphical analysis would require a plot of Shockley’s equation as shown in Fig. By choosing
𝑉𝐺𝑆 = 𝑉𝑃/2 will result in a drain current of 𝐼𝐷𝑆𝑆/ 4 when plotting the equation. For the
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ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY
analysis, the three points defined by 𝐼𝐷𝑆𝑆, 𝑉𝑃 and the intersection just described will be
sufficient for plotting the curve.
Figure 2.2.3 Drain Characteristics
Diagram Electronic Tutorial
Self bias Configuration
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Figure 2.2.3 Self Bias Configuration
Diagram Electronic Tutorial
• This is the most common method of biasing a FET.
• This circuit eliminates the requirement of two dc supplies i.e. only drain supply is used and
no gate supply is connected.
• In this circuit, a resistor 𝑅𝑆, known as bias resistor, is connected in the source lag. The dc
component of drain current 𝐼𝐷 flowing through 𝑅𝑆 makes a voltage drop across 𝑅𝑆. The
voltage drop across 𝑅𝑆 reduces the gate-to-source reverse voltage required for FET operation.
The resistor𝑅𝑆, feedback resistor prevents any variation in drain current
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ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY
Figure 2.2.3 Self Bias Configuration output side
Diagram Electronic Tutorial
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ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY
The result is a second point for the straight-line plot as shown in Fig. The straight line as defined by
Eq. is then drawn and the quiescent point obtained at the intersection of the straight-line plot and the
device characteristic curve. The quiescent values of 𝑉𝐺𝑆 𝑎𝑛𝑑 𝐼𝐷can then be determined and used
to find the other quantities of interest.
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ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY
Figure 2.2.3 Drain Characteristics
Diagram Electronic Tutorial
Voltage-divider bias Configuration
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ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY
EC3353 ELECTRONIC DEVICES AND CIRCUITS
