University of KwaZulu-Natal Analogue Electronics 1 (ENEL3TA)
Tutorial 1
1 The differential amplifier circuit of Figure 1 utilizes a resistor connected to the negative power supply
to establish the dc bias tail current IT, instead of using a current source.
+5 V
4,7k 4,7k
vO
Q1 Q2
vB1 vB2
4,3k
5 V
Figure 1
1.1 Find the dc bias conditions in the circuit assuming v B1 v B2 0 V .
1.2 Determine the differential voltage gain A Vd v O (v B1 v B2 ) .
1.3 Determine the common-mode voltage gain AVc and hence the CMRR.
1.4 The 4,3 kΩ tail resistor is now replaced by a simple BJT current mirror sink operating at the same bias
current. Assuming the current mirror BJTs have β = 100 and VA = 100 V, determine the new CMRR.
Hence explain the relative advantage of using the current mirror instead of the resistor.
2 Design a differential amplifier (similar to Figure 3: Class notes, p3) to amplify a differential input
signal of 0,2 V pk and provide a differential output signal of 4 V pk. To ensure adequate linearity, the
signal voltage across each base-emitter junction is to be limited to 5 mV pk. The differential input
resistance is to be at least 80 kΩ. The BJTs available are specified to have β = 200. Determine the
component values required assuming an ideal tail current source.
3 The differential amplifier of Figure 2 uses BJTs with β = 100. Identify and sketch the differential and
common-mode equivalent half circuits. Determine the differential and common-mode input
resistances. Assuming the output is taken single-endedly (as shown), determine the differential and
common-mode voltage gains and the CMRR.
+15 V
RC RC
RL
10k 10k
10k
vO
Q1 RE Q2
vi 200
200k 1mA 1mA 200k
Figure 2
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University of KwaZulu-Natal Analogue Electronics 1 (ENEL3TA)
4 In Figure 3, a BJT differential amplifier input stage (Q1 & Q2) utilizing two 100 Ω emitter resistors
drives a second differential amplifier stage (Q3 & Q4). Stage 1 is biased with IT1 = 1 mA and stage is
biased with IT2 = 2,5 mA. All BJTs have β = 150.
4.1 Determine the signal differential voltage gain and input resistance of stage 1, and the signal current
i
gain from the input of stage 1 to the collectors of stage 2 i.e. A I c3 .
i b1
4.2 State two likely reasons for the addition of the emitter resistors to stage 1.
RC1 RC2
5k 5k
ic 3
ib 1 ic 1 ib 3
Q1 Q2 Q3 Q4
RE1 RE2
100 100
= 150
IT1 IT2
Figure 3
5 The circuit diagram of a simple op-amp is shown in Figure 4.
+15 V
R2 R3
6k 2,3k
R1
29,3k Q5
IR1
Q3 Q4 Q6
Vi d
VO
IC2
R4 R5
Q1 Q2 15,7k 3k
-15 V
Figure 4
5.1 Perform an approximate dc analysis of the circuit to determine the dc currents and voltages
everywhere in the circuit assuming the inputs are grounded, 1 and VBE 0,7 V .
5.2 Assuming the BJTs have β = 100, determine the differential voltage gain and input resistance, and the
output resistance of the op-amp.
5.3 If due to production mismatch BJT Q3 has β = 120, determine the input bias current IB and input offset
current IOS for this op-amp.
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