Verilog HDL (18EC44)

General Information of HDL

1
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HDLs – WHAT-WHY-HOW
§ WHAT is a HDL?

§ HDLs – A class of programming/computer languages used for

formal description of electronic circuits.

§ A Hardware Description Language is one that can describe

circuit’s operation, conceptual design & organization and can
test it by means of simulation.

§ Usually deal with the design of digital logic circuits and

systems .

2
HDLs – WHAT-WHY-HOW
§ WHY were HDLs required?

§ It is impractical to verify large circuits on breadboards or

large chips after manufacturing.

§ Highly important to find potential functional bugs in the

early stages of design.

§ These needs led to a the use of CAD techniques for digital

design.

§ The designers felt need for a flexible language that may help
the design process by giving a complete framework for design.
3
HDLs – WHAT-WHY-HOW
§ WHY were HDLs required? (contd..)

§ Software Programming languages – Sequential in nature. (C,

Pascal, FORTRAN, etc.)

§ Digital logic circuits involve Concurrency of operations.

§ Traditional programming languages lack the capability for

explicitly expressing time.

§ Using s/w programming languages to represent hardware is –

Inconvenient, Time consuming & Costlier.

4
HDLs – WHAT-WHY-HOW
§ HOW are HDLs advantageous?

§ Allows designer to talk about what the hardware should do

without actually designing the hardware itself.

§ Designers can develop an executable functional specification

that documents the exact behavior of all the components and
their interfaces.

§ Designers can make decisions about cost, performance, power,

and area earlier in the design process.

§ Designers can create tools which automatically manipulate

the design for verification, synthesis, and optimization.
5
Evolution of Computer Aided Design
Evolution of Computer Aided Design
Evolution of Computer Aided Design
 Evolution of Computer Aided Design

LSI
✓ Design process became complex
✓ Led to the invention of the CAD tools
✓ CAD – Computer Aided Design
✓ Designer’s used the circuit and logic
simulation tools to verify the
functionality.
 Evolution of Computer Aided Design

VLSI
✓ With 10000 of transistors, impossible to verify on
a breadboard.
✓ Computer aided techniques became critical for
verification and design of VLSI circuits.
✓ Computer aided techniques which do automatic
route and placement is popular
✓ Logic simulators to verify the functionality has
come into existence.
 Emergence of HDL’s

Earlier programming languages such as Fortran, C and pascal were used

to describe the behavior of the digital circuits.
HDL –Hardware Description Language

HDL came into existence to which allows the concurrency modelling of

the circuits
 Verilog HDL
Typical Design Flow
1. Specifications describe abstractly
the functionality, interface, and
overall architecture of the digital
circuit to be designed. A

Architects do not need to think

about how they will implement this
circuit

2. A behavioral description is
then created to analyze the
design in terms of functionality,
performance, and compliance to
standards, and other high-level
issues.
Behavioral descriptions are often
written with HDLs.
12
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 Verilog HDL

Typical Design Flow

• EDA tools have emerged to simulate behavioral descriptions of circuits
• behavioral description is converted to an RTL description in an HDL
• The designer has to describe the data flow that will implement the
desired digital circuit
• Logic synthesis tools convert the RTL description to a gate-level net
list. Logic synthesis tools ensure that the gate-level net list meets
timing, area, and power specifications.
• A gate-level net list is a description of the circuit in terms of gates and
connections between them. The gate-level netlist is input to an
Automatic Place and Route tool, which creates a layout.
• The layout is verified and then fabricated on a chip

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 Verilog HDL

Hardware Design Flow

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Verilog HDL

Basic Concepts

✓ Lexical Conventions –conventions for operators,

comments, whitespace, strings and identifiers

✓ Data types – value set, nets, registers, vectors, numbers,

simulation time, arrays, parameters and strings

✓ System Tasks - Displaying and monitoring information

✓ Compiler Directives – macros and include files

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Verilog HDL

Lexical Conventions
AVerilog program is a string of tokens

✓ Whitespace
✓ Comments
✓ Delimiters
✓ Numbers
✓ Strings
✓ Identifiers
✓ Keywords

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Verilog HDL

Lexical Conventions
• Whitespace • Comments
• Blank space (\b) • Used for readability and
documentation
• Tab (\t)
• Just like in C:
• Newline (\n)
1 . / / single line comment
• Whitespace is ignored in Verilog 2. /* multi line
except comment
*/
• In strings
3. /* Nested
• When separating tokens comments
/* like this */ may not be
acceptable (depends on
Verilog compiler) */

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Verilog HDL

Lexical Convention cont’d

• Operators
• Unary
a = ~b;
• Binary
a = b && c;
• Ternary
a = b ? c : d; // the only
ternary operator

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Verilog HDL

Lexical Convention cont’d

• Number Specification
§ Sized numbers
§ Unsized numbers
§ Unknown and high-impedance values
§ Negative numbers

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Verilog HDL

Lexical Convention cont’d

• Sized numbers • Unsized numbers
• General syntax:
• Default base is decimal
• <size>’<base><number>
• Default size is at least 32 (depends on
<size> number of bits (in decimal)
Verilog compiler)
<number> is the number in radix
Examples:
<base>
• <base> :
• 23232
• d or D for decimal (radix 10)
• b or B for binary (radix 2)
• ’habc
• o or O for octal (radix 8) • ’o234
• h or H for hexadecimal (radix 16)
• Examples:
• 4’b1111
• 12’habc
• 16’d255

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Verilog HDL

Lexical Convention cont’d

Bit length in decimal. This is an optional value

<number of bits> & if not specified, default is host machine word
size. (usually 32 bits)

<base> ‘b, ‘B, ‘d, ‘D, ‘o, ‘O, ‘h, ‘H. Default is ‘decimal’

<number> 0-9, a -f, A -F, X, Z, ?, _

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Verilog HDL

Lexical Convention cont’d

• X or Zvalues
• Unknown value: lowercase x
4 bits in hex, 3 bits in octal, 1-bit in binary
• High-impedance value: lowercase z
4 bits in hex, 3 bits in octal, 1-bit in binary
• Examples:
12’h13x
6’hx
32’bz
• Extending the most-significant part
• Applied when <size> is bigger than the specified value
• Filled with x if the specified MSB is x
• Filled with z if the specified MSB is z
• Zero-extended otherwise
• Examples:
• 6’hx
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Verilog HDL

Lexical Convention cont’d

• Negative numbers
Put the sign before the <size>
Format: -<size><base><number>
Represented by 2’s complement internally.
• Two’s complement is used to store the value
• Examples:
-6’d3
4’d-2 // illegal
reg [5:0] Num;
Reg [31:0] data;
..
Num = -6; // Negative number
Num = -8’d4; // 8 bit –ve number
Num = ‘d-12; // Illegal !!
data = 32’h_1234_5678; // _ for readability

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Verilog HDL

Lexical Convention cont’d

• Underscore character and question marks
Use ‘_’to improve readability
12’b1111_0000_1010
Not allowed as the first character
• ‘?’ is the same as ‘z’(only regarding numbers)
• 4’b10?? // the same as 4’b10zz
reg [5:0] Num;
Reg [31:0] data;
..
Num = 6’b_100x; // Num = 6’b00100x
data = 32’bx; // 32 bit no with all x bits
Num = ‘bz01; // Num = 6’bzzzz01
Num = ‘b11??1; // Num = 6’b011zz1
data = 32‘h_x5f3_2693; // data = 32’hX5f32693
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Verilog HDL

Numbers example
module Verilog_number;
reg [7:0] Num;
wire status;
…
Num = 16; // 8’b0001_0000
Num = -8’d4; // two’s complement of 4
Num = ‘bx; // 8’bxxxx_xxxx
Num = ‘b0x; // 8’b0000_000x
Num = ‘b10x; // 8’b0000_010x
if (status == 1) // status == 32’h0001
Num = 8’b1010_0101;
if (status == 1’b1)
…
endmodule

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Verilog HDL

Lexical Convention cont’d

• Strings
• As in C, use double-quotes
• Examples:
“Hello world!”
“a / b”
“text\tcolumn1\bcolumn2\n”

• Identifiers and keywords

• Identifiers: alphanumeric characters, ‘_’, and ‘$’
Should start with an alphabetic character or ‘_’
Only system tasks can start with ‘$’
• Keywords: identifiers reserved by Verilog
• Examples:
• reg value;
• input clk;
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Verilog HDL

Lexical Convention cont’d

• Escaped identifiers
• Start with ‘\’
• End with whitespace (space, tab, newline)
• Can have any printable character between start and end
• The ‘\’and whitespace are not part of the identifier
• Examples:
\a+b-c //a+b-c is the identifier
\**my_name** //**my_name** is the identifier

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Verilog HDL

DATATYPES

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Verilog HDL

Datatypes
✓ Value set and strengths
✓ Nets and Registers
✓ Vectors
✓ Integer, Real, and Time Register Data Types
✓ Arrays
✓ Memories
✓ Parameters
✓ Strings

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Verilog HDL

Value Set
• Verilog concepts to model hardware circuits
• Value level
• Value strength
• Used to accurately model
• Signal contention
• MOS devices
• Dynamic MOS
• Other low-level details

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Verilog HDL

Value Set
Value HW Condition Strength level Type
level
0 Logic zero, false supply Driving
strong Driving
1 Logic one, true
pull Driving
x Unknown
large Storage
z High imp., floating
weak Driving
medium Storage
small Storage
highz High Impedance

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Verilog HDL

Nets
§ Represent the connections between hardware elements

§ They are always driven by some source

§ Default value for any net type variable is ‘z’

§ Usually, declared by the keyword wire

§ Different types: wire, wand, wor, tri, triand, trior,

§ trireg, etc.

§ wire is the most common of all.

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Verilog HDL

Nets
• Used to represent connections between HW elements
• Values continuously driven on nets
• Keyword: wire
Default: One-bit values
unless declared as vectors

• Default value: z
For trireg, default is x
• Examples
• wire a;
• wire b, c;
• wire d=1’b0;

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Verilog HDL

Registers
§ Correspond to variables in the C language.
§ Register data types always retain their value until another
§ value is placed on them.

§ DO NOT confuse with hardware registers built with flip-

flops
§ A reg type variable is the one that can hold a value.
§ Unlike nets, registers do not need any drivers
§ In synthesis, the compiler will generate latches or flip-
flops for them. However, if it can be sure their output
does not need to be stored it will synthesize them into
wires

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Verilog HDL

Registers
• Registers represent data storage elements
• Retain value until next assignment
• NOTE: this is not a hardware register or flipflop
• Keyword: reg
Default value: x
• Example:
reg reset;
initial
begin
reset = 1’b1;
#100 reset=1’b0;
end

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Verilog HDL

Vectors
• Net and register data types can be declared as vectors
(multiple bit widths)
• Vectors are multi bit values
Syntax:
• wire/reg [msb_index : lsb_index] data_id;

• Examplewire a;
wire [7:0] bus;
wire [31:0] busA, busB, busC;
reg clock;
reg [0:40] virtual_addr;

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Verilog HDL

Vectors cont’d
• Consider
wire [7:0] bus;
wire [31:0] busA, busB, busC; reg
[0:40] virtual_addr;
• Access to bits or parts of a vector is possible:
busA[7]
bus[2:0] // three least-significant bits of bus
// bus[0:2] is illegal.
virtual_addr[0:1] /* two most-significant bits
* of virtual_addr*/

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Verilog HDL

Vectors cont’d
Variable Vector Part Select
[<starting_bit>+: width>
part-select increments from starting bit
[<starting_bit>-: width>
part-select decrements from starting bit
Examples:
reg [255:0] data1;
reg [0:255] data2;
reg [0:7] byte;
byte= data1[31-:8];
//starting bit is 31 width=8 =>data[31:24]
byte= data1[24+:8];
//starting bit is 24 width=8 =>data[31:24]
byte= data2[31-:8];
//starting bit is 31 width=8 =>data[24:31]
byte= data2[24+:8];
//starting bit is 24 width=8 =>data[24:31]

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Verilog HDL

Integer, Real, and Time Register Data Types

• Integer
Keyword: integer
Very similar to a vector of reg
• integer variables are signed numbers
• reg vectors are unsigned numbers
• Bit width: implementation-dependent (at least 32-bits)
• Designer can also specify a width:
integer [7:0] tmp;
• Examples:
integer counter;
initial
counter = -1;
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Verilog HDL

Integer, Real, and Time Register Data Types

• Real
Keyword: real
Values:
• Default value: 0
• Decimal notation: 12.24
• Scientific notation: 3e6 (=3x106)
• Cannot have range declaration
• Example:
real delta;
initial
begin real delta;
initial
begin
delta=4e10;
delta=2.13;
end integer i;
initial
i = delta; // i gets the value 2 (rounded value of 2.13)

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Verilog HDL

Integer, Real, and Time Register Data Types

• Time
• Used to store values of simulation time
Keyword: time
• Bit width: implementation-dependent (at least 64)
• $time system function gives current simulation time
• Example:
time save_sim_time;
initial
save_sim_time = $time;

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Verilog HDL

Arrays
• Only one-dimensional arrayssupported
Allowed for reg, integer, time
Not allowed for real data type
• Syntax:
<data_type> <var_name>[start_idx : end_idx];
• Examples:
integer count[0:7];
reg bool[31:0];
time chk_point[1:100]; reg [4:0]
port_id[0:7];
integer matrix[4:0][4:0]; // illegal

count[5] chk_point[100]
port_id[3]
• Note the difference between vectors and arrays

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Verilog HDL

Memories
• RAM, ROM, and register-files used many times in digital systems
• Memory = array of registers in Verilog
• Word = an element of the array
• Can be one or more bits
• Examples:
reg membit[0:1023];
reg [7:0] membyte[0:1023];
membyte[511]
• Note the difference (as in arrays):
reg membit[0:127];
reg [0:127] register

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Verilog HDL

Parameters
• Similar to const in C
• But can be overridden for each module at compile-time
• Syntax:
parameter <const_id>=<value>;

• Gives flexibility
• Allows to customize the module
• Example:
parameter port_id=5;
parameter cache_line_width=256; parameter
bus_width=8;
wire [bus_width-1:0] bus;

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Verilog HDL

Strings
• Strings are stored in reg variables.
• 8-bits required per character
• The string is stored from the least-significant part to the most-
significant part of the reg variable
• Example:
reg [8*18:1]
string_value;
initial
string_value = “Hello World!”;

• Escaped characters
• \n: newline \”: “
• \t: tab \\: \
• %%: % \ooo: character number in octal

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Verilog HDL

Module and Ports

✓ Modules

✓ Ports

✓ Hierarchical Names

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Verilog HDL
Modules
❑ A module is the basic building block in Verilog.

❑ Elements are grouped into modules to provide the common functionality that is
used at many places in the design.

❑ A module provides the necessary functionality to the higher-level block through its
port interface (inputs and outputs).

❑ In Verilog a module is declared by the keyword module.

❑ A corresponding keyword endmodule must appear at the end of the module

definition.

❑ Modules CANNOT be nested.

❑ Rather, one module can instantiate another module

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Verilog HDL

Modules
❑ Module instantiation is like creating actual objects (Instances) from the common
template (module definition).

❑ Each instance of module has all the properties of that module.

❑
❑ Module instantiations are used for connecting different parts of the designs, and
connecting test bench to the design.
❑ .

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Verilog HDL

Structure of module

module <mod name> (<port list>);

<declarations>; // input, output, inout

// wire, register, etc.

<statements>; // initial, begin, end, always

// dataflow statements

endmodule

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 Verilog HDL

• The <module name> is an identifier that uniquely

names the module.

• The <port list> is a list of input, inout and output

ports which are used to connect to other modules

• The <declararions>registers, memories and wires

• The <statements> may be initial constructs, always

constructs, continuous assignments or instances
of modules

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Verilog HDL

Structure of modules
module module_name (port_list);
Declarations:
input, output, wire, parameter…..

System Modeling:
describe the system in gate-level, data-flow, or
behavioral style…

endmodule

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Verilog HDL

Program
module not_gate(in, out); // module name+ports
// comments: declaring port type
input in;
output out;

// Defining circuit functionality

assign out = ~in;

endmodule

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Verilog HDL

Program
// Compute the logical AND and OR of inputs A and B.

AND_OR
A
andOut

TheAndGate

orOut
B

TheOrGate

module AND_OR(Y1, Y2, A, B);

output Y1, Y2;
input A, B;
and A1 (Y1, A, B);
or o1 (Y2, A, B);
endmodule

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Verilog HDL

Program

module D_FF(q,d,clk,reset);
output q; //port declaration
input d,clk,reset; // data type declaration reg q;
always @ (posedge reset or negedge clk)
if (reset)
q=1'b0;
else
q=d; endmodule

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Verilog HDL

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Verilog HDL

Ports
• Ports provide interface by which a module can
communicate with its environment.

Eg: input/ output pins of an IC chip are its ports.

•
The environment can interact with the module only
through its ports.

• Ports are also referred as terminals

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Verilog HDL

Ports

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Verilog HDL

Example: 4-bit Adder

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Verilog HDL

Port Declaration

Verilog keyword Types of port

input input port
output output port
inout bidirectional port

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Verilog HDL

Port assignments
Modules contain functional descriptions and have input,
output, and inout (bidirectional ports) for interfaces
The following are true of module interfaces:
§ An input or inout port is a wire type within its module
§ An output port must be a wire if it is generated by a
sub module
§ An output port must be a wire if it is generated
declaratively.
An output port ust be
An output port must be
§ reg if it is assigned to procedurally.
§ A wire if it is assigned through continuous assignment
§ Bidirectional ports cannot be assigned to procedurally

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Verilog HDL

Example :Full adder

module fulladd4 (sum, cout, a, b, cin);
output [3:0] sum; // wire by default
output cout; //wire by default
input [3:0] a, b; // wire by default
input cin; // wire by default
//end port
<module internals>
endmodule

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Verilog HDL

Example :D -Flipflop
module DFF (q, d, clk, reset)
output q;
reg q;
input d, clk, reset;
.
.
.
endmodule

Note: ports of type input and inout cannot be declared as reg.

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Verilog HDL

SR latch
module SR_latch (Q, Qbar, Sbar,
Rbar);
output Q, Qbar;
input Sbar, Rbar;
// instantiate lower -level module
nand n1(Q, Sbar, Qbar);
nand n2(Qbar, Rbar, Q);
endmodule

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Verilog HDL

Test Bench for SR Latch

// stimulus module
module TOP;
wire q, qbar;
reg set, reset;
// feed inverted set & reset
SR_latch m1 (q, qbar, ~set, ~reset);
// behavioral block
initial
begin
$monitor ($time, “set=%b, reset=%b, q=%b\n”, set, reset, q);
set=0; reset=0;
#5 reset=1;
#5 reset=0;
#5 set=1;
end
endmodule Girija S ECE Dr.AIT
Verilog HDL

Port Connection Rules

• Port consists of two units. One unit internal to module and another
external to module.
• The internal and external units are connected.
• There are rules governing port declarations when modules are
instantiated within other modules.

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Verilog HDL

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Verilog HDL

Port Connection Rules

Input: Internally input must be net. Externally it can be
connected to reg/net.
Output: Internally it can be reg/net and externally should be
connected to net.
Inout: Internally it can be net and externally connected to net.
Width matching: It is legal to connect ports of different sizes
while making inter module connection but leads to a warning.
Unconnected Port:certain output ports might be for
debugging and might not be connected to external signals.
Eg: fulladd4 fa0 (sum, ,a, b, Cin); // Cout unconnected

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Verilog HDL

Example for illegal port connection

module TOP;
reg [3:0]A,B
reg Cin;
reg[3:0]Sum; //sum is connected to the reg type
wire Cout;
//Instantiate fulladder4,call it fa0 fulladder4
fa0(Sum,Cout,A,B,Cin);

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Verilog HDL

//Illegal because output port sum is connected to a reg variable sum

in module TOP
.
.
<stimulus>
.
.
.
endmodule
//This problem is rectified if variable Sum is declared as net (wire).

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Verilog HDL

Connecting Ports To External Signals:

There are two methods of making connections between signals
specified in the module instantiation & the ports in a module
definition. These two methods cannot be mixed.

Connecting by ordered list- The signals to be connected must

appear in the module instantiation in the same order as the ports
in the port list in module definition.

Connecting ports by name- capability to connect external

signals to ports by port names, rather than by position.
Used for large designs when the number of ports are more and
remember their order is difficult.

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Verilog HDL

Connecting Ports To External Signals:

Connections by Ordered List

<module_name> < instance_name> [instance_array_range]
( signal, signal , ... );

Connections by Named List

<module_name> < instance_name> [instance_array_range]
( .port_name(signal), .port_name(signal), ... );

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Verilog HDL

Connecting by ordered list

module fulladdre4(SUM,COUT,A,B,CIN);
output [3:0] SUM;
module TOP;
output COUT;
reg[3:0]A,B;
input [3:0] A,B;
reg Cin;
input CIN;
. wire [3:0]Sum;
. wire Cout;
. .
<module intervals> fulladdre4 f1(Sum, Cout,A,B,Cin);
. .
<stimulus>
. .
endmodule .
endmodule

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Verilog HDL

Connecting ports by name

//instantiate module fa_byname & connect signals to ports by
name.

fulladder4 fa_byname(.Cout (COUT), .Sum(SUM), .b(B),

.Cin(CIN), .a(A));

Advantage is that as long as port name is not changed, the order of

ports in the port list of a module can be rearranged without
changing the port connections in module instantiations.

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 Verilog HDL

Dataflow Modeling

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 Verilog HDL

Dataflow modeling
► Gate level modeling works well for small
circuits

► As gate densities on chip increasing rapidly

dataflow modeling has become very important

► Dataflow: In terms of the data flow between

registers and how a designing processes data
rather than instantiation of individual gates

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 Verilog HDL

Dataflow modeling
In data flow modeling a circuit is designed in terms of
the data flow between registers

The designers need to have prerequisite knowledge

of logic design to design in dataflow style

Also to design a huge circuit at GATE level consumes

more time and is error prone.

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 Verilog HDL

Continuous Assignments
Syntax:
continuous_assign ::= assign [ drive_strength ] [ delay ]
list_of_net_assignments ;

drive_strength (strong, supply etc), delay (#5) are

optional

assign net_assignment = list_of_net_assignments /net_value

/expression;

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 Verilog HDL

Characteristics of continuous assignment

1. The left hand side of an assignment must always be a scalar or
vector net or a concatenation of scalar and vector nets. It cannot
be a scalar or vector register.
2. Continuous assignments are always active. The assignment
expression is evaluated as soon as one of the right-hand-side
operands changes and the value is assigned to the left-hand-side
net.
3. The operands on the right-hand side can be registers or nets or
function calls. Registers or nets can be scalars or vectors.
4. Delay values can be specified for assignments in terms of time
units. Delay values are used to control the time when a net is
assigned the evaluated value. This feature is similar to specifying
delays for gates. It is very useful in modeling timing behavior in
real circuits.
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 Verilog HDL

Characteristics
► Left hand side must always be a scalar, vector, net or
a concatenation of scalar and vector nets
► It can not be scalar or vector register
► Always active
► Evaluated as soon as a right hand side value
changes
► RHS canbe registers, nets, or function calls
► Delay is used to decide when to assign the
evaluated value to LHS

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 Verilog HDL

Continuous Statement
► Most basic statement in dataflow modeling
► Drives a value onto a net
► Nets: connections between hardware elements
§ Declared with wire
§ Default value z
§ Get output of drivers (no value = z)
§ Class net
► Wire, wand, wor, tri, triand, trior, trireg
§ Continuous assignment replaces gates

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 Verilog HDL

Continuous Statement
Examples :
//Continuous assign. out is a net. i1 and i2 are nets.
assign out = i1 & i2;

//Continuous assign for vector nets. addr is a 16-bit net

//addr1 and addr2 are 16-bit vector registers.
assign addr[15:0] = addr1_bits[15:0] ^ addr2_bits[15:0];

//Concatenation. Left-hand side is a concatenation of a scalar

net and a vector net.

assign {c_out, sum[3:0]} = a[3:0] + b[3:0] + c_in;

sign {c_out, sum[3:0]} = a[3:0] + b[3:0] + c_in;
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 Verilog HDL

Implicit Continuous Assignment

Instead of declaring a net and then writing a continuous
assignment on the net, Verilog provides a shortcut by which
a continuous assignment can be placed on a net when it is
declared.

//Regular continuous assignment.

wire out;
assign out = in1 & in2;

//Same effect is achieved by an implicit continuous

//assignment.
wire out = in1 & in2;

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 Verilog HDL

Implicit Net Declaration

A signal name defined at the left is considered as net. If
the net is connected to a module port the width of the
inferred net is equal to the width of the module port.

//Regular continuous assignment

wire in1,in2;
assign out=in1 &in2;

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 Verilog HDL

Delays
Delay values control the time between the change in a
right-hand-side operand and when the value is assigned to
the LHS.
There are 3 ways of specifying delays in continuous
assignment-
1. regular assignment delay,
2. implicit continuous assignment delay and
3. net declaration delay.

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 Verilog HDL

Regular Assignment Delay

The first method is to assign delay for continuous assignment
statement.
The delay value is specified after the keyword assign.

assign #10 out=in1 &in2; //Delay in a continuous assign

The result of expression in1 & in2 is assigned to out after 10

time units. This is called inertial delay.
An input pulse that is shorter than the delay of the
assignment statement does not propagate to the output.

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 Verilog HDL

Regular Assignment Delay

Regular assignment delay
assign #10 out=in1 &in2;

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 Verilog HDL

Regular Assignment Delay

In the waveform shown

In1 = in2= 1 at t=20, out=1 at t=30 (10 time units later).
In1= 0 at t=60, out=0 at t=70.
In1=1 at t=80, but goes low(0) before 10 time units .
When a computation has to be done after 10 units at t=80 , in1=0 so out=0.
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 Verilog HDL

Implicit Continuous Assignment Delay

Assignment and delay are specified simultaneously.

Regular assignment statement:

wire out ;
assign #10 out=in1 & in2;

Implicit Continuous Assignment delay

wire #10 out= in1 & in2;

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 Verilog HDL

Net Declaration Delay

A net can be specified delay when it is declared without
putting a continuous assignment on the net.

wire # 10 out1;
assign out1= in1 & in2;
// here out will be delayed by 10

OR
wire out;
assign #10 out = in1 & in2;

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 Verilog HDL
Expressions, Operators and Operands
► Registers : data storage
► Nets : connection between hardware elements
► Vectors : e.g. wire [7:0] bus;
reg [0:4] data_reg;
► Time : e.g. time save_sim_time;
save_sim_time = $time;
► Arrays : reg, integer, time
e.g. integer count [0:7];
reg bool [31:0]
reg [4:0] port_id [0:7];
e.g. bool[5] 5th bit of count
port_id[3] 3rd element of port_id
► Memories : array of registers
e.g. Reg [7:0] membyte [0:1023]
//1K 8-bit words

► Parameter port_id = 5
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 Verilog HDL

Expressions, Operators and Operands

► Operands: Nets, Registers, Vectors, Integer, Real

and Time register data types

► Value set: 0, 1, x, z

► Operator Types – Unary, binary and Ternary

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 Verilog HDL
Operator Types
► Arithmetic
► Logical
► Relational
► Equality
► Bitwise
► reduction
► Shift
► Concatenation
► Replication
► conditional

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 Verilog HDL
Operator Types

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 Verilog HDL
Unary Operators
The + ,&, - operators can be used as unary operators. They work on
single operand. Unary operators have higher precedence than the binary
operator
-4 // Negative 4
+5 //positive 5

Negative numbers are represented as 2’s complement internally in

Verilog

Preferably use –ve numbers only for integers & real data

-10/5 //evalutes to -2 (0110 & 5 are integers)

2′ s comp of 10 232 −10
-’d10/5 // = = // 32 is default machine word width
5 5

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 Verilog HDL

Arithmetic Operators

► Binary: * , / , + , - , %
§ Result is “x” if any of the two operands contains an x

► Unary operators:
+ (positive) or – (negative) sign
§ Higher precedence

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 Verilog HDL

Arithmetic Operators
Operator Operator Operation No of
type symbol performe operands
d
* Multiply Two
/ Divide Two
Arithmetic + Add Two
- Subtract Two
% Modulus Two
** Power(exp Two
onent)

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 Verilog HDL

Arithmetic Operators
A= 4’b0011 B= 4’b0100 //A&B are registers
D= 6 E= 4 F= 2 // D&E are integers
A*B = //mul A&B, o/p 4’b1100
D/E // Div D by E, o/p 1
A+B //Add A&B, o/p 4’b0111
B-A //Subtract A from B, o/p 4’b0001
F=E**F //F= 𝐸 F = 42 =16

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 Verilog HDL

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 Verilog HDL

Arithmetic Operators
If any operand has a value x, then the result of the
entire expression is x
i1= 4’b101x i2=4’b1011
i1+i2 = 4’bx
Modulus operator produces the remainder from division
of two numbers
13 % 3 //13/3 R=1
-7 % 2 //-7/2 R=-1
7 % -2 //7/-2 R=+1

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 Verilog HDL

Logical Operators

► Boolean Logical operator

► Bitwise Logical Operator
► Reduction Logical Operator

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 Verilog HDL

Boolean Logical Operators

► Binary: &&, ||
► Unary: !
► Evaluates to a 1-bit (0, 1 or x)
§ Operand = 0 logical 0
§ Operand != 0 logical 1
§ Operand with x’s or z’s x se)

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 Verilog HDL

Boolean Logical Operators

• Logical operators always evaluate to a 1-bit value, 0
(false), 1(true) or x (ambiguous )

• An operand can be zero (false condition) & one (true

condition) if any operand is x or z, it is equivalent to
x(ambiguous condition)

• Logical operator take variables or expression as

operands

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 Verilog HDL

Boolean Logical Operators

Operator symbol Operation No of

type performed operands

! Logical one
Logical negation

&& Logical and Two

|| Logical or Two

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 Verilog HDL

Boolean Logical Operators

A =3, B= 0
A && B //o/p is 0
A || B //o/p is 1
!A //o/p is 0, not(logic 1)
!B //o/p is 1, not(logic 0)

//unknowns
A= 2‘b0X; B= 2’b10;
A && B //o/p is 2’bX(evaluates to X)

// expression
(a==2) && (b==3)

//if both a==2 & b==3 then true else false

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 Verilog HDL

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 Verilog HDL
Bitwise Logical Operators
NOT ~
AND &
OR !
XOR ^
XNOR (^~, ~^)

✓ These operators perform bitwise operations. If one

operand is shorter than the other
✓ it will be extended with zeros to match the length of the
longer operand.
✓ Z is treated as an x

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 Verilog HDL

Bitwise Logical Operators

// X=4’b1010, Y=4’b1101, Z=4’b10x1
~X //o/p is 4’b0101
X&Y //o/p is 4’b1000
X|Y //o/p is 4’b1111
X^Y //o/p is 4’b0111
~(X^Y) //4’b1000
X&Z //4’b10x0
Note:
Boolean Logical operators (&&, ||) yield ‘0’ or ‘1’.
Bitwise operators (&, |, ^) yield a bit by bit value.

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 Verilog HDL

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 Verilog HDL

Reduction Logical Operators

► & , ~& , | , ~| , ^ , ~^

► Take one operand

► 1-bit result

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 Verilog HDL

Reduction Logical Operators

Performs a bitwise operation on a single vector operand and
yield a 1-bit result.

// x = 4’b1010
&x // 1 & 0 & 1 & 0 => 1’b0
|x // 1 | 0 | 1 | 0 => 1’b1
^x // 1^ 0 ^ 1 ^ 0 => 1’b0
// used for a even or odd parity generation. Similarly
~& reduction nand,
~^ reduction xnor,
~| reduction nor

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 Verilog HDL

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 Verilog HDL

Relational Operators
Relational operators are
• greaterthan (>)
• lessthan (<)
• greaterthan or equal to (>=)
• lessthan or equal to (<=).

When relational operators are used in an expression, the

expression returns a logic value of 1 if the expression is
true & 0 if the expression is false.
If there are any unknown or z bits in the operands, the
expression takes a value X.

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 Verilog HDL

Relational Operators

Operator type symbol Operation performed No of

operands
> Greaterthan Two

< Lesserthan Two

Relational

>= Greaterthan or equal to Two

<= Lesserthan or equal to Two

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 Verilog HDL

Relational Operators

// A= 4, B= 3
//X= 4’b1010, Y=4’b1101, z=4’b1xxx

A <= B //evaluate to ‘0’.

A>B //evaluate to ‘1’.
Y >= X //evaluate to ‘1’.
Y<Z //evaluate to ’X’.

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 Verilog HDL

Equality Operators

== Equality Two 0,1,x

!= Inequality Two 0,1,x

Equality
=== Case Two 0,1
equality
!== Case Two 0,1
inequality

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 Verilog HDL

Equality Operators

When used in expression equality operator returns logic

value 1 if true, 0 if false.
These operators compare the two operands bit by bit, with
zero filling if the operands are unequal length.
►== , != 0,1,x
§ Return x if any of the two operands include x’s or z’s
►=== , !== 0,1
§ Can compare x and z values

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 Verilog HDL

Equality Operators
Case equality: unlike the ordinary ‘==’ both operands are compared bit
by bit including x & z. the result is ‘1’ if the operands match exactly,&
result is ‘0’ if the operands do not match exactly.
The o/p of case equality & case inequality is never ‘X’.
//A=4, B=3, X=4’b1010, Y=4’b1011
//Z= 4’b1xxz,M=4’b1xxz, N=4’b1xxx
A == B //o/p is ‘0’.
A != B //o/p is ‘1’
X == Z //o/p is ‘X’
Z ===M //o/p is ‘1’
Z===N //o/p is ‘0’
M! == N //o/p is ‘1’
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 Verilog HDL

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 Verilog HDL

Shift Operators
► >> shift right

► << shift left

► Digits are filled with 0’s

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 Verilog HDL

Shift Operators
Operator Operato Operation No of
type r symbol performed operands

Shift >> Right shift (fill Two

with 0)
<< Left shift (fill Two
with 0)
>>> Arithmetic right Two
shift Keep
<<< Arithmetic left Two
shift

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 Verilog HDL

Shift Operators
Regular shift operators shift a vector operands to the
right or the left by specified number of bits the operands
are the vector and the number of bits to shift.
When bits are shifted the vacant bit positions are filled
with zeros

// x = 4’b1100
Y = x >> 1 ; // y = 4’b0110
Y = x << 1 ; // y = 4’b1000
Y = x << 2 ; // y = 4’b0000

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 Verilog HDL
Shift Operators
// Arithmetic shift right or left
The >>> operator shifts to the right by the number of bit positions
given by the right operand. The vacated bit positions are filled with
zeros if the result type is unsigned. If the result type is signed, the
vacated bit positions are filled with the value of the most-significant
bit of the left operand.
The <<< operator shifts the left operand to the left by the number
of bit positions given by the right operand. The vacated bit positions
are filled with zeros.
Example

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 Verilog HDL

Concatenation Operators

► {{…}

► Operands must be sized

► {op1, op2, op3, …. opN)}

§ Where opi : scalar nets or registers, vector nets or
registers, bit_select, part_select, or sized constants

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 Verilog HDL

Concatenation Operator
• It provides a mechanism to concatenate multiple
operands must be sized.
• Unsigned operands not allowed.
• Operands enclosed in {} and separated by ,

// a = 2’b01 b=2’b11 c=2’b10 d=3’b110

Y = {b,c} // 5’b1110
Y = {a,b,c,d,3’b001} //y=011110110001
Y = {a,b[1],c[0],d[2]} //y=01101

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 Verilog HDL

Replication Operator
The operator is {{}}
Repetitive concatenation of the same number can be
expressed by using a replication constant.
A replication constant tells number of time repetition is
to be done.
A=1’b1 ; b=2’b00 ; c=2’b11
Y= {4{a}} //y=4’b1111
Y= {4{a},2{b}} // y= 11110000

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 Verilog HDL

Conditional Operators

► <Condition_expr> ? True_expr : Flase_expr;

Nested conditional operator

§ assign out = (a==3) ? (control ? x : y) : (control ? m : n);

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 Verilog HDL

Conditional Operator
Conditions expiration? true expression : false expression;
► Used in data flow to model conditional
statements
► Example
§ assign addr_bus = drive_enable ? Addr_out : 32’bz;
§ assign out = control ? in1 : in0;

//xor
y=(a != b)? 1:0;

assign y = control ? in1 : in2; 2:1

MUX

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 Verilog HDL

Operator Precedence
Operators Operator symbol Precedence
Unary +, - ,! , ~ highest
Mul,div,mod *,/ , %
Add,sub,shift +, -, << , >>
Relational < ,<= , > ,>=
Equality ==, !=, === ,!==
Reduction &, ~&, ^, ~^, |, ~|

Logical && , ||
Conditional ?! lowest
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 Verilog HDL

Operator Precedence

A= 110010, B=111101 , C=011000 , D=111011

E=(A & (~B) |C | 2 & D)
=(110010 & (~111101)|011000|2 &111011)

A, B and C are unsigned variables

=(110010 & 000010 | 011000 | 2 &111011)
=(00010|011000 | 000010)
=011010

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 Verilog HDL

Operator Precedence
A=11110000, B=01011101, C=00000000

1. ~(A&B) =~(11110000 & 01011101)

=~(01010000)
= 10101111

2. (A&&C)= (11110000 && 00000000)=0

3. ~|B = ~|(01011101)=1

4. !B = ~(01011101) //o/p is ‘0’

5. B<<1 = 01011101 <<1 = 10111010

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 Verilog HDL

Exercise
A=10010011 B=01101111

A<<2 = A<<2 = 01001100

A %2= A %2= 1
!(&B)= !(&B)= 0
(A&B)=
(A&B)= 00000011
(A&&b)= 0
(A&&b)=
A===B = 0
A===B

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 Verilog HDL

Exercise
A=4’b0110; b=4’b1001; c=4’b101x; d=4’b101x
C===D
C===D 1
B>>>2
B>>>2 0010
A**B A**B 69
Y=(A>B)? C :D Y=(A>B)? C :D 101x
C==D C==D x
A<=D A<=D 0
Y= Y = {a,b[1],c[0],d[2]} Y= {a,b[1],c[0],d[2]} 01100x0

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ANALYSIS AND DESIGN OF COMBINATIONAL LOGIC Digital Electronics (18EC32)

//Dataflow Description
//Gatelevel Description
module full_adder_data(a,b,c, sum,carry);
module full_adder_gate(a,b,c, sum,carry);
input a,b,c; output sum,carry;
input a,b,c;
assign s= a^b^c;
output reg sum, carry;
assign carry= (a&b)(b&c)|(c&a);
wire x1,x2,x3,x4;
endmodule
xor g1 (x1,a,b);
xor g2(sum,x1,c);
//Behavioral Description and a1(x2,a,b);
module full_adder(a,b,c, sum,carry); and a2(x3, b, c);
input a, b, c; and a3(x4, c, a );
output reg sum, carry; or o1(carry, x2, x3, x4);
always@(c, a, b) endmodule
begin
sum = a ^ b ^ c;
carry= (a&b)|(a&c)|(b&c);
end
endmodule

Girija S., Dept. of ECE, Dr. AIT, Bengaluru

ANALYSIS AND DESIGN OF COMBINATIONAL LOGIC Digital Electronics (18EC32)
1 0 0 0

Ripple Carry Adder 0101

0110
• To add n-bit numbers: 1011

• Use n Full-Adders in parallel

• The carries propagates as in addition by hand
• Use Z in the circuit as a Cin module rca(a,b, c, s, cout);
input [3:0] a,b;
input c; output [3:0] s;
output cout;

wire [2:0]w;

gfulladder g1(s[0],w[0],a[0],b[0],c);
gfulladder g2(s[1],w[1],a[1],b[1],w[0]);
gfulladder g3(s[2],w[2],a[2],b[2],w[1]);
gfulladder g4(s[3],cout,a[3],b[3],w[2]);
endmodule

Girija S., Dept. of ECE, Dr. AIT, Bengaluru

ANALYSIS AND DESIGN OF COMBINATIONAL LOGIC Digital Electronics (18EC32)

Half Subtractor
Difference = A XOR B
Borrow = A’B

module Half_Subtractor(output D, B, input X, Y);

assign D = X ^ Y;
assign B = ~X & Y;
endmodule

Girija S., Dept. of ECE, Dr. AIT, Bengaluru

ANALYSIS AND DESIGN OF COMBINATIONAL LOGIC Digital Electronics (18EC32)

module Full_Subtractor_3(output D, B, input X, Y, Z);

assign D = X ^ Y ^ Z;
assign B = ~X & (Y^Z) | Y & Z;
endmodule

module Full_Sub ( input a, b, bin, output diff, borr );

Logic diagram of full subtractor always @(a or b or bin)

assign {borr,diff} = (~a) + b + bin;

endmodule

Girija S., Dept. of ECE, Dr. AIT, Bengaluru

CARRY LOOK AHEAD ADDER -RTL Code
module CLA_Adder(a,b,cin,sum,cout);
input[3:0] a,b;
input cin;
output [3:0] sum;
output cout;
wire p0,p1,p2,p3,g0,g1,g2,g3,c1,c2,c3,c4;
assign p0=(a[0]^b[0]),
p1=(a[1]^b[1]),
p2=(a[2]^b[2]),
p3=(a[3]^b[3]);
assign g0=(a[0]&b[0]),
g1=(a[1]&b[1]),
g2=(a[2]&b[2]),
g3=(a[3]&b[3]);
assign c0=cin,
c1=g0|(p0&cin),
c2=g1|(p1&g0)|(p1&p0&cin),
c3=g2|(p2&g1)|(p2&p1&g0)|(p1&p1&p0&cin),
c4=g3|(p3&g2)|(p3&p2&g1)|(p3&p2&p1&g0)|(p3&p2&p1&p0&cin);
assign sum[0]=p0^c0,
sum[1]=p1^c1,
sum[2]=p2^c2,
sum[3]=p3^c3; 137
ANALYSIS AND DESIGN OF COMBINATIONAL LOGIC Digital Electronics (18EC32)

In Logic diagram of 2 to 4 line decoder. Here, 2 inputs are decoded into four outputs.

Each output representing one of the minterms of the 2 input variables.

The two inverters provide the complement of the inputs, and each one of four AND gates
generates one of the minterms.

Y0= A’B’ , Y1= A’B, Y2= AB’ and Y3= AB

Girija S., Dept. of ECE, Dr. AIT, Bengaluru

ANALYSIS AND DESIGN OF COMBINATIONAL LOGIC Digital Electronics (18EC32)

//Dataflow Description //Behavioral Description

module decoder24_behaviour(en,a,b,y); module decoder24_behaviour(en,a,b,y);
input en, a, b; input en,a,b;
output [3:0]y; output reg [3:0]y; // use reg to store the output value
wire na, nb; // only in Behavioral modeling.
always @(en,a,b)
assign na = ~a; begin
assign nb = ~b; if(en==1)
begin
// assign output value by referring to logic diagram if(a==1’b0 && b==1'b0) y=4'b1110;
assign y[0] = en&na&nb; else if(a==1’b0 && b==1'b1) y=4'b1101;
assign y[1] = en&na&b; else if(a==1'b1 && b==1'b0) y=4'b1011;
assign y[2] = en&a&nb; else if(a==1 && b==1) y=4'b0111;
assign y[3] = en&a&b; else y=4'bxxxx;
endmodule end
else
y=4'b1111;
end
endmodule

Girija S., Dept. of ECE, Dr. AIT, Bengaluru

ANALYSIS AND DESIGN OF COMBINATIONAL LOGIC Digital Electronics (18EC32)

//Gatelevel Description //Testbench/Stimulus code

module decoder24_behaviour(en,a,b,y); module tb;
input en,a,b; reg a,b,en; // input port are declared in reg(register)
output [3:0]y; wire [3:0]y; // output port are declared in wire(net)
wire na,nb;
// instantiate 4 and gates and 3 not gates decoder24_behaviour dut(en,a,b,y); // instantiate design block
not n1(na,a); initial
not n2(nb,b); begin
$monitor("en=%b a=%b b=%b y=%b",en,a,b,y);
and n3(y[0],en,na,nb); // with reference to truth table provide input values
and n4(y[1],en,na,b); en=0;a=1'bx;b=1'bx;#5
and n5(y[2],en,a,nb); en=1;a=0;b=0;#5
and n6(y[3],en,a,b); en=1;a=0;b=1;#5
en=1;a=1;b=0;#5
endmodule en=1;a=1;b=1;#5
// terminate simulation using $finish system task
$finish;
end
endmodule

Girija S., Dept. of ECE, Dr. AIT, Bengaluru

ANALYSIS AND DESIGN OF COMBINATIONAL LOGIC Digital Electronics (18EC32)

//Dataflow Description //Testbench

module tb;
module decoder_3_8(a, b, c, out); reg a, b,c;
input a,b,c; wire [7:0] out;
decoder_3_8 DUT(a,b,c,out);
output [7:0] out ; initial
assign out [0] = (~a&~b&~c) ; begin
$monitor($time,"a=%b , b=%b , c=%b , out = %b" , a,b,c,out);
assign out [1] =(~a&~b&c) ; a=0 ; b=0 ;c=0 ;
assign out [2] =(~a&b&~c); # 100 a=0 ; b=0 ;c=1 ;
#100 a=0 ; b=1 ;c=0 ;
assign out [3] = (~a&b&c); #100 a=1 ; b=1 ;c=1 ;
assign out [4] = (a&~b&~c); #100 $finish;
end
assign out [5] = (a&~b&c); endmodule
assign out [6] = (a&b&~c);
assign out [7] = (a&b&c);
endmodule

Girija S., Dept. of ECE, Dr. AIT, Bengaluru

ANALYSIS AND DESIGN OF COMBINATIONAL LOGIC Digital Electronics (18EC32)

4:2 Encoder
//Testbench code for 4-2 Encoder
module encode_4_to_2( module top;
input d0,d1,d2,d3, wire a0,a1;
output a0,a1 reg d0,d1,d2,d3;
); Encoder_4_to_2(d0,d1,d2,d3, a0,a1);
wire x,y,z; initial
not g1(x,d2); begin
and g2(y,x,d1); // Initialize Inputs
or g3(a0,y,d3); d0 = 1;d1 = 0;d2 = 0;d3 = 0;
or g4(a1,d2,d3); #100;
endmodule // Add stimulus here
#100;d0 = 0;d1 = 1;d2 = 0;d3 = 0;
#100;d0 = 0;d1 = 0;d2 = 1;d3 = 0;
#100;d0 = 0;d1 = 0;d2 = 0;d3 = 1;
end

Girija S., Dept. of ECE, Dr. AIT, Bengaluru

 Verilog HDL

4:1 Multiplexer

Out = s1’s0’ i0 + s1’s0 i1+ s1s0’i2 + s1s0 i3

Girija S ECE Dr.AIT

 Verilog HDL

4:1 Multiplexer

Method 1. USING LOGIC EQUATIONS

module mux4to1 (out, i0, i1, i2, i3, s1, s0);

output out; //port declarations
input s1, s0;
input i0, i1, i2, i3;
assign out = (~s1 & ~s0 & i0)|(~s1 & s0 & i1)|(s1 & ~s0 &
i2)| (s1&s0&i3);
endmodule

Girija S ECE Dr.AIT

 Verilog HDL

4:1 Multiplexer
Method2 : using conditional operator
// 4-to-1 multiplexer. Port list is taken exactly from the I/O
diagram.
module mux4_to_1 (out, i0, i1, i2, i3, s);

// Port declarations from the I/O diagram

output out;
input i0, i1, i2, i3;
input [1:0]s;

//Use conditional operator

assign out = (s==0)?i0:(s==1)?i1:(s==2)?i2:(s==3)?i3;
endmodule

Girija S ECE Dr.AIT

 Verilog HDL

4:1 Multiplexer
Method3 : using nested ternary/conditional operator
// 4-to-1 multiplexer. Port list is taken exactly from the I/O
diagram.
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

// Port declarations from the I/O diagram

output out;
input i0, i1, i2, i3;
input s1, s0;

//Using nested conditional operator

assign out = s1 ? ( s0 ? i3 : i2) : (s0 ? i1 : i0) ;
endmodule
Girija S ECE Dr.AIT
 Verilog HDL

module stimulus; // Define the stimulus module (no ports)

reg IN0, IN1, IN2, IN3; // Declare variables to be connected to inputs

reg S1, S0;
wire OUTPUT; // Declare output wire

// Instantiate the multiplexer

mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0);
// Stimulate the inputs
initial
begin
IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
$display("IN0= %b, IN1= %b, IN2= %b, IN3= %b\n",IN0,IN1,IN2,IN3);
S1 = 0; S0 = 0; // choose IN0
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
S1 = 0; S0 = 1; // choose IN1
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
S1 = 1; S0 = 0; // choose IN2
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
S1 = 1; S0 = 1; // choose IN3
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
end endmodule

Girija S ECE Dr.AIT

 Verilog HDL

Girija S ECE Dr.AIT

 Verilog HDL

4-bit Full Adder, Using Dataflow Operators

// Define a 4-bit full adder

module fulladd4(sum, c_out, a, b, c_in);

// I/O port declarations

output [3:0] sum;
output c_out;
input[3:0] a, b;
input c_in;
// Specify the function of a full adder
assign {c_out, sum} = a + b + c_in;

endmodule

Girija S ECE Dr.AIT

 Verilog HDL
Example 6-4 4-bit Full Adder, Using Dataflow Operators Cont

// Define the stimulus (top level module)

module stimulus;

// Set up variables
0] A, B;
reg C_IN;
wire [3:0] SUM;
wire C_OUT;

// Instantiate the 4-bit full adder. call it FA1_4

fulladd4 FA1_4(SUM, C_OUT, A, B, C_IN);

// Setup the monitoring for the signal values

initial begin
$monitor($time," A= %b, B=%b, C_IN= %b,, C_OUT= %b, SUM= %b\n", A, B, C_IN, C_OUT, SUM);
end

// Stimulate inputs
initial begin
A = 4'd0; B = 4'd0; C_IN = 1'b0;
#5 A = 4'd34'd4;
#5 A = 4'd2; B = 4'd5;
#5 A = 4'd9; B = 4'd9;
#5 A = 4'd10; B = 4'd15;
#5 A = 4'd10; B = 4'd5; C_IN = 1'b1;
end
endmodule

Girija S ECE Dr.AIT

 Verilog HDL

4-bit Carry Look ahead adder

• In ripple carry adders, the carry must propagate
through the gate before the sum is available at the
output terminals.
• An n-bit ripple carry adder will have 2n gate levels.
• To reduce this delay we go for carry look ahead adder
we define two functions generate and propagate and
make the carry at any stage independent of previous
stage carry.

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 Verilog HDL

4-bit Carry Look ahead adder

Girija S ECE Dr.AIT

 Verilog HDL

4-bit Carry Look ahead adder

𝑠𝑖 = 𝑥𝑖 xor 𝑦𝑖 xor 𝑐𝑖
𝐶𝑖+1 = 𝑥𝑖 𝑦𝑖 + 𝑥𝑖 𝑐𝑖 + 𝑦𝑖 𝑐𝑖 or
𝐶𝑖+1 = 𝑥𝑖 𝑦𝑖 + 𝑐𝑖 𝑥𝑖 𝑥𝑜𝑟 𝑦𝑖 = 𝐺𝑖 + 𝑃𝑖 𝐶𝑖
G – Generate function= 𝒙𝒊 𝒚𝒊
P - Propagate function= 𝒙𝒊 𝒙𝒐𝒓 𝒚𝒊
Consider a 4-bit adder
𝐶1 = 𝐺0 +𝑃0 𝐶0
𝐶2 = 𝐺1 +𝑃1 𝐶1 = 𝐺1 +𝑃1 𝐺0 +𝑃1 𝑃0 𝐶0
𝐶3 = 𝐺2 +𝑃2 𝐶2 = 𝐺2 +𝑃2 𝐺1 +𝑃2 𝑃1 𝐺0 + 𝑃2 𝑃1 𝑃0 𝐶0
𝐶4 = 𝐺3 +𝑃3 𝐶3 = 𝐺3 +𝑃3 𝐺2 +𝑃3 𝑃2 𝐺1 +𝑃3 𝑃2 𝑃1 𝐺0 +𝑃3 𝑃2 𝑃1 𝑃0 𝐺0

Girija S ECE Dr.AIT

 Verilog HDL
//4-bit Full Adder With Carry Lookahead
module fulladd4(sum, c_out, a, b, c_in);

// Inputs and outputs output [3:0] sum; output

c_out;
input [3:0] a,b; input c_in;

// Internal wires
wire p0,g0, p1,g1, p2,g2, p3,g3; wire c4, c3, c2, c1;

// compute the p for each stage

assign p0 = a[0] ^ b[0],
p1 = a[1] ^ b[1],
p2 = a[2] ^ b[2],
p3 = a[3] ^ b[3];

// compute the g for each stage

assign g0 = a[0] & b[0],
g1 = a[1] & b[1],
g2 = a[2] & b[2],
g3 = a[3] & b[3];

Girija S ECE Dr.AIT

 Verilog HDL

// compute the carry for each stage

// Note that c_in is equivalent c0 in the arithmetic equation for carry lookhead
computation
assign c1 = g0 | (p0 & c_in),
c2 = g1 | (p1 & g0) | (p1 & p0 & c_in),
c3 = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & c_in),
c4 = g3 | (p3 & g2) | (p3 & p2 & g1)
| (p3 & p2 & p1 & g0) | (p3 & p2 & p1 & p0 & c_in);

// Compute Sum
assign sum[0] = p0 ^ c_in,
sum[1] = p1 ^ c1,
sum[2] = p2 ^ c2,
sum[3] = p3 ^ c3;

// Assign carry output

assign c_out = c4;

endmodule

Girija S ECE Dr.AIT