74AC175 • 74ACT175 Quad D-Type Flip-Flop
November 1988
Revised November 1999
74AC175 • 74ACT175
Quad D-Type Flip-Flop
General Description Features
The AC/ACT175 is a high-speed quad D-type flip-flop. The ■ ICC reduced by 50%
device is useful for general flip-flop requirements where ■ Edge-triggered D-type inputs
clock and clear inputs are common. The information on the
D-type inputs is stored during the LOW-to-HIGH clock tran- ■ Buffered positive edge-triggered clock
sition. Both true and complemented outputs of each flip- ■ Asynchronous common reset
flop are provided. A Master Reset input resets all flip-flops, ■ True and complement output
independent of the Clock or D-type inputs, when LOW. ■ Outputs source/sink 24 mA
■ ACT175 has TTL-compatible inputs
Ordering Code:
Order Number Package Number Package Description
74AC175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74AC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC175PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74ACT175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT175PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names Description
D0–D3 Data Inputs
CP Clock Pulse Input
MR Master Reset Input
Q0–Q3 True Outputs
Q0–Q3 Complement Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS009936 www.fairchildsemi.com
74AC175 • 74ACT175
Functional Description Truth Table
The AC/ACT175 consists of four edge-triggered D-type flip-
flops with individual D inputs and Q and Q outputs. The Inputs Outputs
Clock and Master Reset are common. The four flip-flops @ tn, MR = H @ tn+1
will store the state of their individual D inputs on the LOW-
to-HIGH clock (CP) transition, causing individual Q and Q Dn Qn Qn
outputs to follow. A LOW input on the Master Reset (MR)
will force all Q outputs LOW and Q outputs HIGH indepen- L L H
dent of Clock or Data inputs. The AC/ACT175 is useful for H H L
general logic applications where a common Master Reset
and Clock are acceptable. H = HIGH Voltage Level
L = LOW Voltage Level
tn = Bit Time before Clock Pulse
tn+1 = Bit Time after Clock Pulse
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74AC175 • 74ACT175
Absolute Maximum Ratings(Note 1) Recommended Operating
Supply Voltage (VCC) −0.5V to +7.0V Conditions
DC Input Diode Current (IIK) Supply Voltage (VCC)
VI = −0.5V −20 mA AC 2.0V to 6.0V
VI = VCC + 0.5V +20 mA ACT 4.5V to 5.5V
DC Input Voltage (VI) −0.5V to VCC + 0.5V Input Voltage (VI) 0V to VCC
DC Output Diode Current (IOK) Output Voltage (VO) 0V to VCC
VO = −0.5V −20 mA Operating Temperature (TA) −40°C to +85°C
VO = VCC + 0.5V +20 mA Minimum Input Edge Rate (∆V/∆t)
DC Output Voltage (VO) −0.5V to VCC + 0.5V AC Devices
DC Output Source VIN from 30% to 70% of VCC
or Sink Current (IO) ± 50 mA VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns
DC VCC or Ground Current Minimum Input Edge Rate (∆V/∆t)
per Output Pin (ICC or IGND) ± 50 mA ACT Devices
Storage Temperature (TSTG) −65°C to +150°C VIN from 0.8V to 2.0V
Junction Temperature (TJ) VCC @ 4.5V, 5.5V 125 mV/ns
PDIP 140°C Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications
DC Electrical Characteristics for AC
VCC TA = +25°C TA = −40°C to +85°C
Symbol Parameter Units Conditions
(V) Typ Guaranteed Limits
VIH Minimum HIGH Level 3.0 1.5 2.1 2.1 VOUT = 0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V
5.5 2.75 3.85 3.85
VIL Maximum LOW Level 3.0 1.5 0.9 0.9 VOUT = 0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V
5.5 2.75 1.65 1.65
VOH Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V IOUT = −50 µA
5.5 5.49 5.4 5.4
VIN = VIL or VIH
3.0 2.56 2.46 IOH = −12 mA
4.5 3.86 3.76 V IOH = −24 mA
5.5 4.86 4.76 IOH = −24 mA (Note 2)
VOL Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V IOUT = 50 µA
5.5 0.001 0.1 0.1
VIN = VIL or VIH
3.0 0.36 0.44 IOL = 12 mA
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 2)
IIN Maximum Input
5.5 ±0.1 ± 1.0 µA VI = VCC, GND
(Note 4) Leakage Current
IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max
IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min
ICC Maximum Quiescent
5.5 4.0 40.0 µA VIN = VCC or GND
(Note 4) Supply Current
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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74AC175 • 74ACT175
DC Electrical Characteristics for ACT
VCC TA = +25°C TA = −40°C to +85°C
Symbol Parameter Units Conditions
(V) Typ Guaranteed Limits
VIH Minimum HIGH Level 4.5 1.5 2.0 2.0 VOUT = 0.1V
V
Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V
VIL Maximum LOW Level 4.5 1.5 0.8 0.8 VOUT = 0.1V
V
Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V
VOH Minimum HIGH Level 4.5 4.49 4.4 4.4
V IOUT = −50 µA
Output Voltage 5.5 5.49 5.4 5.4
VIN = VIL or VIH
4.5 3.86 3.76 V IOH = −24 mA
5.5 4.86 4.76 IOH = −24 mA (Note 5)
VOL Maximum LOW Level 4.5 0.001 0.1 0.1
V IOUT = 50 µA
Output Voltage 5.5 0.001 0.1 0.1
VIN = VIL or VIH
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 5)
IIN Maximum Input Leakage Current 5.5 ±0.1 ± 1.0 µA VI = VCC, GND
ICCT Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V
IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max
IOHD Output Current(Note 6) 5.5 −75 mA VOHD = 3.85V Min
ICC Maximum Quiescent VIN = VCC
5.5 4.0 40.0 µA
Supply Current or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
VCC TA = +25°C TA = −40°C to +85°C
Symbol Parameter (V) CL = 50 pF CL = 50 pF Units
(Note 7) Min Typ Max Min Max
fMAX Maximum Clock 3.3 149 214 139
MHz
Frequency 5.0 187 244 187
tPLH Propagation Delay 3.3 2.0 9.5 12.0 2.0 13.5
ns
CP to Qn or Qn 5.0 1.5 7.0 9.0 1.0 9.5
tPHL Propagation Delay 3.3 2.5 8.5 13.0 2.0 14.5
ns
CP to Qn or Qn 5.0 1.5 6.0 9.5 1.5 10.5
tPLH Propagation Delay 3.3 3.0 7.5 12.5 2.5 13.5
ns
MR to Qn 5.0 2.0 5.5 9.0 1.5 10.0
tPHL Propagation Delay 3.3 3.0 8.5 11.0 2.5 12.5
ns
MR to Qn 5.0 2.0 6.0 8.5 1.5 9.0
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
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74AC175 • 74ACT175
AC Operating Requirements for AC
VCC TA = +25°C TA = −40°C to +85°C
Symbol Parameter (V) CL = 50 pF CL = 50 pF Units
(Note 8) Typ Guaranteed Minimum
tS Setup Time, HIGH or LOW 3.3 2.0 4.5 4.5
ns
Dn to CP 5.0 1.0 3.0 3.0
tH Hold Time, HIGH or LOW 3.3 1.0 1.0 1.0
ns
Dn to CP 5.0 1.0 1.0 1.0
tW CP Pulse Width 3.3 2.5 4.5 4.5
ns
HIGH or LOW 5.0 2.0 3.5 3.5
tW MR Pulse Width, LOW 3.3 2.5 4.5 5.0
ns
5.0 2.0 3.5 3.5
tREC Recovery Time 3.3 −2.0 0 0
ns
MR to CP 5.0 −1.0 0 0
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics for ACT
VCC TA = +25°C TA = −40°C to +85°C
Symbol Parameter (V) CL = 50 pF CL = 50 pF Units
(Note 9) Min Typ Max Min Max
fMAX Maximum Clock
5.0 175 236 145 MHz
Frequency
tPLH Propagation Delay
5.0 2.0 6.0 10.0 1.5 11.0 ns
CP to Qn or Qn
tPHL Propagation Delay
5.0 2.0 7.0 11.0 1.5 12.0 ns
CP to Qn or Qn
tPLH Propagation Delay
5.0 2.0 6.0 9.5 1.5 10.5 ns
MR to Qn
tPHL Propagation Delay
5.0 2.0 5.5 9.5 1.5 10.5 ns
MR to Qn
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements for ACT
VCC TA = +25°C TA = −40°C to +85°C
Symbol Parameter (V) CL = 50 pF CL = 50 pF Units
(Note 10) Typ Guaranteed Minimum
tS (H) Setup Time 5.0 3.0 2.0 2.0
ns
tS (L) Dn to CP 3.0 2.5 2.5
tH Hold Time, HIGH or LOW
5.0 0 1.0 1.0 ns
Dn to CP
tW CP Pulse Width
5.0 4.0 3.0 3.5 ns
HIGH or LOW
tW MR Pulse Width, LOW 5.0 4.0 3.0 4.0 ns
trec Recovery Time, MR to CP 5.0 0 0 0 ns
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol Parameter Typ Units Conditions
CIN Input Capacitance 4.5 pF V CC = OPEN
CPD Power Dissipation Capacitance 45.0 pF V CC = 5.0V
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74AC175 • 74ACT175
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
Package Number M16A
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74AC175 • 74ACT175
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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74AC175 • 74ACT175
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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74AC175 • 74ACT175 Quad D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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SEMICONDUCTOR CORPORATION. As used herein:
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body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support
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instructions for use provided in the labeling, can be rea-
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