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The document outlines a comprehensive 100-day curriculum covering various topics in digital design and Verilog programming. It includes fundamental concepts such as multiplexers, logical gates, and data types, as well as advanced topics like finite state machines, digital clocks, and communication protocols. Each day focuses on a specific topic, providing a structured approach to learning digital system design.

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0% found this document useful (0 votes)
8 views3 pages

Topics

The document outlines a comprehensive 100-day curriculum covering various topics in digital design and Verilog programming. It includes fundamental concepts such as multiplexers, logical gates, and data types, as well as advanced topics like finite state machines, digital clocks, and communication protocols. Each day focuses on a specific topic, providing a structured approach to learning digital system design.

Uploaded by

Harsh saini
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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day1:"basic 2:1 mux"

day2:"logical gates"
day3:"datatyes"(two types of datatypes *net type *re datatype)
day4:"verilog operators"
day5:"modules and ports"(implements by 4_1 mux)
day6:"gate modeling"(by using logical gates(structural modeling))
day7:"dataflow modeling" (using assign statement implement by gray to binary code
by xor)
day8:"behviour modeling "(using always block implemented by counter(8bit))
day9:"traffic light"(it works based fsm(states) default state is red )
day10:"digital clock"(the clock upto 15 then resets to 0)
day11:"jk-flipflop(edge)"(overcome the condition of j=1 k=1 it toggles the previous
output q )
day12:"sr-latch(level)"(set-when s=1 reset when r=1 depends on (s,r) not the
clk(while flipflops depends on clk (edge)))
day13:"up-counter"(by counting (increasing the count by 1 count+=1 initialising
count=0000 by reset))
day14:"down-counter"(by counting(decresing by 1 count-=1 initialising count=1111 by
reset))
day15:"shift register"(shifts by right or left )
day16:"carry-look-ahead-adder"(overcome the problem of propagation delay in ripple
carry adder by generate and propagation signal g=a&b p=a^b )
day17:"4-bitadder-subtractor"(based on the crtl signal if crtl?add:sub(2's
complement will be done by xor operation))
day18:"comparator"(compare two inputs and produce the ouput (a>b)(a<b)(a==b))
day19:"Demux 1:4"(1 inputs 4 output base selection line sel[1:0] (2 bits))
day20:"gray to binary code"
day21:"ripple_carry_adder"(output of the 1st will be the cin of the next inputs)
day22:"full adder"
day23:"full subtractor"
day24:"binary encoder"2^n input n output "(difference between encoder and mux is
there will be selection line here there is not like that. )
day25:"priority encoder"(to overcome the drwback of binary encoder where in encoder
the o/p is invalid when 2 i/p is set as high here it will prioritize that which is
to be)
day26:"decoder"(n input 2^n output)
day27:"universal shift register"(it can be used as pipo,sipo,siso,piso)
day28:"LFSR"(it takes any of the 2 binary bits and done xor operation sequentially
as per our requirements)
day29:"MULTIPLIER"(it gives partial multiplied value
)
day30:"clock_divider"
day31:"carry select adder"(this adder is used to spped up the addition process and
multiple cin will performed in parallel form)
day32:"binary to one hot encoder"(this type of encoder sets only one bt has high)
day33:"n_bit_comparator"(it compares n bit data )
day34:"barrel_shifter"(that shift dataword for a specific no of bits)
day35:"d_latch using 2:1 mux"
day36:"universal binary counter" (it up count,down count and load specific values
based on the control input)
day37:"parallel in parallel out sift register"(it shifts parallely)
day 38:"Parallel in seriel out"(it takes parallel input and produce serial output)
day39:"serial in parallel out"(it takes serial input and produces parallel output)
day40:"serial in serial out"(it takes serial input and produce serial output)
day41:"ring counter"(this counter is like a shift register typically the output of
last ff will be fed to the input of 1st ff)
day42:"majority detector"(it outputs 1 if the majority of the inputs are 1. it is
used to voting system,decision making process)
day43:"minority detector"(the outputs are 1 when the minority of the inputs are 1)
day44:"Johnson Counter"(the complement output of the last flipflop is given as a
input to the new flipflop (it is also called Twisted ring counter))
day45:"serial adder"(it adds bit by bit of two binary numbers processing 1 bit at a
time)
day46:"SEQUENCE GENERATOR"(it generate a sequence)
day47:"clock buffer"(it distributes clock signal to diffrent parts of
digitalsystem)
day48:"simple register"(it is used to store and transfer the data)
day49:"7 segment display"(it is generally used to display decimal digits in digital
systems )
day50:"array multiplier"(it is used to multiply two binary numbers)
day51:"booth multiplier"(Booth's algorithm can handle both positive and negative
numbers efficiently.)
day52:"wallace_tree_multipler"(it is also used for multiplying two binary number
and it is very efficient than other )
day53:"restoring division algorithm"(it is used to divide two binary numbers and
It involves a sequence of shift and subtract operations to compute the quotient and
remainder)
day54:"GCD"(determining GCD using behaviour model and euclid's algorithm)
day55:"single port ram "(it is used to write a data in a required address in a ram
and read a data in a required address)
day56:"round_orbit_arbitor"(A round-robin arbiter is a type of digital circuit used
to allocate access to a shared resource among multiple requesters in a cyclic
order.)
day57:"CN-change-nochange flipflop"(The CN Flip-Flop is a unique type of flip-flop
that allows the output to either change its state or remain unchanged based on the
control input)
day58:"fixed_priority_arbitor"( In a fixed priority arbiter, each request has a
predetermined priority level that does not change over time)
day59:"dynamic priority arbitor"(Unlike fixed priority arbiters, where the priority
is predetermined, a dynamic priority arbiter can adjust the priority based on
certain conditions)
day60:"dual port ram"(Dual-port RAM allows simultaneous read and write operations
on two different memory addresses, making it highly efficient for parallel
processing applications)
day61:"7 segment display using rom "(By using a ROM, I mapped each input value to
the corresponding segment outputs that create the desired digit on the display)
day62:"dram using fsm"(It is characterized by its ability to store each bit of data
in a separate capacitor within an integrated circuit)
day63:"carry skip adder"(The carry skip adder efficiently handles the addition of
4-bit binary numbers by using a parallel adder and an XOR-based skip mechanism)
day64:"bcd to binary"(it is used to coonvert bcd to binary)
day65:"dual_edge_triggering"(it is able change the output botj on falling and
leading edge clk)
day66:"convert bcd to binary"("it is used to convert the bcd to binary
representation)
day67:"convert bcd toexcee 3 converter"( Each digit of a decimal number is
represented by its corresponding 4-bit binary equivalent, incremented by 3)
day68:"check the number is even or odd"
day69:"clock phasing"(it is used to represent the different clock pahses
90',0',180',270');
day70:"synchronous fifo"(it works sequentially diffrent from dual port . in dual
port we specify in which location we are going to write and vicde versa but here
user not allowed to customize the data addr it is for temporary memory)
day71:"synchronous lifo"
day72:"is_prime"(to check number is a prime)
day73:"is palindrime"(to check a number is a palindrome or not )
day74:"check armstrong"(to check the given number is armstrong or not)
day75:"clock edge detector"(to detect positive edge or negetive edge or dual edge)
day76:"hot fsm"
day77:"elevator fsm"(working of elevator using verilog)
day78:"vending machine fsm"(working of vending machine)
day79:"sequence detector 1100"(non overlapping sequence detector 1100 using verilog
(MOORE))
day80:"sequence detector 0101"(overlapping sequnce detector 0101 using verilog
(MOORE))
day81:"sequence detector 1011"(non overlapping sequence detector (MEALY) using
verilog)
day82:"sequence detector 0010"(overlapping sequence detector (MEALY) using verilog)
day83:"gray counter"(it counts in gray code based)
day84:"two sequence detector"(it detects two sequenctor "101" and "0010")
day85:"digital watch fsm"
day86:"password checker"(the user will give default password and it verfies each
time whether the password(4digits) is correct or not)
day87:"credit card"(it is used to verify valid data and sufficient balance is there
in the respective account and give the transaction status)
day88:"temperature controller"(it is used to control the temperature depending on
high or low than setpoint )
day89:"WASHING MACHINE"(this topic shows the working of washing machine in terms of
fsm)
day90:"ATM FSM"
day91:"apb-sram interface"
day92:"i2c arbitration"(in i2c communication 2 master try to ownership of the bus
so using wired and operation one master will be neglect this process is called
arbitration )
day93:"apb protocol"(it is used to
data transfer between a master and a peripheral using the APB (Advanced Peripheral
Bus))
day94:"uart serial communication"(this protocol is used to communicate with
microncontroller or any other peripherals)
day95:"car parking management"
day96:"error detection using hamming decoder and encoder"
day97:"pulse width modulation "
day98:"simple spi communication "
day99:"vga controller (video graphics controller)"
day100:"voting_machine"

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