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Mid17 Sol

The document contains midterm solutions for digital circuits, including a mix of questions on binary conversion, truth tables, Karnaugh maps, and combinational logic. It provides detailed answers and explanations for various problems related to digital logic design. Additionally, it includes figures for circuit implementations and truth tables.

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0% found this document useful (0 votes)
26 views6 pages

Mid17 Sol

The document contains midterm solutions for digital circuits, including a mix of questions on binary conversion, truth tables, Karnaugh maps, and combinational logic. It provides detailed answers and explanations for various problems related to digital logic design. Additionally, it includes figures for circuit implementations and truth tables.

Uploaded by

gxrc46r82m
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Digital Circuits

Midterm Solutions

1. Mix of Questions (40 points)


Answer the following 8 questions. Simple reasoning will be enough. Each of them worth
5 points.

(a) Covert the binary number 1011.01(2) to decimal.


(b) Add binary numbers 101.011(2) + 11.101(2) (Your answer should be a binary number
as well).
(c) Determine the 2’s complement of 10011000.
(d) Construct a truth table of X = ĀB + AB C̄ + ĀC̄ + AB̄C.
(e) Convert X = AB(CD + EF ) to sum-of-product (SOP) form.
(f) Implement a logic circuit for X = AD + B C̄.
(g) For the full-adder with input A = 0, B = 1, Cin = 1, determine the outputs Σ and
Cout .
(h) Design a simple decoder that detects the presence of the binary code 0110.

Solution: Mix of Questions

(a) 23 + 21 + 20 + 2−2 = 11.25.


(b) 1001.
(c) 1’s complement of the given number is 01100111. We need to add 1 after that which
gives us 01101000.
(d) X = ĀB + AB C̄ + ĀC̄ + AB̄C.
A B C X
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
(e) We have

X =AB(C̄D + EF ) (1)
=AB + C̄D + EF (2)

Midterm Page 1 of 6
=Ā + B̄ + C̄D · EF (3)
=Ā + B̄ + (C + D̄)(Ē + F̄ ) (4)
=Ā + B̄ + C Ē + D̄Ē + C F̄ + D̄F̄ . (5)

(f) Figure 1 shows the logic circuit.

Figure 1: Problem 1(f).

(g) Σ = 0 and Cout = 1.


(h) Figure 2 shows the decoder.

Figure 2: Problem 1(h).

Midterm Page 2 of 6
2. Karnaugh Map (30 points)
Let X = (A + BC)(AC + D) + ĀB C̄ D̄.

(a) Develop a truth table of X. (10 points)


(Hint: You can simplify the formula first)
(b) Use a Karnaugh map to reduce X to a minimum SOP form.(10 points)
(c) Use a Karnaugh map to reduce X to a minimum POS form.(10 points)

Solution: Karnaugh Map.

(a) We can simplify X first.

X =(A + BC)(AC + D) + ĀB C̄ D̄ (6)


=A + BC + AC + D + ĀB C̄ D̄ (7)
=Ā(B̄ + C) + (Ā + C̄)D + ĀB C̄ D̄ (8)
=ĀB̄ + ĀC + ĀD + C̄D + ĀB C̄ D̄. (9)

This provides
A B C D X
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 0
(b) It is not hard to show that X = Ā + C̄D.
(c) It is not hard to show that X = (Ā + D)(Ā + C̄).

Midterm Page 3 of 6
Figure 3: Problem 2.

3. Functions of Combinational Logic (30 points)

(a) For the multiplexer in Figure 4, input states are given by D0 = 1, D1 = 1, D2 =


0, D3 = 0. Then, determine the output waveform when the data-select inputs are
sequenced as shown by the waveforms in Figure 5. (15 points)

Figure 4: Multiplexer.

Figure 5: Data-Select Input Waveforms.

Midterm Page 4 of 6
(b) Suppose you have two 4-bit odd parity generators as decribed in Figure 6. This
4-bit odd parity generators outputs 1 if even numbers of inputs are 1 and outputs
0 if odd numbers of inputs are 1. For example, the output is P = 1 if A = 1, B =
0, C = 1, D = 0, and the output is P = 0 if A = 1, B = 0, C = 1, D = 1. Construct
8-bit odd parity generator using two 4-bit odd parity generators with one additional
logic gate. (15 points)
(Hint: Again, 8-bit odd parity generator outputs 1 if even number of inputs are 1
and outputs 0 if odd numbers of inputs are 1)

Figure 6: Data-Select Input Waveforms.

Solution: Functions of Combinational Logic

(a) Figure 7 shows the output waveform. Y = 1 if and only if S1 = 0, S0 = 0 or


S1 = 0, S0 = 1. In other words, Y = S¯1 .

Figure 7: Problem 3(a).

(b) Figure 8 shows the 8-bit odd parity generators using two 4-bit odd parity generator
and one XNOR gate. This is because the output should be 1 if and only if two 4-bit
odd parity generators have the same output.

Midterm Page 5 of 6
Figure 8: Problem 3(b) 8-bit Odd Parity Generator.

Midterm Page 6 of 6

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