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CSA Unit 2 (mcq's) - Exams

Network Analysis (Bangalore University)

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COMPUTER SYSTEM ARCHITECTURE

(MCQ’S)

Unit - 2

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1. Any signed negative binary number c) Adding

is recognised by its _ d) Subtracting
a) MSB
b) LSB Answer: b
c) Byte Explanation: On multiplying the
d) Nibble decimal number continuously by 2,
the binary equivalent is obtained by
Answer: a the collection of the integer part.
Explanation: Any negative number is However, if it‟s an integer, then it‟s
recognized by its MSB (Most binary equivalent is determined by
Significant Bit). dividing the number by 2 and
If it‟s 1, then ít‟s negative, else if it‟s collecting the remainders.
0, then positive.
4. The representation of octal
2. The parameter through which 16 number (532.2)8 in decimal is
distinct values can be represented is
known as a) Dividing
a) Bit b) Multiplying
b) Byte
c) Word
d) Nibble

Answer: c
Explanation: It can be represented up
to 16 different values with the help of
a Word. Nibble is a combination of
four bits and Byte is a combination of
8 bits. It is “word” which is said to be
a collection of 16-bits on most of the
systems.
3. If the decimal number is a fraction
then its binary equivalent is obtained
by the number
continuously by 2.

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a) (346.25)10
b) (532.864)10
c) (340.67)10
d) (531.668)10

Answer: a
Explanation: Octal to Decimal
conversion is obtained by
multiplying 8 to the power of
base index along with the value
at that index position. (532.2)8
= 5 * 82 + 3 * 81 + 2 * 80 + 2 *
8-1 = (346.25)10
5. Which of the following is not a
data type?
a) Symbolic Data
b) Alphanumeric Data
c) Numeric Data
d) Alphabetic Data

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Answer: a has no I.Q. of its own. It does only

Explanation: Data types are of three what it is programmed to do. It
basic types: Numeric, Alphabetic and cannot take decisions of its own.
Alphanumeric. Numeric Data consists A computer is diligent because it can
of only numbers. work continuously for hours without
Alphabetic Data consists of only getting any errors or without getting
letters and a blank character and grumbled.
alphanumeric data consists of The accuracy of a computer is
symbols. consistently high and its level of
accuracy depends on its design. A
6. is the raw material computer can perform any task if, it
used as input and is the can be broken down into a series of
processed data obtained as output of logical steps. Therefore, a computer
data processing. is versatile.
a) Data, Instructions
b) Instructions, Program 8. Fill in the blank in the diagram.
c) Data, Program
d) Program, Code

Answer: a
Explanation: Data can be assumed as
a raw material which, in turns after
processing gives the desired output in
the form of instructions. Further, a
set of ordered and meaningful a) Input Unit
instructions is known as a program. b) Memory Unit
c) Control Unit
7. Which of the following is not a d) I/O Unit
characteristic of a computer?
a) Diligence Answer: c
b) I.Q. Explanation: The control unit
c) Accuracy manages and coordinates the
d) Versatility operations of a computer system.
The ALU is responsible for performing
Answer: b all the arithmetic and bitwise
Explanation: The Computer system operations . Therefore, both these

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units combine to form the brain of address for the read and write
the computer ,which is the central operations.
processing unit.
11. If the control signals are
9. The part of a processor which generated by combinational logic,
contains hardware necessary to then they are generated by a type of
perform all the operations required controlled unit.
by a computer: a) Micro programmed
a) Data path b) Software
b) Controller c) Logic
c) Registers d) Hardwired
d) Cache
Answer: d
Answer: a Explanation: The main task of a
Explanation: A processor is a part of control unit is to generate control
the computer which does all the data signals. There are two main types of
manipulation and decision making. A control units:
processor comprises of: A hardwired control unit generates
A data path which contains the control signals by using
hardware necessary to perform all combinational logic circuits and the
the operations. A controller tells the Micro programmed control unit
data path what needs to be done. generates control signals by using
The registers act as intermediate some softwares.
storage for the data.
12. Which is the simplest method of
10. What does MAR stand for? implementing hardwired control
a) Main Address Register unit?
b) Memory Access Register a) State Table Method
c) Main Accessible Register b) Delay Element Method
d) Memory Address Register c) Sequence Counter Method
d) Using Circuits
Answer: d
Explanation: MAR is a type of register Answer: a
which is responsible for the fetch Explanation: There are 3 ways of
operation. MAR is connected to the implementing hardwired control unit:
address bus and it specifies the A state table is the simplest method

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in which a number of circuits are understands only binary language.

designed based on the cells in the So, the micro-program should have
table. instructions which are in the form of
A delay element method consists of a 0s and 1s. Each output line of the
flowchart drawn for the circuit. A D- micro-program corresponds to one
flip flop is used as a delay element. control signal.
A sequence counter method used k-
modulo counter as a replacement for 15. A decoder is required in case of a
k delay elements.
a) Vertical Microinstruction
13. A set of microinstructions for a b) Horizontal Microinstruction
single machine instruction is called c) Multilevel Microinstruction
d) All types of microinstructions
a) Program
b) Command Answer: a
c) Micro program Explanation: There are two types of
d) Micro command microinstructions: Horizontal and
Vertical.
Answer: c In a horizontal microinstruction, each
Explanation: For every micro- bit represents a signal to be activated
operation, a set of microinstructions whereas, in case of vertical
are written which indicate the control microinstruction bits are decoded
signals to be activated. A set of and, the decoder then produces
microinstructions is a micro program. signals.
The address of the next
microinstruction is given by a Micro- 16. In boolean algebra, the OR
program counter. operation is performed by which
properties?
14. Micro-program consists of a set of
a) Associative properties
microinstructions which are strings of
0s and 1s. b) Commutative properties
a) True c) Distributive properties
b) False d) All of the Mentioned

Answer: a Answer: d
Explanation: The computer Explanation: The expression for

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Associative property is given by 19. The involution of A is equal to

A+(B+C) = (A+B)+C & A*(B*C) =
(A*B)*C. a) A
The expression for Commutative b) A‟
property is given by A+B = B+A & A*B c) 1
= B*A. d) 0
The expression for Distributive
Answer: a
property is given by A+BC=(A+B)(A+C)
Explanation: The involution of A
& A(B+C) = AB+AC.
means double inversion of A (i.e. A”)
17. The expression for Absorption law and is equal to A.
is given by Proof: ((A)‟)‟ = A
a) A + AB = A
20. A(A + B) = ?
b) A + AB = B
a) AB
c) AB + AA‟ = A
b) 1
d) A + B = B + A
c) (1 + AB)
Answer: a d) A
Explanation: The expression for
Answer: d
Absorption Law is given by: A+AB = A.
Explanation: A(A + B) = AA + AB (By
Proof: A + AB = A(1+B) = A (Since 1 +
Distributive Property) = A + AB (A.A =
B = 1 as per 1‟s Property).
A By Commutative Property) = A(1 +
18. According to boolean law: A + 1 = B) = A*1 (1 + B = 1 by 1‟s Property) =
? A.
a) 1
21. DeMorgan‟s theorem states that
b) A
c) 0
a) (AB)‟ = A‟ + B‟
d) A‟
b) (A + B)‟ = A‟ * B
Answer: a c) A‟ + B‟ = A‟B‟
Explanation: A + 1 = 1, as per 1‟s d) (AB)‟ = A‟ + B
Property.

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Answer: a Answer: a
Explanation: The DeMorgan‟s law Explanation: Y = AB‟ + (A‟ + B)C = AB‟
states that (AB)‟ = A‟ + B‟ & (A + B)‟ = + (AB‟)‟C = (AB‟ + C)( AB‟ + AB‟) = (AB‟
A‟ * B‟, as per the Dual Property. + C).1 = (AB‟ + C).

22. (A + B)(A‟ * B‟) = ? 25. The boolean function A + BC is a

a) 1 reduced form of
b) 0 a) AB + BC
c) AB b) (A + B)(A + C)
d) AB‟ c) A‟B + AB‟C
d) (A + C)B
Answer: b
Explanation: The DeMorgan‟s law Answer: b
states that (AB)‟ = A‟ + B‟ & (A + B)‟ = Explanation: (A + B)(A + C) = AA + AC
A‟ * B‟, as per the Dual Property. + AB + BC = A + AC + AB + BC (By
Commutative Property) = A(1 + C + B)
23. Complement of the expression
+ BC = A + BC (1 + B + C =1 By 1‟s
A‟B + CD‟ is
Property).
a) (A‟ + B)(C‟ + D)
b) (A + B‟)(C‟ + D) 26. What is an ambiguous condition
c) (A‟ + B)(C‟ + D) in a NAND based S‟-R‟ latch?
d) (A + B‟)(C + D‟) a) S‟=0, R‟=1
b) S‟=1, R‟=0
Answer: b
c) S‟=1, R‟=1
Explanation: (A‟B + CD‟)‟ = (A‟B)'(CD‟)‟
d) S‟=0, R‟=0
(By DeMorgan‟s Theorem) = (A” +
B‟)(C‟ + D”) (By DeMorgan‟s Theorem) Answer: d
= (A + B‟)(C‟ + D). Explanation: In a NAND based S-R
latch, If S‟=0 & R‟=0 then both the
24. Simplify Y = AB‟ + (A‟ + B)C.
outputs (i.e. Q & Q‟) goes HIGH and
a) AB‟ + C
this condition is called as
b) AB + AC
ambiguous/forbidden state. This
c) A‟B + AC‟
state is also known as an Invalid state
d) AB + A

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as the system goes into an 29. One major difference between a

unexpected situation. NAND based S‟-R‟ latch & a NOR
based S-R latch is
27. In a NAND based S‟-R‟ latch, if
a) The inputs of NOR latch are 0 but 1
S‟=1 & R‟=1 then the state of the
for NAND latch
latch is
b) The inputs of NOR latch are 1 but 0
a) No change
for NAND latch
b) Set
c) The output of NAND latch becomes
c) Reset
set if S‟=0 & R‟=1 and vice versa for
d) Forbidden
NOR latch
Answer: a d) The output of NOR latch is 1 but 0
Explanation: In a NAND based S‟-R, for NAND latch
latch if S‟=1 & R‟=1 then there is no
Answer: a
any change in the state. It remains in
Explanation: Due to inverted input of
its prior state. This state is used for
NAND based S‟-R‟ latch, the inputs of
the storage of data.
NOR latch are 0 but 1 for NAND latch.
28. A NAND based S‟-R‟ latch can be
30. The characteristic equation of S-R
converted into S-R latch by placing
latch is
a) Q(n+1) = (S + Q(n))R‟
a) A D latch at each of its input
b) Q(n+1) = SR + Q(n)R
b) An inverter at each of its input
c) Q(n+1) = S‟R + Q(n)R
c) It can never be converted
d) Q(n+1) = S‟R + Q'(n)R
d) Both a D latch and an inverter at its
input Answer: a
Explanation: A characteristic equation
Answer: d
is needed when a specific gate
Explanation: A NAND based S‟-R‟
requires a specific output in order to
latch can be converted into S-R latch
satisfy the truth table. The
by placing either a D latch or an
characteristic equation of S-R latch is
inverter at its input as it‟s operations
Q(n+1) = (S + Q(n))R‟.
will be complementary.

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31. The difference between a flip-flop Answer: b

& latch is Explanation: The S-R flip flop consist
a) Both are same of two additional AND gates at the S
b) Flip-flop consist of an extra output and R inputs of S-R latch.
c) Latches has one input but flip-flop
34. What is one disadvantage of an S-
has two
R flip-flop?
d) Latch has two inputs but flip-flop
a) It has no Enable input
has one
b) It has a RACE condition
Answer: c c) It has no clock input
Explanation: Flip-flop is a modified d) Invalid State
version of latch. To determine the
Answer: d
changes in states, an additional
Explanation: The main drawback of s-
control input is provided to the latch.
r flip flop is invalid output when both
32. How many types of flip-flops are? the inputs are high, which is referred
a) 2 to as Invalid State.
b) 3
35. One example of the use of an S-R
c) 4
flip-flop is as
d) 5
a) Racer
Answer: c b) Stable oscillator
Explanation: There are 4 types of flip- c) Binary storage register
flops, viz., S-R, J-K, D, and T. D flip- d) Transition pulse generator
flop is an advanced version of S-R flip-
Answer: c
flop, while T flip-flop is an advanced
Explanation: S-R refers to set-reset.
version of J-K flip-flop.
So, it is used to store two values 0
33. The S-R flip flop consist of and 1. Hence, it is referred to as
binary storage element. It functions
a) 4 AND gates as memory storage during the No
b) Two additional AND gates Change State.
c) An additional clock input
d) 3 AND gates

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36. When is a flip-flop said to be triggered when the transition takes

transparent? place from high to low.
a) When the Q output is opposite the
38. A group of bits used to represent
input
a symbol is called a
b) When the Q output follows the
a) byte
input
b) memory
c) When you can see through the IC
c) nibble
packaging
d) code
d) When the Q output is
complementary of the input Answer: a
Explanation: In binary coding, every
Answer: b
symbol that appears in data is
Explanation: Flip-flop have the
represented by a group of bits, which
property of responding immediately
are called bytes. Computer codes use
to the changes in its inputs. This
binary coding schemes.
property is called transparency.
39. BCD uses 6 bits to represent a
37. On a positive edge-triggered S-R
symbol.
flip-flop, the outputs reflect the input
a) True
condition when
b) False
a) The clock pulse is LOW
b) The clock pulse is HIGH Answer: a
c) The clock pulse transitions from Explanation: In a Binary Coded
LOW to HIGH Decimal format, 64 characters i.e. 26
d) The clock pulse transitions from different characters can be
HIGH to LOW represented. It is one of the early
computer codes.
Answer: c
Explanation: Edge triggered device 40. Which of the following is not a
will follow when there is transition. It type of computer code?
is a positive edge triggered when a) EBCDIC
transition takes place from low to b) BCD
high, while, it is negative edge

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c) ASCII Answer: b
d) EDIC Explanation: To add any two BCD
numbers :
Answer: d
Simply perform the addition :
Explanation: There is no coding
23+20=43.
scheme like EDIC. EBCDIC stands for
Then, write the equivalent BCD
Extended Binary Coded Decimal
number = (0100 0011)BCD.
Interchange Code. BCD stands for
Binary Coded Decimal. ASCII stands 43. The weights used in Binary coded
for American Standard Code for decimal code are:
information interchange. a) 4,2,1
b) 8,4,2,1
41. The BCD representation of
c) 6,4,2,1
(34)10 is
d) 2,1
a) 6
b) 7 Answer: b
c) 8 Explanation: BCD is a weighted code
d) 5 and it uses the weights 8,4,2,1
respectively. It is often called the
Answer: b
8421 code. Since, it uses 4 bits for the
Explanation: BCD numbers are
representation therefore the weights
represented as:
are assigned as : 23 = 8, 22 = 4, 21 = 2,
34 = (0011 0100)BCD.
20 = 1.
Each digit is individually taken and an
equivalent standard 4 bit term is 44. Write the decimal equivalent for
written for the respective digit. (110001)BCD.
a) 31
42. Perform BCD addition of (23)BCD +
b) 13
(20)BCD .
c) C1
a) 00110100
d) 1C
b) 01000011
c) 10011 Answer: a
d) 11100 Explanation: To obtain the decimal
equivalent :

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We start from the rightmost bit and a) 0110

make groups of 4, then write the b) 1110
decimal equivalent accordingly. c) 0111
0011 0001 = (31)10. d) 1100

45. The 9‟s complement of 45 is Answer: c

Explanation: The excess-3 code is
a) 45 obtained by adding 3 to the BCD
b) 54 code.
c) 64 Here, 0100+0011=0111.
d) 46 Also, 4+3=7.
Answer: b 48. What is the hold condition of a
Explanation: The 9‟s complement of a flip-flop?
number is obtained by subtracting a) Both S and R inputs activated
each digit from 9. Here, 99-45=54. b) No active S or R input
Therefore, the 9‟s complement is 54. c) Only S is active
d) Only R is active
46. The 10‟s complement of 455 is
Answer: b
a) 543 Explanation: The hold condition in a
b) 544 flip-flop is obtained when both of the
c) 545 inputs are LOW. It is the No Change
d) 546 State or Memory Storage state if a
Answer: c flip-flop.
Explanation: To obtain the 10‟s 49. If an active-HIGH S-R latch has a 0
complement, we first obtain the 9‟s on the S input and a 1 on the R input
complement and then add 1 to it. and then the R input goes to 0, the
999-455=544 (9‟s) latch will be
544+1=545(10‟s). a) SET
47. The Excess-3 representation of b) RESET
(0100)BCD is c) Clear
d) Invalid

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Answer: b
Explanation: If S=0, R=1, the flip flop
is at reset condition. Then at S=0,
R=0, there is no change. So, it
remains in reset. If S=1, R=0, the flip
flop is at the set condition.

50. The circuit that is primarily

responsible for certain flip-flops to be
designated as edge-triggered is the

a) Edge-detection circuit
b) NOR latch
c) NAND latch
d) Pulse-steering circuit

Answer: a
Explanation: The circuit that is
primarily responsible for certain flip-
flops to be designated as edge-
triggered is the edge-detection
circuit.

51. The output of a logic gate is 1

when all the input are at logic 0 as
shown below: The gate is either
a) A NAND or an EX-OR
INPUT OUTPUT b) An OR or an EX-NOR
c) An AND or an EX-OR
A B C d) A NOR or an EX-NOR

Answer: d
Explanation: The output of a logic

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gate is 1 when all inputs are at logic decoder:

0. The gate is NOR. The output of a f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2,
logic gate is 1 when all inputs are at 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
logic 0 or all inputs are at logic 1, then The minimum configuration of
it is EX-NOR. (The truth tables for decoder will be
NOR and EX-NOR Gates are shown in a) 2 to 4 line
above table). b) 3 to 8 line
c) 4 to 16 line
52. The code where all successive
d) 5 to 32 line
numbers differ from their preceding
number by single bit is Answer: c
a) Alphanumeric Code Explanation: 4 to 16 line decoder as
b) BCD the minterms are ranging from 1 to
c) Excess 3 14.
d) Gray
54. How many AND gates are
Answer: d required to realize Y = CD + EF + G?
Explanation: The code where all a) 4
successive numbers differ from their b) 5
preceding number by single bit is gray c) 3
code. It is an unweighted code. The d) 2
most important characteristic of this
Answer: d
code is that only a single bit change
Explanation: To realize Y = CD + EF +
occurs when going from one code
G, two AND gates are required and
number to next. BCD Code is one in
two OR gates are required.
which decimal digits are represented
by a group of 4-bits each, whereas, in 55. The NOR gate output will be high
Excess-3 Code, the decimal numbers if the two inputs are
are incremented by 3 and then a) 00
written in their BCD format. b) 01
c) 10
53. The following switching functions
d) 11
are to be implemented using a

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Answer: a function and are thus Universal Logic

Explanation: In 01, 10 or 11 output is Gates.
low if any of the I/P is high. So, the
58. A full adder logic circuit will have
correct option will be 00.

56. How many two-input AND and OR a) Two inputs and one output
gates are required to realize Y = b) Three inputs and three outputs
CD+EF+G? c) Two inputs and two outputs
a) 2, 2 d) Three inputs and two outputs
b) 2, 3
Answer: d
c) 3, 3
Explanation: A full adder circuit will
d) 3, 2
add two bits and it will also accounts
Answer: a the carry input generated in the
Explanation: Y = CD + EF + G previous stage. Thus three inputs and
The number of two input AND gate = two outputs (Sum and Carry) are
2 there. In case of half adder circuit,
The number of two input OR gate = 2. there are only two inputs bits and
two outputs (SUM and CARRY).
57. A universal logic gate is one which
can be used to generate any logic 59. How many two input AND gates
function. Which of the following is a and two input OR gates are required
universal logic gate? to realize Y = BD + CE + AB?
a) OR a) 3, 2
b) AND b) 4, 2
c) XOR c) 1, 1
d) NAND d) 2, 3

Answer: d Answer: a
Explanation: An Universal Logic Gate Explanation: There are three product
is one which can generate any logic terms. So, three AND gates of two
function and also the three basic inputs are required. As only two input
gates: AND, OR and NOT. Thus, NOR OR gates are available, so two OR
and NAND can generate any logic

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gates are required to get the logical 62. The CISC stands for
sum of three product terms. a) Computer Instruction Set
Compliment
60. Which of following are known as
b) Complete Instruction Set
universal gates?
Compliment
a) NAND & NOR
c) Computer Indexed Set
b) AND & OR
Components
c) XOR & OR
d) Complex Instruction set computer
d) EX-NOR & XOR
Answer: d
Answer: a
Explanation: CISC is a computer
Explanation: The NAND & NOR gates
architecture where in the processor
are known as universal gates because
performs more complex operations in
any digital circuit can be realized
one step.
completely by using either of these
two gates, and also they can generate 63. The computer architecture aimed
the 3 basic gates AND, OR and NOT. at reducing the time of execution of
instructions is
61. The gates required to build a half
a) CISC
adder are
b) RISC
a) EX-OR gate and NOR gate
c) ISA
b) EX-OR gate and OR gate
d) ANNA
c) EX-OR gate and AND gate
d) EX-NOR gate and AND gate Answer: b
Explanation: The RISC stands for
Answer: c
Reduced Instruction Set Computer.
Explanation: The gates required to
build a half adder are EX-OR gate and 3. The Sun micro systems processors
AND gate. EX-OR outputs the SUM of usually follow architecture.
the two input bits whereas AND a) CISC
outputs the CARRY of the two input b) ISA
bits. c) ULTRA SPARC
d) RISC

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Answer: d c) Semantic gap

Explanation: The Risc machine aims d) All of the mentioned
at reducing the instruction set of the
Answer: c
computer.
Explanation: The semantic gap is the
64. The RISC processor has a more gap between the high level language
complicated design than CISC. and the low level language.
a) True
67. Out of the following which is not
b) False
a CISC machine.
Answer: b a) IBM 370/168
Explanation: The RISC processor b) VAX 11/780
design is more simpler than CISC and c) Intel 80486
it consists of fewer transistors. d) Motorola A567

65. The iconic feature of the RISC Answer: d

machine among the following is Explanation: None.

68. Pipe-lining is a unique feature of

a) Reduced number of addressing
modes
a) RISC
b) Increased memory size
b) CISC
c) Having a branch delay slot
c) ISA
d) All of the mentioned
d) IANA
Answer: c
Answer: a
Explanation: A branch delay slot is an
Explanation: The RISC machine
instruction space immediately
architecture was the first to
following a jump or branch.
implement pipe-lining.
66. Both the CISC and RISC
69. In CISC architecture most of the
architectures have been developed to
complex instructions are stored in
reduce the
a) Cost
a) Register
b) Time delay
b) Diodes

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c) CMOS 72. An HTML file is a text file

d) Transistors containing small markup tags.
a) True
Answer: d
b) False
Explanation: In CISC architecture
more emphasis is given on the Answer: a
instruction set and the instructions Explanation: The statement is true.
take over a cycle to complete. HTML stands for Hyper Text Markup
Language. It is a text file containing
70. Which of the architecture is
small markup tags.
power efficient?
a) CISC 73. Secondary memory is the long
b) RISC term store for programs and data
c) ISA while main memory holds program
d) IANA and data currently in use. What kind
of an organization is this?
Answer: b
a) Physical
Explanation: Hence the RISC
b) Logical
architecture is followed in the design
c) Structural
of mobile devices.
d) Simple
71. A task carried out by the OS and
Answer: a
hardware to accommodate multiple
Explanation: The secondary memory
processes in main memory.
is the long term store for programs
a) Memory control
and data while main memory holds
b) Memory management
program and data currently in use.
c) Memory sharing
This is a physical organization.
d) Memory usage
74. Memory organization in which
Answer: b
users write programs in modules with
Explanation: Memory management is
different characteristics.
carried out by the OS and hardware
a) Physical
to accommodate multiple processes
b) Logical
in main memory.

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c) Structural Transfer Protocol. It is a type of

d) Simple internet service use for the
transmission of files.
Answer: b
Explanation: The answer is Logical. To 77. A set of overlapping divisions in
handle user programs properly, the the main memory are called
operating system and the hardware a) Partitions
should support a basic form of b) Divisions
module to provide protection and c) Blocks
sharing. d) Modules

75. An executing process must be Answer: a

loaded entirely in main memory. Explanation: Partition main memory
What kind of a memory organization into a set of non overlapping regions
is this? called partitions. Partitions can be of
a) Physical equal or unequal sizes.
b) Logical
78. Any program, no matter how
c) Structural
small, occupies an entire partition.
d) Simple
This is called
Answer: d a) fragmentation
Explanation: This is simple memory b) prior fragmentation
organisation. An executing process c) internal fragmentation
must be loaded entirely in main d) external fragmentation
memory (if overlays are not used).
Answer: c
76. FTP stands for? Explanation: It is called as internal
a) File Text Protocol fragmentation. Main memory use is
b) File Transfer Protocol inefficient. Any program, no matter
c) Firm Transfer Protocol how small, occupies an entire
d) File Transplant Protocol partition. This is called internal
fragmentation.
Answer: b
Explanation: FTP stands for File

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79. _ is used to shift Answer: d

processes so they are contiguous and Explanation: When a person walks
all free memory is in one block. across a carpeted or tile floor electric
a) Fragmentation charge builds up in the body due to
b) Compaction the friction between shoes and floor
c) External Fragmentation material. If the friction static is
d) Division greater the voltage potential develop
in the body will be greater. You start
Answer: b
act as a capacitor. This is called
Explanation: Use compaction to shift
Electrostatic discharge. The potential
processes so they are contiguous and
static charge that can develop from
all free memory is in one block.
walking on tile floors is greater than
80. searches for smallest 15000 volts while carpeted floors can
block. The fragment left behind is generate in excess of 30000 volts.
small as possible.
82. What must be done to interface
a) best fit
TTL to CMOS?
b) first fit
a) A dropping resistor must be used
c) next fit
on the CMOS of 12 V supply to
d) last fit
reduce it to 5 V for the TTL
Answer: a b) As long as the CMOS supply
Explanation: Best fit searches for the voltage is 5 V they can be interfaced
smallest block. The fragment left (however, the fan-out of the TTL is
behind is as small as possible. limited to five CMOS gates)
c) A 5 V zener diode must be placed
81. What is the static charge that can
across the inputs of the TTL gates in
be stored by your body as you walk
order to protect them from the
across a carpet?
higher output voltages of the CMOS
a) 300 volts
gates
b) 3000 volts
d) A pull-up resistor must be used
c) 30000 volts
between the TTL output-CMOS input
d) Over 30000 volts
node and Vcc; the value of RP will

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depend on the number of CMOS and temperatures

gates connected to the node b) The 5400 series are military grade
and allow for a wider range of supply
Answer: d
voltages and temperatures
Explanation: To interface TTL to
c) The 7400 series are an
CMOS a pull-up resistor must be used
improvement over the original 5400s
between the TTL output-CMOS input
d) The 7400 series was originally
node and Vcc. A pull-up resistor is
developed by Texas Instruments and
used to avoid the floating state on
the 5400 series was brought out by
the input node of the CMOS, thus
National Semiconductors after TI‟s
using a small amount of current. The
patents expired as a second supply
value of RP will depend on the
source
number of CMOS gates connected to
the node. Answer: b
Explanation: The 5400 series are
83. What causes low-power Schottky
military grade and allow for a wider
TTL to use less power than the 74XX
range of supply voltages and
series TTL?
temperatures, these are the major
a) The Schottky-clamped transistor
differences between the 5400 and
b) A larger value resistor
7400 series of ICs. Also, the working
c) The Schottky-clamped MOSFET
temperature range of 5400 series is -
d) A small value resistor
50 to 125C while that for 7400 is 0 to
Answer: b 70C.
Explanation: A larger value resistor
85. Which of the following
causes low power low-power
statements apply to CMOS devices?
Schottky TTL to use less power than
a) The devices should not be inserted
the 74XX series TTL.
into circuits with the power on
84. What are the major differences b) All tools, test equipment and metal
between the 5400 and 7400 series of workbenches should be tied to earth
ICs? ground
a) The 5400 series are military grade c) The devices should be stored and
and require tighter supply voltages shipped in antistatic tubes or

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conductive foam Answer: a

d) All of the Mentioned Explanation: The control unit is
referred to as the central nervous
Answer: d
system because it selects and
Explanation: For CMOS devices, all
interprets the instructions and
the mentioned statements are
coordinates execution.
applicable. The devices should not be
inserted into circuits with the power 88. What does MBR stand for?
on. All tools, test equipment and a) Main Buffer Register
metal workbenches should be tied to b) Memory Buffer Routine
earth ground. Also, the devices c) Main Buffer Routine
should be stored and shipped in d) Memory Buffer Register
antistatic tubes or conductive foam.
Answer: d
86. Brain of computer is Explanation: The binary subtraction 0
– 1 gives the result 1.
a) Control unit A borrow of 1 is although generated
b) Arithmetic and Logic unit and is removed from the next higher
c) Central Processing Unit column.
d) Memory
89. In the instruction ADD A, B, the
Answer: c answer gets stored in
Explanation: The CPU is referred to as a) B
the brain of a computer. b) A
It consists of a control unit and the c) Buffer
arithmetic and logic unit. It is d) C
responsible for performing all the
Answer: b
processes and operations.
Explanation: In any instruction of the
87. Control Unit acts as the central form ADD A, B; the answer gets
nervous system of the computer. stored in the A register. The format
a) True is: ADD Destination, Source.
b) False

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90. What is the high speed memory Answer: a

between the main memory and the Explanation: Whenever the data is
CPU called? found in the cache memory, it is
a) Register Memory called as Cache HIT. CPU first checks
b) Cache Memory in the cache memory since it is
c) Storage Memory closest to the CPU.
d) Virtual Memory
93. LRU stands for
Answer: b a) Low Rate Usage
Explanation: It is called the Cache b) Least Rate Usage
Memory. The cache memory is the c) Least Recently Used
high speed memory between the d) Low Required Usage
main memory and the CPU.
Answer: c
91. Cache Memory is implemented Explanation: LRU stands for Least
using the DRAM chips. Recently Used. LRU is a type of
a) True replacement policy used by the cache
b) False memory.

Answer: b 94. When the data at a location in

Explanation: The Cache memory is cache is different from the data
implemented using the SRAM chips located in the main memory, the
and not the DRAM chips. SRAM cache is called
stands for Static RAM. It is faster and a) Unique
is expensive. b) Inconsistent
c) Variable
92. Whenever the data is found in the
d) Fault
cache memory it is called as
Answer: b
a) HIT Explanation: The cache is said to be
b) MISS inconsistent. Inconsistency must be
c) FOUND avoided as it leads to serious data
d) ERROR bugs.

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95. Which of the following is not a Answer: d

write policy to avoid Cache Explanation: The IR which stands for
Coherence? the instruction register contains the
a) Write through last instruction fetched.
b) Write within All the others options are registers
c) Write back which are used for the fetch
d) Buffered write operation.

Answer: b 98. The portion of the processor

Explanation: There is no policy which which contains the hardware
is called as the write within policy. required to fetch the operations is
The other three options are the write
policies which are used to avoid a) Datapath
cache coherence. b) Processor
c) Control
96. What does PC stand for?
d) Output unit
a) Program Changer
b) Program Counter Answer: a
c) Performance Counter Explanation: The datapath contains
d) Performance Changer the hardware required to fetch the
operations. The control tells the data
Answer: b
path what needs to be done.
Explanation: The Program counter
contains the address of the next 99. Causing the CPU to step through a
instruction which is to be fetched by series of micro operations is called
the control unit.
All other options are invalid. a) Execution
b) Runtime
97. Which of the following holds the
c) Sequencing
last instruction fetched?
d) Pipelining
a) PC
b) MAR Answer: c
c) MBR Explanation: Sequencing is the
d) IR process of causing the CPU to step

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through a series of micro operations. 102. All input of NOR as low produces
Execution causes the performance of result as
each micro operation. a) Low
b) Mid
100. The functions of execution and
c) High
sequencing are performed by using
d) Floating
a) Input Signals Answer: c
b) Output Signals Explanation: All input of NOR as low
c) Control Signals produces the result as high, whereas,
d) CPU rest all conditions produce output as
low.
Answer: c
Explanation: Sequencing followed by 103. What is a multiplexer?
the process of execution is performed a) It is a type of decoder which
by the Control signals. Sequencing is decodes several inputs and gives one
traversing each and every operation output
whereas execution causes the b) A multiplexer is a device which
performance of each operation. converts many signals into one
c) It takes one input and results into
101. What does D in the D-flip flop
many output
stand for?
d) It is a type of encoder which
a) Digital
decodes several inputs and gives one
b) Direct
output
c) Delay
d) Durable Answer: b
Explanation: A multiplexer (or MUX)
Answer: c
is a device that selects one of several
Explanation: In the hardwired control
analog or digital input signals and
unit, the delay element method uses
forwards the selected input into a
D-flip flop which causes a delay.
single line, depending on the active
Since, in the delay element method,
select lines.
there must be a finite time gap
between the 2 steps.

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104. Which combinational circuit is the digital multiplexer with the

renowned for selecting a single input proficiency of large number of inputs.
from multiple inputs & directing the
106. Which is the major functioning
binary information to output line?
responsibility of the multiplexing
a) Data Selector
combinational circuit?
b) Data distributor
a) Decoding the binary information
c) Both data selector and data
b) Generation of all minterms in an
distributor
output function with OR-gate
d) DeMultiplexer
c) Generation of selected path
Answer: a between multiple sources and a
Explanation: Data Selector is another single destination
name of Multiplexer. A multiplexer d) Encoding of binary information
(or MUX) is a device that selects one
Answer: c
of several analog or digital input
Explanation: The major functioning
signals and forwards the selected
responsibility of the multiplexing
input into a single line, depending on
combinational circuit is generation of
the active select lines.
selected path between multiple
105. It is possible for an enable or sources and a single destination
strobe input to undergo an expansion because it makes the circuit too
of two or more MUX ICs to the digital flexible. A multiplexer (or MUX) is a
multiplexer with the proficiency of device that selects one of several
large number of analog or digital input signals and
a) Inputs forwards the selected input into a
b) Outputs single line, depending on the active
c) Selection lines select lines.
d) Enable lines
107. What is the function of an
Answer: a enable input on a multiplexer chip?
Explanation: It is possible for an a) To apply Vcc
enable or strobe input to undergo an b) To connect ground
expansion of two or more MUX ICs to

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c) To active the entire chip Binary as the word suggests contains

d) To active one half of the chip only 2 digits : 0 and 1.
0 denotes false and 1 denotes a truth
Answer: c
value.
Explanation: Enable input is used to
active the chip, when enable is high 110. The contains the
the chip works (ACTIVE), when enable address of the next instruction to be
is low the chip does not work executed.
(MEMORY). However, Enable can be a) IR
Active-High or Active-Low, indicating b) PC
it is active either when it is connected c) Accumulator
to VCC or GND respectively. d) System counter

108. The language made up of binary Answer: b

coded instructions. Explanation: PC stands for program
a) Machine counter (It contains the address of
b) C the next instruction to be executed).
c) BASIC
111. The memory unit is made up of
d) High level
bytes.
Answer: a a) 256
Explanation: The language made up b) 124
of binary coded instructions built into c) 4096
the hardware of a particular d) 3096
computer and used directly by the
Answer: c
computer is machine language.
Explanation: The memory unit is
109. Binary code comprises of digits made up of 4,096 bytes. Memory unit
from 0 to 9. is responsible for the storage of data.
a) True It is an important entity in the
b) False computer system.

Answer: b 112. A document that specifies how

Explanation: The statement is false. many times and with what data the

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program must be run in order to c) program

thoroughly test it. d) semantics
a) addressing plan
Answer: b
b) test plan
Explanation: Syntax determines the
c) validation plan
grammatical rules in a code.
d) verification plan
Semantics give meaning to the
Answer: b instructions.
Explanation: Test plan is the A
115. A program that reads each of
document that specifies how many
the instructions in mnemonic form
times and with what data the
and translates it into the machine-
program must be run in order to
language equivalent.
thoroughly test it. It comes under
a) Machine language
testing.
b) Assembler
113. An approach that designs test c) Interpreter
cases by looking at the allowable data d) C program
values.
Answer: b
a) Maintenance
Explanation: Assembler does this job.
b) Evaluation
A language that uses mnemonic
c) Data coverage
codes for the representation of
d) Validation
machine-language instructions is
Answer: c called assembly language.
Explanation: Data coverage is the
116. An approach that designs test
term used. It is responsible for
cases by looking at the allowable data
designing the test cases.
values.
114. The formal grammar rules a) Data coverage
governing the construction of valid b) Code Coverage
instruction. c) Debugging
a) test case d) Validation
b) syntax

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Answer: a forwards the selected input into a

Explanation: Data coverage is an single line, depending on the active
approach that designs test cases by select lines. Since many operational
looking at the allowable data values. behaviour can be performed by using
Code coverage is an approach that a multiplexer. Whereas, a
designs test cases by looking at the combinational circuit is a
code. combination of many logic gates
which makes the circuit more
117. The rules that give meaning to
complex.
the instructions.
a) Semantics 119. A digital multiplexer is a
b) Syntax combinational circuit that selects
c) Code
d) Cases a) One digital information from
several sources and transmits the
Answer: a
selected one
Explanation: The answer is semantics.
b) Many digital information and
They are the rules that give meaning
convert them into one
to the instructions. The syntax is the
c) Many decimal inputs and transmits
formal rules that ensure validation of
the selected information
code.
d) Many decimal outputs and accepts
118. One multiplexer can take the the selected information
place of
Answer: a
a) Several SSI logic gates
Explanation: A digital multiplexer is a
b) Combinational logic circuits
combinational circuit that selects one
c) Several Ex-NOR gates
digital information from several
d) Several SSI logic gates or
sources and transmits the selected
combinational logic circuits
information on a single output line
Answer: d depending on the status of the select
Explanation: A multiplexer (or MUX) lines. That is why it is also known as a
is a device that selects one of several data selector.
analog or digital input signals and

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120. In a multiplexer, the selection of b) 4

a particular input line is controlled by c) 8
d) 3
a) Data controller
Answer: d
b) Selected lines
Explanation: 2n input lines, n control
c) Logic gates
lines and 1 output line available for
d) Both data controller and selected
MUX. Here, 8 input lines mean
lines
23 inputs. So, 3 control lines are
Answer: b possible. Depending on the status of
Explanation: The selection of a the select lines, the input is selected
particular input line is controlled by a and fed to the output.
set of selected lines in a multiplexer,
123. A basic multiplexer principle can
which helps to select a particular
be demonstrated through the use of
input from several sources.
a
121. If the number of n selected input a) Single-pole relay
lines is equal to 2^m then it requires b) DPDT switch
select lines. c) Rotary switch
a) 2 d) Linear stepper
b) m
Answer: c
c) n
Explanation: A basic multiplexer
d) 2n
principle can be demonstrated
Answer: b through the use of a rotary switch.
Explanation: If the number of n Since its behaviour is similar to the
selected input lines is equal to 2^m multiplexer. There are around 10
then it requires m select lines to digits out of which one is selected
select one of m select lines. one at a time and fed to the output.
122. How many select lines would be 124. How many NOT gates are
required for an 8-line-to-1-line required for the construction of a 4-
multiplexer? to-1 multiplexer?
a) 2 a) 3

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b) 4
c) 2 a) X0
d) 5 b) X1
c) X2
Answer: c
d) X3
Explanation: There are two NOT gates
required for the construction of 4-to- Answer: b
1 multiplexer. x0, x1, x2 and x3 are Explanation: The output will be X1,
the inputs and C1 and C0 are the because c1 = 0 and c0 = 1 results into
select lines and M is the output. 1 which further results as X1. And
The diagram of a 4-to-1 multiplexer is rest of the AND gates gives output as
shown 0.
below:
126. The enable input is also known
as
a) Select input
b) Decoded input
c) Strobe
d) Sink

Answer: c
Explanation: The enable input is also
125. In the given 4-to-1 multiplexer, if known as strobe which is used to
c1 = 0 and c0 = 1 then the output M is cascade two or more multiplexer ICs
to construct a multiplexer with a
larger number of inputs. Enable input
activates the multiplexer to operate.

127. Execution of several activities at

the same time.
a) processing
b) parallel processing
c) serial processing
d) multitasking

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Answer: b c) Serial processing

Explanation: Execution of several d) Distribution
activities at the same time is referred
Answer: b
to as parallel processing. Like, Two
Explanation: Parallelism leads
multiplications at the same time on 2
naturally to Concurrency. For
different processes.
example, Several processes trying to
128. Parallel processing has single print a file on a single printer.
execution flow.
131. A parallelism based on
a) True
increasing processor word size.
b) False
a) Increasing
Answer: b b) Count based
Explanation: The statement is false. c) Bit based
Sequential programming specifically d) Bit level
has single execution flow.
Answer: d
129. A term for simultaneous access Explanation: Bit level parallelism is
to a resource, physical or logical. based on increasing processor word
a) Multiprogramming size. It focuses on hardware
b) Multitasking capabilities for structuring.
c) Threads
132. A type of parallelism that uses
d) Concurrency
micro architectural techniques.
Answer: d a) instructional
Explanation: Concurrency is the term b) bit level
used for the same. When several c) bit based
things are accessed simultaneously, d) increasing
the job is said to be concurrent.
Answer: a
130. leads to Explanation: Instructional level uses
concurrency. micro architectural techniques. It
a) Serialization focuses on program instructions for
b) Parallelism structuring.

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133. MIPS stands for? Answer: a

a) Mandatory Instructions/sec Explanation: Isoefficiency is the rate
b) Millions of Instructions/sec at which the problem size need to be
c) Most of Instructions/sec increased to maintain efficiency.
d) Many Instructions / sec
136. Several instructions execution
Answer: b simultaneously in
Explanation: MIPS stands for Millions a) processing
of Instructions/sec. MIPS is a way to b) parallel processing
measure the cost of computing. c) serial processing
d) multitasking
134. The measure of the “effort”
needed to maintain efficiency while Answer: b
adding processors. Explanation: In parallel processing,
a) Maintainablity the several instructions are executed
b) Efficiency simultaneously.
c) Scalabilty
137. How many inputs will a decimal-
d) Effectiveness
to-BCD encoder have?
Answer: c a) 4
Explanation: The measure of the b) 8
“effort” needed to maintain c) 10
efficiency while adding processors is d) 16
called as scalabilty.
Answer: c
135. The rate at which the problem Explanation: An encoder is a
size need to be increased to maintain combinational circuit encoding the
efficiency. information of 2n input lines to n
a) Isoeffciency output lines, thus producing the
b) Efficiency binary equivalent of the input. Thus,
c) Scalabilty a Decimal-to-bcd converter has
d) Effectiveness decimal values as inputs which range
from 0-9. So, total 10 inputs are there
in a decimal-to-BCD encoder.

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138. How many outputs will a performs the opposite operation of a

decimal-to-BCD encoder have? decoder which results in 2n outputs
a) 4 from n inputs. Thus, an encoder
b) 8 different from a decoder because of
c) 12 the output of an encoder is a binary
d) 16 code for 1-of-N input.

Answer: a 140. The full form of ROM is

Explanation: An encoder is a
combinational circuit encoding the a) Read Outside Memory
information of 2n input lines to n b) Read Out Memory
output lines, thus producing the c) Read Only Memory
binary equivalent of the input. Thus, d) Read One Memory
a decimal to BCD encoder has 4
Answer: c
outputs.
Explanation: The full form of ROM is
139. How is an encoder different Read Only Memory.
from a decoder?
141. ROM consist of
a) The output of an encoder is a
a) NOR and OR arrays
binary code for 1-of-N input
b) NAND and NOR arrays
b) The output of a decoder is a binary
c) NAND and OR arrays
code for 1-of-N input
d) NOR and AND arrays
c) The output of an encoder is a
binary code for N-of-1 output Answer: c
d) The output of a decoder is a binary Explanation: ROM consists of NAND
code for N-of-1 output and OR arrays which can be
programmed by the user to
Answer: a
implement combinational &
Explanation: An encoder is a
sequential functions. Combinational
combinational circuit encoding the
Operations like that of adders and
information of 2n input lines to n
subtractors and Sequential Functions
output lines, thus producing the
like that of storing in the memory.
binary equivalent of the input. It

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142. For reprogrammability, PLDs use Memory

c) Eradicate Programmable Read Only
a) PROM Memory
b) EPROM d) Easy Programmable Read Out
c) CDROM Memory
d) PLA
Answer: b
Answer: b Explanation: The full form of EPROM
Explanation: For reprogrammability, is Erasable Programmable Read Only
PLDs use EPROM (i.e. Erasable Memory, where the ROM can be
PROM). It erases the previous erased and re-used by the user.
program and starts uploading a new
145. PLDs with programmable AND
one. However, data is erased by
and fixed OR arrays are called
exposing it to UV-light, which is a
tedious and time-consuming process.
a) PAL
143. The full form of PROM is b) PLA
c) APL
a) Previous Read Only Memory d) PPL
b) Programmable Read Out Memory
Answer: a
c) Programmable Read Only Memory
Explanation: PLDs with
d) Previous Read Out Memory
programmable AND and fixed OR
Answer: c arrays are called PAL (i.e.
Explanation: The full form of PROM is Programmable Array Logic).
Programmable Read Only Memory, However, PAL is less flexible but has
where the ROM can be programmed higher speed.
by the user.
146. When both the AND and OR are
144. The full form of EPROM is programmable, such PLDs are known
as
a) Easy Programmable Read Only a) PAL
Memory b) PPL
b) Erasable Programmable Read Only

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c) PLA Answer: b
d) APL Explanation: The programmability
and high density of PLDs make them
Answer: c
useful in the design of ASIC (i.e.
Explanation: When both the AND and
Application Specific Integrated
OR are programmable, such PLDs are
Circuits) where design changes can
known as PLA (i.e. Programmable
be more rapidly and inexpensively.
Logic Array). However, PLA is more
flexible but has less speed. 149. FPGA stands for
a) Full Programmable Gate Array
147. ASIC stands for
b) Full Programmable Genuine Array
a) Application Special Integrated
c) First Programmable Gate Array
Circuits
d) Field Programmable Gate Array
b) Applied Special Integrated Circuits
c) Application Specific Integrated Answer: d
Circuits Explanation: In digital electronics,
d) Applied Specific Integrated Circuits FPGA stands for Field Programmable
Answer: c Gate Array. This type of integrated
Explanation: In digital electronics, circuit is for general-purpose which is
ASIC stands for Application Specific configured by the user as per their
Integrated Circuits. It is a customized requirement.
integrated circuit which is produced
150. Which of the following is a
for a specific use and not for a
reprogrammable gate array?
common-purpose.
a) EPROM
148. The programmability and high b) FPGA
density of PLDs make them useful in c) Both EPROM and FPGA
the design of d) ROM
a) ISAC
Answer: c
b) ASIC
Explanation: Both FPGA and EPROM
c) SACC
are reprogrammable gate array.
d) CISF

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151. The difference between FPGA 153. Can an encoder be a transducer?

and PLD is that a) Yes
a) FPGA is slower than PLD b) No
b) FPGA has high power dissipation c) May or may not be
c) FPGA incorporates logic blocks d) Both are not even related slightly
d) All of the Mentioned
Answer: a
Answer: c Explanation: Of course, a transducer
Explanation: The differences between is a device which has the capability to
FPGA and PLD is that FPGA emit data as well as to accept.
incorporates logic blocks instead of Transducer converts signal from one
fixed AND-OR gates and is faster with form of energy to another.
low power dissipation. FPGAs are
154. How many OR gates are
designed for having higher gate count
required for a Decimal-to-bcd
whereas, PLDs are used for lesser
encoder?
gate counts.
a) 2
152. If we record any music in any b) 10
recorder, such types of process is c) 3
called d) 4
a) Multiplexing
Answer: d
b) Encoding
Explanation: An encoder is a
c) Decoding
combinational circuit encoding the
d) Demultiplexing
information of 2^n input lines to n
Answer: b output lines, thus producing the
Explanation: If we record any music in binary equivalent of the input.
any recorder, it means that we are This is clear from the diagram that it
giving data to a recorder. So, such requires 4 OR gates:
process is called encoding. Getting
back the music from the recorded
data, is known as decoding.

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Since, a part of the program needs to

be in memory for the process of
execution, the logical space can
therefore be much larger than the
physical address space.

157. Virtual Memory can be

implemented via
a) Demand Paging
b) Logical paging
. c) Structural way
d) Simple division
155. Separation of user logical
memory and physical memory is Answer: a
Explanation: Demand paging can
a) Memory control implement virtual memory. Another
b) Memory management way is demand segmentation.
c) Memory sharing 158. COW stands for?
d) Virtual memory a) Copy over write
Answer: d b) Convert over write
Explanation: The separation of user c) Count over write
logical memory and physical memory d) Copy over write
is called virtual memory. Only part of Answer: d
the program needs to be in memory Explanation: COW stands for Copy
for execution. over write. COW allows both parent
156. Logical Address space can be and child processes to share the
larger than physical address space. same pages initially.
a) True 159. LRU stands for?
b) False a) Least Recently used
Answer: a b) Less Recently used
Explanation: The statement is true.

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c) Least Recurrently used process can take a frame from

d) Least Randomly used another.

Answer: a 162. How many OR gates are

Explanation: LRU stands for Least required for an octal-to-binary
Recently used. LRU is least recently encoder?
used. It replaces page with the a) 3
smallest count. b) 2
c) 8
160. An allocation that uses a
d) 10
proportional allocation scheme using
priorities rather than size. Answer: a
a) Priority allocation Explanation: An encoder is a
b) File allocation combinational circuit encoding the
c) Preference allocation information of 2n input lines to n
d) Simple allocation output lines, thus producing the
binary equivalent of the input. Thus,
Answer: a
in octal to binary encoder there are 8
Explanation: Priority allocation uses a
(=23) inputs, thus 3 output lines.
proportional allocation scheme using
priorities rather than size. 163. For 8-bit input encoder how
many combinations are possible?
161. A process selects a replacement
a) 8
frame from the set of all frames.
b) 2^8
a) Local replacement
c) 4
b) Global replacement
d) 2^4
c) Block replacement
d) Module replacement Answer: b
Explanation: An encoder is a
Answer: b
combinational circuit encoding the
Explanation: Global replacement
information of 2n input lines to n
process selects a replacement frame
output lines, thus producing the
from the set of all frames; one
binary equivalent of the input. There
are 28 combinations are possible for

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an 8-bit input encoder but out of without a single output line and
which only 8 are used using 3 output without any selection lines.
lines. It is a disadvantage of encoder.
166. If two inputs are active on a
164. The discrepancy of 0 output due priority encoder, which will be coded
to all inputs being 0 or D0, being 0 is on the output?
resolved by using additional input a) The higher value
known as b) The lower value
a) Enable c) Neither of the inputs
b) Disable d) Both of the inputs
c) Strobe
Answer: a
d) Clock
Explanation: An encoder is a
Answer: a combinational circuit encoding the
Explanation: Such problems are information of 2n input lines to n
resolved by using enable input, which output lines, thus producing the
behaves as active if it gets 0 as input binary equivalent of the input. If two
since it is an active-low pin. inputs are active on a priority
encoder, the input of higher value
165. Can an encoder be called as
will be coded in the output.
multiplexer?
a) No 167. How many outputs are present
b) Yes in a BCD decoder?
c) Sometimes a) 4
d) Never b) 5
c) 15
Answer: b
d) 10
Explanation: A multiplexer or MUX is
a combination circuit that contains Answer: d
more than one input line, one output Explanation: A binary decoder is a
line and more than one selection line. combinational logic circuit which
Whereas, an encoder is also decodes binary information from n-
considered a type of multiplexer but inputs to a maximum of 2n outputs. A
BCD to Decimal decoder has 10

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number of outputs because the 170. How many inputs are required
decimal digit‟s range is from 0 to 9. for a 1-of-10 BCD decoder?
a) 4
168. Which digital system translates
b) 8
coded characters into a more useful
c) 10
form?
d) 2
a) Encoder
b) Display Answer: a
c) Counter Explanation: A binary decoder is a
d) Decoder combinational logic circuit which
decodes binary information from n-
Answer: d
inputs to a maximum of 2n outputs.
Explanation: A binary decoder is a
Therefore, for a BCD to decimal
combinational logic circuit which
decoder, No. of inputs = 4 such that
decodes binary information from n-
number of outputs is <= 2n.
inputs to a maximum of 2n outputs.
Decoder converts the coded 171. A BCD decoder will have how
characters into our required data many rows in its truth table?
form. a) 10
b) 9
169. What control signals may be
c) 8
necessary to operate a 1-line-to-16
d) 3
line decoder?
a) Flasher circuit control signal Answer: a
b) A LOW on all gate enable inputs Explanation: A binary decoder is a
c) Input from a hexadecimal counter combinational logic circuit which
d) A HIGH on all gate enable circuits decodes binary information from n-
inputs to a maximum of 2n outputs.
Answer: b
Thus, BCD decoder will have 10 rows
Explanation: A LOW on all gate
as it‟s input ranges from 0 to 9.
enable inputs is necessary to operate
a 1-line-to-16 line decoder because 172. How many possible outputs
enable pins are usually, active-low would a decoder have with a 6-bit
pins. binary input?

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a) 32 inputs to a maximum of 2n outputs.

b) 64 Here, number of outputs = 16.
c) 128 16 = 24 = 2n. Thus, number of inputs is
d) 16 4.

Answer: c 175. A truth table with output

Explanation: The possible outputs columns numbered 0–15 may be for
would be: 2n = 64 (Since n = 6 here). which type of decoder IC?
a) Hexadecimal 1-of-16
173. One way to convert BCD to
b) Dual octal outputs
binary using the hardware approach
c) Binary-to-hexadecimal
is:
d) Hexadecimal-to-binary
a) By using MSI IC circuits
b) By using a keyboard encoder Answer: a
c) By using an ALU Explanation: A binary decoder is a
d) By using UART combinational logic circuit which
decodes binary information from n-
Answer: a
inputs to a maximum of 2n outputs. A
Explanation: One way to convert BCD
truth table with output columns
to binary using the hardware
numbered 0–15 may be for
approach is MSI (medium scale
Hexadecimal 1-of-16. Because,
integration) IC circuits.
hexadecimal occupies less space in a
174. How many inputs are required system.
for a 1-of-16 decoder?
176. How can the active condition
a) 2
(HIGH or LOW) or the decoder output
b) 16
be determined from the logic
c) 8
symbol?
d) 4
a) A bubble indicates active-HIGH
Answer: d b) A bubble indicates active-LOW
Explanation: A binary decoder is a c) A triangle indicates active-HIGH
combinational logic circuit which d) A triangle indicates active-LOW
decodes binary information from n-

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Answer: b given: 0101=5, 0011=3. Then convert

Explanation: A bubble indicates 53 to binary, which will give 110101.
active-LOW in a decoder always. Again, do the same with the next 4
Enable pin of the decoder is usually set of binary digits.
active-LOW and is triggered on input
179. The primary use for Gray code is
being at 0.

177. A code converter is a logic circuit a) Coded representation of a shaft‟s

that mechanical position
a) Inverts the given input b) Turning on/off software switches
b) Converts into decimal number c) To represent the correct ASCII code
c) Converts data of one type into to indicate the angular position of a
another type shaft on rotating machinery
d) Converts to octal d) To convert the angular position of
a shaft on rotating machinery into
Answer: c
hexadecimal code
Explanation: A code converter is a
logic circuit that changes data Answer: a
presented in one type of binary code Explanation: Gray code is useful
to another type of binary code. because only one bit changes at a
time, which is implemented easily in
178. Use the weighting factors to
Coded representation of a shaft‟s
convert the following BCD numbers
mechanical position. In Gray Code,
to binary _
every sequence of successive bits
0101 0011 & 0010 0110 1000 differs by 1 bit only.

a) 01010011 001001101000 180. Code is a symbolic

b) 11010100 100001100000 representation of
c) 110101 100001100 a) Discrete information
d) 101011 001100001 b) Continuous information
c) Decimal information into binary
Answer: c
d) Binary information into decimal
Explanation: Firstly, convert every 4
sets of binary to decimal from the

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Answer: a position of a rotating shaft because

Explanation: Code is a symbolic only one digit changes between
representation of discrete counts that is reflected to the next
information. Codes can be anything count.
like numbers, letter or words, written
183. Reflected binary code is also
in terms of group of symbols.
known as
181. One way to convert BCD to a) BCD code
binary using the hardware approach b) Binary code
is c) ASCII code
a) With MSI IC circuits d) Gray Code
b) With a keyboard encoder
Answer: d
c) With an ALU
Explanation: The reflected binary
d) UART
code is also known as gray code
Answer: a because one digit reflected to the
Explanation: One way to convert BCD next bit. In Gray Code, every
to binary using the hardware sequence of successive bits differs by
approach is MSI IC (i.e. medium scale 1 bit only.
integration) circuits.
184. Why do we use gray codes?
182. Why is the Gray code more a) To count the no of bits changes
practical to use when coding the b) To rotate a shaft
position of a rotating shaft? c) Error correction
a) All digits change between counts d) Error Detetction
b) Two digits change between counts
Answer: c
c) Only one digit changes between
Explanation: Today, Gray codes are
counts
widely used to facilitate error
d) Alternate digit changes between
correction in digital communications
counts
such as digital terrestrial television
Answer: c and some cable TV systems.
Explanation: The Gray code is more
practical to use when coding the

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185. Earlier, reflected binary codes 187. Convert binary number into gray
were applied to code: 100101.
a) Binary addition a) 101101
b) 2‟s complement b) 001110
c) Mathematical puzzles c) 110111
d) Binary multiplication d) 111001

Answer: c Answer: c
Explanation: The reflected binary Explanation: : Conversion from Binary
code is also known as gray code To Gray Code:
because one digit reflected to the
1 (XOR) 0 (XOR) 0 (XOR) 1 (XOR) 0
next bit. In Gray Code, every
(XOR) 1
sequence of successive bits differs by
1 bit only. Reflected binary codes ↓ ↓ ↓ ↓ ↓
were applied to mathematical puzzles
1 1 0 1 1 1
before they became known to
engineers. 188. Each personal computer has a
that manages the
186. The binary representation of
computer‟s arithmetical, logical and
BCD number 00101001 (decimal 29)
control activities.
is
a) Microprocessor
a) 0011101
b) Assembler
b) 0110101
c) Microcontroller
c) 1101001
d) Interpreter
d) 0101011
Answer: a
Answer: a
Explanation: Microprocessor handles
Explanation: The given BCD number
all these activities. Each family of
00101001 has three 1s. So, it can be
processors has its own set of
rewritten as 0000001-1, 0001000-8,
instructions for handling various
0010100-20 and after addition, we
operations like getting input from
get 0011101 as output.
keyboard, displaying information on a

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screen and performing various other a) Segment Address

jobs. b) Absolute Address
c) Offset
189. Assembly Language requires less
d) Memory Address
memory and execution time.
a) True Answer: b
b) False Explanation: There are two kinds of
memory addresses:
Answer: a
• An absolute address – a direct
Explanation: The statement is true.
reference of specific location.
Advantages of using assembly
• The segment address (or offset) –
language are:
starting address of a memory
• It requires less memory and
segment with the offset value.
execution time.
• It allows hardware-specific complex 192. A Borland Turbo Assembler.
jobs in an easier way. a) nasm
• It is suitable for time-critical jobs. b) tasm
c) gas
190. The data size of a word is
d) asm
a) 2-byte Answer: b
b) 4-byte Explanation: Tasm is the borland
c) 8-byte turbo assembler. Nasm is used with
d)16-byte linux generally. Gas is the GNU
assembler.
Answer: a
Explanation: The processor supports 193. The instructions that tell the
the following data sizes: assembler what to do.
• Word: a 2-byte data item a) Executable instructions
• Double word: a 4-byte (32 bit) data b) Pseudo-ops
item, etc. c) Logical instructions
d) Macros
191. A direct reference of specific
location.

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Answer: a Answer: d
Explanation: The executable Explanation: The processor has some
instructions or simple instructions tell internal memory storage locations,
the processor what to do. Each known as registers. The registers
instruction consists of an operation stores data elements for processing
code (opcode). Each executable without having to access memory.
instruction generates one machine
196. To locate the exact location of
language instruction.
data in memory, we need the starting
194. The segment containing data address of the segment, which is
values passed to functions and found in the DS register and an offset
procedures within the program. value. This offset value is also called?
a) Code a) Effective Address
b) Data b) Direct offset address
c) Stack c) Memory address
d) System d) General Address

Answer: c Answer: a
Explanation: The stack segment Explanation: When operands are
contains data values passed to specified in memory addressing
functions and procedures within the mode, direct access to main memory,
program. The code segment defines usually to the data segment, is
an area in memory that stores the required. This way of addressing
instruction codes. results in slower processing of data.
To get the exact location of data in
195. To speed up the processor
memory, we need segment start
operations, the processor includes
address, which is found in the DS
some internal memory storage
register and an offset value. This
locations, called
offset value is called an effective
a) Drives
address.
b) Memory
c) Units 197. Each byte of character is stored
d) Registers as its ASCII value in

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a) Hexadecimal c) Three stable state

b) Binary d) Infinite stable states
c) Octal
Answer: b
d) Decimal
Explanation: Since, a latch works on
Answer: a the principal of bistable
Explanation: Assembly language deals multivibrator. A Bistable
with hexadecimal values only. Each multivibrator is one in which the
decimal value is automatically circuit is stable in either of two
converted to its 16-bit binary states. It can be flipped from one
equivalent and stored as a state to the other state and vice-
hexadecimal number. versa. So a latch has two stable
states.
198. A latch is an example of a
200. Why latches are called a
a) Monostable multivibrator memory devices?
b) Astable multivibrator a) It has capability to stare 8 bits of
c) Bistable multivibrator data
d) 555 timer b) It has internal memory of 4 bit
c) It can store one bit of data
Answer: c
d) It can store infinite amount of data
Explanation: A latch is an example of
a bistable multivibrator. A Bistable Answer: c
multivibrator is one in which the Explanation: Latches can be memory
circuit is stable in either of two devices, and can store one bit of data
states. It can be flipped from one for as long as the device is powered.
state to the other state and vice- Once device is turned off, the
versa. memory gets refreshed.
199. Latch is a device with 201. Two stable states of latches are

a) One stable state a) Astable & Monostable

b) Two stable state b) Low input & high output

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c) High output & low output set/reset. It is a type of latch having

d) Low output & high input two stable states.

Answer: c 204. The SR latch consists of

Explanation: A latch has two stable
states, following the principle of a) 1 input
Bistable Multivibrator. There are two b) 2 inputs
stable states of latches and these c) 3 inputs
states are high-output and low- d) 4 inputs
output.
Answer: b
202. How many types of latches are Explanation: SR or Set-Reset latch is
the simplest type of bistable
a) 4 multivibrator having two stable
b) 3 states.
c) 2 The diagram of SR latch is shown
d) 5 below:
Answer: a
Explanation: There are four types of
latches: SR latch, D latch, JK latch and
T latch. D latch is a modified form of
SR latch whereas, T latch is an
advanced form of JK latch.

203. The full form of SR is 205. The outputs of SR latch are

a) System rated a) x and y

b) Set reset b) a and b
c) Set ready c) s and r
d) Set Rated d) q and q‟

Answer: b Answer: d
Explanation: The full form of SR is Explanation: SR or Set-Reset latch is

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the simplest type of bistable Answer: b

multivibrator having two stable Explanation: All flip flops have at least
states. The inputs of SR latch are s one output labeled Q (i.e. inverted).
and r while outputs are q and q‟. It is This is so because the flip flops have
clear from the diagram: inverting gates inside them, hence in
order to have both Q and Q
complement available, we have
atleast one output labelled.

208. The inputs of SR latch are

. a) x and y
b) a and b
206. The NAND latch works when
c) s and r
both inputs are
d) j and k
a) 1
b) 0
c) Inverted Answer: c
d) Don‟t cares Explanation: SR or Set-Reset latch is
the simplest type of bistable
Answer: a
multivibrator having two stable
Explanation: The NAND latch works
states. The inputs of SR latch are s
when both inputs are 1. Since, both
and r while outputs are q and q‟. It is
of the inputs are inverted in a NAND
clear from the diagram:
latch.

207. The first step of analysis

procedure of SR latch is to

a) label inputs
b) label outputs
c) label states
d) label tables 209. When a high is applied to the Set
line of an SR latch, then

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a) Q output goes high identical and this is “metastable”, and

b) Q‟ output goes high the device will be in an undefined
c) Q output goes low state for an indefinite period.
d) Both Q and Q‟ go high
212. Latches constructed with NOR
Answer: a and NAND gates tend to remain in
Explanation: S input of a SR latch is the latched condition due to which
directly connected to the output Q. configuration feature?
So, when a high is applied Q output a) Low input voltages
goes high and Q‟ low. b) Synchronous operation
c) Gate impedance
210. When both inputs of SR latches
d) Cross coupling
are low, the latch
a) Q output goes high Answer: d
b) Q‟ output goes high Explanation: Latch is a type of
c) It remains in its previously set or bistable multivibrator having two
reset state stable states. Both inputs of a latch
d) it goes to its next set or reset state are directly connected to the other‟s
output. Such types of structure is
Answer: c
called cross coupling and due to
Explanation: When both inputs of SR
which latches remain in the latched
latches are low, the latch remains in
condition.
it‟s present state. There is no change
in the output. 213. One example of the use of an S-
R flip-flop is as _
211. When both inputs of SR latches
a) Transition pulse generator
are high, the latch goes
b) Racer
a) Unstable
c) Switch debouncer
b) Stable
d) Astable oscillator
c) Metastable
d) Bistable Answer: c
Explanation: The SR flip-flop is very
Answer: c
effective in removing the effects of
Explanation: When both gates are
switch bounce, which is the

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unwanted noise caused during the 216. Which of the following is correct
switching of electronic devices. for a gated D-type flip-flop?
a) The Q output is either SET or RESET
214. The truth table for an S-R flip-
as soon as the D input goes HIGH or
flop has how many VALID entries?
LOW
a) 1
b) The output complement follows
b) 2
the input when enabled
c) 3
c) Only one of the inputs can be HIGH
d) 4
at a time
Answer: c d) The output toggles if one of the
Explanation: The SR flip-flop actually inputs is held HIGH
has three inputs, Set, Reset and its
Answer: a
current state. The Invalid or
Explanation: In D flip flop, when the
Undefined State occurs at both S and
clock is high then the output depends
R being at 1.
on the input otherwise reminds
215. When both inputs of a J-K flip- previous output. In a state of clock
flop cycle, the output will high, when D is high the output Q
also high, if D is „0‟ then output is also
a) Be invalid zero. Like SR flip-flop, the D-flip-flop
b) Change also have an invalid state at both
c) Not change inputs being 1.
d) Toggle
217. A basic S-R flip-flop can be
Answer: c constructed by cross-coupling of
Explanation: After one cycle the value which basic logic gates?
of each input comes to the same a) AND or OR gates
value. Eg: Assume J=0 and K=1. After b) XOR or XNOR gates
1 cycle, it becomes as J=0->1->0(1 c) NOR or NAND gates
cycle complete) and K=1->0->1(1 d) AND or NOR gates
cycle complete). The J & K flip-flop
Answer: c
has 4 stable states: Latch, Reset, Set
Explanation: The basic S-R flip-flop
and Toggle.

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can be constructed by cross coupling Answer: a

of NOR or NAND gates. Cross Explanation: Combinational circuits
coupling means the output of second are often faster than sequential
gate is fed to the input of first gate circuits. Since, the combinational
and vice-versa. circuits do not require memory
elements whereas the sequential
218. The logic circuits whose outputs
circuits need memory devices to
at any instant of time depends only
perform their operations in
on the present input but also on the
sequence. Latches and Flip-flops
past outputs are called
come under sequential circuits.
a) Combinational circuits
b) Sequential circuits 220. How many types of sequential
c) Latches circuits are?
d) Flip-flops a) 2
b) 3
Answer: b
c) 4
Explanation: In sequential circuits,
d) 5
the output signals are fed back to the
input side. So, The circuits whose Answer: a
outputs at any instant of time Explanation: There are two type of
depends only on the present input sequential circuits viz., (i)
but also on the past outputs are synchronous or clocked and (ii)
called sequential circuits. Unlike asynchronous or unclocked.
sequential circuits, if output depends Synchronous Sequential Circuits are
only on the present state, then it‟s triggered in the presence of a clock
known as combinational circuits. signal, whereas, Asynchronous
Sequential Circuits function in the
219. Whose operations are more
absence of a clock signal.
faster among the following?
a) Combinational circuits 221. The sequential circuit is also
b) Sequential circuits called
c) Latches a) Flip-flop
d) Flip-flops b) Latch

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c) Strobe 224. What is a trigger pulse?

d) Adder a) A pulse that starts a cycle of
operation
Answer: b
b) A pulse that reverses the cycle of
Explanation: The sequential circuit is
operation
also called a latch because both are a
c) A pulse that prevents a cycle of
memory cell, which are capable of
operation
storing one bit of information.
d) A pulse that enhances a cycle of
222. The basic latch consists of operation

Answer: a
a) Two inverters
Explanation: Trigger pulse is defined
b) Two comparators
as a pulse that starts a cycle of
c) Two amplifiers
operation.
d) Two adders
225. The circuits of NOR based S-R
Answer: a
latch classified as asynchronous
Explanation: The basic latch consists
sequential circuits, why?
of two inverters. It is in the sense that
a) Because of inverted outputs
if the output Q = 0 then the second
b) Because of triggering functionality
output Q‟ = 1 and vice versa.
c) Because of cross-coupled
223. In S-R flip-flop, if Q = 0 the connection
output is said to be d) Because of inverted outputs &
a) Set triggering functionality
b) Reset
Answer: c
c) Previous state
Explanation: The cross-coupled
d) Current state
connections from the output of one
Answer: b gate to the input of the other gate
Explanation: In S-R flip-flop, if Q = 0 constitute a feedback path. For this
the output is said to be reset and set reason, the circuits of NOR based S-R
for Q = 1. latch classified as asynchronous
sequential circuits. Moreover, they

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are referred to as asynchronous Answer: c

because they function in the absence Explanation: A counter circuit is
of a clock pulse. usually constructed of a number of
flip-flops connected in cascade.
226. In digital logic, a counter is a
Preferably, JK Flip-flops are used to
device which
construct counters and registers.
a) Counts the number of outputs
b) Stores the number of times a 228. What is the maximum possible
particular event or process has range of bit-count specifically in n-bit
occurred binary counter consisting of „n‟
c) Stores the number of times a clock number of flip-flops?
pulse rises and falls a) 0 to 2n
d) Counts the number of inputs b) 0 to 2n + 1
c) 0 to 2n – 1
Answer: b
d) 0 to 2n+1/2
Explanation: In digital logic and
computing, a counter is a device Answer: c
which stores (and sometimes Explanation: The maximum possible
displays) the number of times a range of bit-count specifically in n-bit
particular event or process has binary counter consisting of „n‟
occurred, often in relationship to a number of flip-flops is 0 to 2n-1. For
clock signal. say, there is a 2-bit counter, then it
will count till 22-1 = 3. Thus, it will
227. A counter circuit is usually
count from 0 to 3.
constructed of
a) A number of latches connected in 229. How many types of the counter
cascade form are there?
b) A number of NAND gates a) 2
connected in cascade form b) 3
c) A number of flip-flops connected in c) 4
cascade d) 5
d) A number of NOR gates connected
Answer: b
in cascade form
Explanation: Counters are of 3 types,

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namely, have their preceding flip-flop output

(i)asynchronous/synchronous, as clock to them.
(ii)single and multi-mode &
232. Synchronous counter is a type of
(iii)modulus counter. These further
can be subdivided into Ring Counter,
a) SSI counters
Johnson Counter, Cascade Counter,
b) LSI counters
Up/Down Counter and such like.
c) MSI counters
230. A decimal counter has d) VLSI counters
states.
Answer: c
a) 5
Explanation: Synchronous Counter is
b) 10
a Medium Scale Integrated (MSI). In
c) 15
Synchronous Counters, the clock
d) 20
pulse is supplied to all the flip-flops
Answer: b simultaneously.
Explanation: Decimal counter is also
233. Three decade counter would
known as 10 stage counter. So, it has
have
10 states. It is also known as Decade
a) 2 BCD counters
Counter counting from 0 to 9.
b) 3 BCD counters
231. Ripple counters are also called c) 4 BCD counters
d) 5 BCD counters
a) SSI counters
Answer: b
b) Asynchronous counters
Explanation: Three decade counter
c) Synchronous counters
has 30 states and a BCD counter has
d) VLSI counters
10 states. So, it would require 3 BCD
Answer: b counters. Thus, a three decade
Explanation: Ripple counters are also counter will count from 0 to 29.
called asynchronous counter. In
234. BCD counter is also known as
Asynchronous counters, only the first
flip-flop is connected to an external
a) Parallel counter
clock while the rest of the flip-flops

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b) Decade counter Answer: d

c) Synchronous counter Explanation: A register is defined as
d) VLSI counter the group of flip-flops suitable for
storing binary information. Each flip-
Answer: b
flop is a binary cell capable of storing
Explanation: BCD counter is also
one bit of information. The data in a
known as decade counter because
register can be transferred from one
both have the same number of stages
flip-flop to another.
and both count from 0 to 9.
237. The register is a type of
235. The parallel outputs of a counter
circuit represent the
a) Sequential circuit
a) Parallel data word
b) Combinational circuit
b) Clock frequency
c) CPU
c) Counter modulus
d) Latches
d) Clock count
Answer: a
Answer: d
Explanation: Register‟s output
Explanation: The parallel outputs of a
depends on the past and present
counter circuit represent the clock
states of the inputs. The device which
count. A counter counts the number
follows these properties is termed as
of times an event takes place in
a sequential circuit. Whereas,
accordance to the clock pulse.
combinational circuits only depend
236. A register is defined as on the present values of inputs.

238. How many types of registers

a) The group of latches for storing
are?
one bit of information
a) 2
b) The group of latches for storing n-
b) 3
bit of information
c) 4
c) The group of flip-flops suitable for
d) 5
storing one bit of information
d) The group of flip-flops suitable for Answer: c
storing binary information Explanation: There are 4 types of shift

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registers, viz., Serial-In/Serial-Out, Registers are made of a group of flip-

Serial-In/Parallel-Out, Parallel- flops.
In/Serial-Out and Parallel-In/Parallel-
241. Registers capable of shifting in
Out.
one direction is
239. The main difference between a a) Universal shift register
register and a counter is b) Unidirectional shift register
c) Unipolar shift register
a) A register has no specific sequence d) Unique shift register
of states
Answer: b
b) A counter has no specific sequence
Explanation: The register capable of
of states
shifting in one direction is
c) A register has capability to store
unidirectional shift register. The
one bit of information but counter
register capable of shifting in both
has n-bit
directions is known as a bidirectional
d) A register counts data
shift register.
Answer: a
242. A register that is used to store
Explanation: The main difference
binary information is called
between a register and a counter is
that a register has no specific
a) Data register
sequence of states except in certain
b) Binary register
specialised applications.
c) Shift register
240. In D register, „D‟ stands for d) D – Register

Answer: b
a) Delay
Explanation: A register that is used to
b) Decrement
store binary information is called a
c) Data
binary register. A register in which
d) Decay
data can be shifted is called shift
Answer: c register.
Explanation: D stands for “data” in
case of flip-flops and not delay.

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243. A shift register is defined as these are serial shifting & parallel
shifting.
a) The register capable of shifting
245. In serial shifting method, data
information to another register
shifting occurs
b) The register capable of shifting
a) One bit at a time
information either to the right or to
b) simultaneously
the left
c) Two bit at a time
c) The register capable of shifting
d) Four bit at a time
information to the right only
d) The register capable of shifting Answer: a
information to the left only Explanation: As the name suggests
serial shifting, it means that data
Answer: b
shifting will take place one bit at a
Explanation: The register capable of
time for each clock pulse in a serial
shifting information either to the
fashion. While in parallel shifting,
right or to the left is termed as shift
shifting will take place with all bits
register. A register in which data can
simultaneously for each clock pulse in
be shifted only in one direction is
a parallel fashion.
called unidirectional shift register,
while if data can shifted in both 246. Memory is a/an
directions, it is known as a a) Device to collect data from other
bidirectional shift register. computer
b) Block of data to keep data
244. How many methods of shifting
separately
of data are available?
c) Indispensable part of computer
a) 2
d) Device to connect through all over
b) 3
the world
c) 4
d) 5 Answer: c
Explanation: Memory is an
Answer: a
indispensable unit of a computer and
Explanation: There are two types of
microprocessor based systems which
shifting of data are available and
stores permanent or temporary data.

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247. The instruction used in a Answer: b

program for executing them is stored Explanation: Register is also a part of
in the memory inside a computer. It stands
a) CPU there to hold a word. A word is a
b) Control Unit group of 16-bits or 2-bytes.
c) Memory
250. A register file holds
d) Microprocessor
a) A large number of word of
Answer: c information
Explanation: All of the program and b) A small number of word of
the instructions are stored in the information
memory. The processor fetches it as c) A large number of programs
and when required. d) A modest number of words of
information
248. A flip flop stores
a) 10 bit of information Answer: d
b) 1 bit of information Explanation: A register file is different
c) 2 bit of information from a simple register because of
d) 3-bit information capability to hold a modest number
of words of information. A word is a
Answer: b
group of 16-bits or 2-bytes.
Explanation: A flip-flop has capability
to store 1 bit of information. It can be 251. The very first computer memory
used further after erasing previous consisted of
information. a) A small display
b) A large memory storage
249. A register is able to hold
equipment
c) An automatic keyboard input
a) Data
d) An automatic mouse input
b) Word
c) Nibble Answer: b
d) Both data and word Explanation: The very first computer
memory consisted of a minute
magnetic toroid, which required

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large, bulky circuit boards stored in b) VLSI semiconductor

large cabinates. c) CDR semiconductor
d) SSI semiconductor
252. A minute magnetic toroid is also
called as Answer: b
a) Large memory Explanation: VLSI (Very Large Scale
b) Small memory Integration) semiconductor is used in
c) Core memory modern computers to short the size
d) Both small and large memory of memory.

Answer: c 255. VLSI chip utilizes

Explanation: A minute magnetic a) NMOS
toroid is also called as core memory b) CMOS
which is made up of a semiconductor. c) BJT
A semiconductor is a device whose d) All of the Mentioned
electrical conductivity lies between
Answer: d
that of conductor and insulator.
Explanation: VLSI (Very Large Scale
253. Which one of the following has Integration) is a memory chip which
capability to store data in extremely is made up of NMOS, CMOS, BJT, and
high densities? BiCMOS. It can include 10,000 to
a) Register 100,000 gates per IC.
b) Capacitor
256. CD-ROM refers to
c) Semiconductor
a) Floppy disk
d) Flip-Flop
b) Compact Disk-Read Only Memory
Answer: c c) Compressed Disk-Read Only
Explanation: Semiconductor has Memory
capability to store data in extremely d) Compressed Disk- Random Access
high densities. Memory

254. A large memory is compressed Answer: b

into a small one by using Explanation: CD-ROM refers to
a) LSI semiconductor Compact Disk-Read Only Memory.

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257. Data stored in an electronic Answer: a

memory cell can be accessed at Explanation: The evolution of PLD
random and on demand using (Programmable Logic Device) began
with Programmable Read Only
a) Memory addressing Memory (i.e. PROM). Here, the ROM
b) Direct addressing can be externally programmed as per
c) Indirect addressing the user.
d) Control Unit
260. A ROM is defined as
Answer: b a) Read Out Memory
Explanation: Direct addressing b) Read Once Memory
eliminates the need to process a c) Read Only Memory
large stream of irrelevant data in d) Read One Memory
order to the desired data word. View Answer
258. The full form of PLD is Answer: c
Explanation: A ROM is defined as
a) Programmable Large Device Read Only Memory which can read
b) Programmable Long Device the instruction stored in a computer.
c) Programmable Logic Device
d) Programmable Lengthy Device 261. Which of the circuits in figure (a
to d) is the sum-of-products
Answer: c implementation of figure (e)?
Explanation: The full form of PLD is
Programmable Logic Device.

259. The evolution of PLD began with

a) EROM
b) RAM
c) PROM
d) EEPROM

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262. Which of the following logic

expressions represents the logic
diagram shown?

a) X=AB‟+A‟B
b) X=(AB)‟+AB
c) X=(AB)‟+A‟B‟
d) X=A‟B‟+AB

Answer: d
Explanation: 1st output of AND gate
is = A‟B‟
2nd AND gate‟s output is = AB and,
OR gate‟s output is = (A‟B‟)+(AB) = AB
a) a + A‟B‟.
b) b
c) c 263. The device shown here is most
d) d likely a

Answer: d
Explanation: SOP means Sum Of
Products form which represents the
sum of product terms having
variables in complemented as well as a) Comparator
in uncomplemented form. Here, the b) Multiplexer
diagram of d contains the OR gate c) Inverter
followed by the AND gates, so it is in d) Demultiplexer
SOP form.

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Answer: d below, which output waveform is

Explanation: The given diagram is correct?
demultiplexer, because it takes single
input & gives many outputs. A
demultiplexer is a combinational
circuit that takes a single output and
latches it to multiple outputs
depending on the select lines.

264. What type of logic circuit is

represented by the figure shown
below?
a) d
b) a
c) c
d) b

Answer: a
a) XOR Explanation: When both inputs are
b) XNOR same then the o/p is high for a XNOR
gate.
c) AND
d) XAND i.e., A B O/P
0 01
Answer: b 010
Explanation: After solving the circuit 100
we get (A‟B‟)+AB as output, which is 1 1 1.
XNOR operation. Thus, it will produce Thus, it will produce 1 when inputs
1 when inputs are even number of 1s are even number of 1s or all 0s, and
or all 0s, and produce 0 when input is produce 0 when input is odd number
odd number of 1s. of 1s.
265. For a two-input XNOR gate, with 266. Which of the following
the input waveforms as shown combinations of logic gates can

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decode binary 1101? results in information being disrupted

a) One 4-input AND gate and loss of data.
b) One 4-input AND gate, one
268. For the device shown here,
inverter
assume the D input is LOW, both S
c) One 4-input AND gate, one OR gate
inputs are LOW and the input is LOW.
d) One 4-input NAND gate, one
What is the status of the Y‟ outputs?
inverter

Answer: b
Explanation: For decoding any
number output must be high for that
code and this is possible in One 4-
input NAND gate, one inverter option a) All are HIGH
only. A decoder is a combinational b) All are LOW
circuit that converts binary data to n- c) All but Y0 are LOW
coded data upto 2n outputs. d) All but Y0 are HIGH
267. What is the indication of a short Answer: d
to ground in the output of a driving Explanation: In the given diagram, S0
gate? and S1 are selection bits. So,
a) Only the output of the defective I/P S0 S1 O/P
gate is affected D = 0 0 0 Y0
b) There is a signal loss to all load D = 0 0 1 Y1
gates D = 0 1 0 Y2
c) The node may be stuck in either D = 0 1 1 Y3
the HIGH or the LOW state Hence, inputs are S0 and S1 are Low
d) The affected node will be stuck in means 0, so output is Y0 and rest all
the HIGH state are HIGH.
Answer: b 269. The carry propagation can be
Explanation: Short to ground in the expressed as
output of a driving gate indicates of a a) Cp = AB
signal loss to all load gates. This b) Cp = A + B

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c) All but Y0 are LOW a) Arithmetic and logic unit

d) All but Y0 are HIGH b) Motherboard
c) Control Unit
Answer: b
d) Memory
Explanation: This happens in parallel
adders (where we try to add numbers Answer: a
in parallel via more than one adders). Explanation: The Arithmetic and logic
A carry propagation occurs when unit performs all the basic operations
carry from one adder needs to be of the computer system. It performs
forwarded to other adder and that all the arithmetic(+,-,*,/,etc) as well
second adder is holding the as the logical operations( AND, OR,
computation (addition) because carry NOT, etc.).
from first adder has not come yet. So,
272. ALU is the place where the
there is a slight delay for second
actual executions of instructions take
adder and this is known as carry
place during the processing
propagation.
operation.
270. 3 bits full adder contains a) True
b) False
a) 3 combinational inputs
Answer: a
b) 4 combinational inputs
Explanation: ALU is a combinational
c) 6 combinational inputs
electronic circuit which basically
d) 8 combinational inputs
performs all the logical or the bitwise
Answer: d operations and the arithmetic
Explanation: Full Adder is a operations. Therefore, it is the place
combinational circuit with 3 input bits where the actual executions of
and 2 output bits CARRY and SUM. instructions take place.
Three bits full adder requires 23 = 8
273. Which of the following is not a
combinational circuits.
bitwise operator?
271. The „heart‟ of the processor a) |
which performs many different b) ^
operations

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c) . d) Institute of Electrical and

d) << electronics engineers

Answer: c Answer: d
Explanation: All except the dot(.) Explanation: The IEEE is an
operator are bitwise operators. organization of professionals in the
| : Bitwise OR field of electronics and electrical
^ : Bitwise XOR engineering. IEEE has given certain
<< : Shift Left standards of its own which are
followed in the field of computer
274. The sign magnitude
science and electrical engineering.
representation of -1 is
a) 0001 276. The ALU gives the output of the
b) 1110 operations and the output is stored in
c) 1000 the
d) 1001 a) Memory Devices
b) Registers
Answer: d
c) Flags
Explanation: The first leftmost bit i.e.
d) Output Unit
the most significant bit in the sign
magnitude represents if the number Answer: b
is positive or negative. If the MSB is 1, Explanation: Any output generated
the number is negative else if it is 0, by the ALU gets stored in the
the number is positive. Here, registers. The registers are the
+1=0001 and for -1=1001. temporary memory locations within
the processor that are connected by
275. IEEE stands for
signal paths to the CPU.
a) Instantaneous Electrical
Engineering 278. The process of division on
b) Institute of Emerging Electrical memory spaces is called
Engineers
c) Institute of Emerging Electronic a) Paging
Engineers b) Segmentation

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c) Bifurcation the number of 1 bit in any operation.

d) Dynamic Division The resultant bit is called the parity
bit. The main aim of the parity bit is
Answer: b
to check for errors.
Explanation: The memory space is
divided into segments of dynamic 281. The bitwise complement of 0 is
size. The programmer is aware of the
segmentation and can reallocate the a) 00000001
segments accordingly. b) 10000000
c) 11111111
279. Number of bits in ALU is
d) 11111110
a) 4 Answer: c
b) 8 Explanation: Bitwise complement is
c) 16 basically used to convert all the 0
d) 2 digits to 1 and the 1s to 0s.
So, for 0 = 00000000(in 8-bits) :::
Answer: c
11111111(1s complement). The
Explanation: Arithmetic and Logic
bitwise complement is often referred
Unit consists of 16bits. They perform
to as the 1s complement.
certain Arithmetic and bitwise
operations (add, subtract, AND, OR, 282. Unicode provides a consistent
XOR, Increment, decrement, shift). way of encoding multilingual plain
text.
280. Which flag indicates the number
a) True
of 1 bit that results from an
b) False
operation?
a) Zero Answer: a
b) Parity Explanation: Unicode defines codes
c) Auxiliary for characters used in all major
d) Carry languages of the world.
It is a coding system which supports
Answer: b
almost all the languages. It defines
Explanation: The parity flag indicates

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special codes for different characters, 285. The EBCDIC value of the number
symbols, diacritics, etc. 345 in zoned format is
a) F3F4F5
283. Which of the following is not a
b) E3E4E5
type of numeric value in zoned
c) F3F4C5
format?
d) F3F4D5
a) Positive
b) Negative Answer: a
c) Double Explanation: F is used for the
d) Unsigned representation of unsigned numbers
therefore, F3F4F5 represents 345.
Answer: c
F3F4C5 represents +345 . F3F4D5
Explanation: The zoned format can
represents -345.
represent numeric values of type
Positive, negative and unsigned 286. Which of the following logic
numbers. A sign indicator is used in families has the highest maximum
the zone position of the rightmost clock frequency?
digit. a) S-TTL
b) AS-TTL
284. The sign indicator of unsigned
c) HS-TTL
numbers is
d) HCMOS
a) C
b) D Answer: b
c) F Explanation: AS-TTL (Advanced
d) X Schottky) has a maximum clock
frequency of 105 MHz. S-TTL
Answer: c
(Schottky High Speed TTL) has 100
Explanation: A sign indicator is used
MHz. Found nothing as HS-TTL. There
in the zone position of the rightmost
are H and S separate TTL. HCMOS has
digit. A sign indicator C is used for
50 MHz clock frequency.
positive, D for negative and F is used
for negative numbers. 287. Why is the fan-out of CMOS
gates frequency dependent?
a) Each CMOS input gate has a

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specific propagation time and this As the frequency increases Pd also

limits the number of different gates increases so fan-out depends on
that can be connected to the output frequency.
of a CMOS gate
288. Logic circuits that are designated
b) When the frequency reaches the
as buffers, drivers or buffers/drivers
critical value the gate will only be
are designed to have:
capable of delivering 70% of the
a) A greater current/voltage
normal output voltage and
capability than an ordinary logic
consequently the output power will
circuit
be one-half of normal and this
b) Greater input current/voltage
defines the upper operating
capability than an ordinary logic
frequency
circuit
c) The higher number of gates
c) A smaller output current/voltage
attached to the output the more
capability than an ordinary logic
frequently they will have to be
d) Greater the input and output
serviced thus reducing the frequency
current/voltage capability than an
at which each will be serviced with an
ordinary logic circuit
input signal
d) The input gates of the FETs are Answer: a
predominantly capacitive and as the Explanation: Buffer circuits are
signal frequency increases the usually incorporated to isolate the
capacitive loading also increases input from the output. Logic circuits
thereby limiting the number of loads that are designated as buffers, drivers
that may be attached to the output or buffer/drivers are designed to
of the driving gate have a greater current/voltage
capability than an ordinary logic
Answer: d
circuit.
Explanation: Fan out is the measure
of maximum number of inputs that a 289. Which of the following will not
single logic gate output can drive. normally be found on a data sheet?
Actually power dissipation in CMOS a) Minimum HIGH level output
circuits depends on clock frequency. voltage

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b) Maximum LOW level output Answer: b

voltage Explanation: ARM is a type of system
c) Minimum LOW level output architecture.
voltage
292. The main importance of ARM
d) Maximum HIGH level input current
micro-processors is providing
Answer: c operation with
Explanation: Minimum LOW level a) Low cost and low power
output voltage will not normally be consumption
found on a data sheet. b) Higher degree of multi-tasking
c) Lower error or glitches
290. Which of the following logic
d) Efficient memory management
families has the shortest propagation
delay? Answer: a
a) S-TTL Explanation: The Stand alone feature
b) AS-TTL of the ARM processors is that they‟re
c) HS-TTL economically viable.
d) HCMOS
293. ARM processors where basically
Answer: b designed for
Explanation: AS-TTL (Advanced a) Main frame systems
Schottky) has a maximum clock b) Distributed systems
frequency that is 105 MHz. So, the c) Mobile systems
propagation delay will be given by d) Super computers
1/105 sec which is the lowest one. It
Answer: c
is followed by S-TTL and HCMOS in
Explanation: These ARM processors
terms of increasing propagation
are designed for handheld devices.
delay.
294. The ARM processors don‟t
291. ARM stands for
support Byte addressability.
a) Advanced Rate Machines
a) True
b) Advanced RISC Machines
b) False
c) Artificial Running Machines
d) Aviary Running Machines

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Answer: b Answer: b
Explanation: The ability to store data Explanation: It is called so because it
in the form of consecutive bytes. performs its operation at the
assembly level.
295. The address space in ARM is
298. The fetch and execution cycles
24
a) 2 are interleaved with the help of
b) 264
c) 216 a) Modification in processor
d) 232 architecture
b) Clock
Answer: d
c) Special unit
Explanation: None.
d) Control unit
296. have been developed
Answer: b
specifically for pipelined systems.
Explanation: The time cycle of the
a) Utility software
clock is adjusted to perform the
b) Speed up utilities
interleaving.
c) Optimizing compilers
d) None of the mentioned 299. Each stage in pipelining should
be completed within
Answer: c
cycle.
Explanation: The compilers which are
a) 1
designed to remove redundant parts
b) 2
of the code are called as optimizing
c) 3
compilers.
d) 4
297. The pipelining process is also
Answer: a
called as
Explanation: The stages in the
a) Superscalar operation
pipelining should get completed
b) Assembly line operation
within one cycle to increase the
c) Von Neumann cycle
speed of performance.
d) None of the mentioned

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300. In pipelining the task which can reduce the speed of memory
requires the least time is performed access by a factor of 10.
first.
303. The periods of time when the
a) True
unit is idle is called as
b) False
a) Stalls
Answer: b b) Bubbles
Explanation: This is done to avoid c) Hazards
starvation of the longer task. d) Both Stalls and Bubbles

301. If a unit completes its task Answer: d

before the allotted time period, then Explanation: The stalls are a type of
hazards that affect a pipelined
a) It‟ll perform some other task in the system.
remaining time
304. The contention for the usage of
b) Its time gets reallocated to a
a hardware device is called
different task
a) Structural hazard
c) It‟ll remain idle for the remaining
b) Stalk
time
c) Deadlock
d) None of the mentioned
d) None of the mentioned
Answer: c
Answer: a
Explanation: None.
Explanation: None.
302. To increase the speed of
305. The situation wherein the data
memory access in pipelining, we
of operands are not available is called
make use of
a) Special memory locations
a) Data hazard
b) Special purpose registers
b) Stock
c) Cache
c) Deadlock
d) Buffers
d) Structural hazard
Answer: c
Answer: a
Explanation: By using the cache we
Explanation: Data hazards are

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generally caused when the data is not a) Orthogonal

ready on the destination side. b) Normalized
c) Determinate
306. The decimal numbers
d) None of the mentioned
represented in the computer are
called as floating point numbers, as Answer: b
the decimal point floats through the Explanation: None.
number.
309. constitute the
a) True
representation of the floating
b) False
number.
Answer: a a) Sign
Explanation: By doing this the b) Significant digits
computer is capable of c) Scale factor
accommodating the large float d) All of the mentioned
numbers also.
Answer: d
307. The numbers written to the Explanation: The following factors are
power of 10 in the representation of responsible for the representation of
decimal numbers are called as the number.
a) Height factors
310. The sign followed by the string
b) Size factors
of digits is called as
c) Scale factors
a) Significant
d) None of the mentioned
b) Determinant
Answer: c c) Mantissa
Explanation: These are called as scale d) Exponent
factors cause they‟re responsible in
Answer: c
determining the degree of
Explanation: The mantissa also
specification of a number.
consists of the decimal point.
308. If the decimal point is placed to
311. In IEEE 32-bit representations,
the right of the first significant digit,
the mantissa of the fraction is said to
then the number is called
occupy bits.

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a) 24 b) -256 to 255
b) 23 c) 0 to 255
c) 20 d) None of the mentioned
d) 16
Answer: a
Answer: b Explanation: Since the exponent field
Explanation: The mantissa is made to has only 8 bits to store the value.
occupy 23 bits, with 8 bit exponent.
315. In double precision format, the
312. The normalized representation size of the mantissa is
of 0.0010110 * 2 9 is a) 32 bit
a) 0 10001000 0010110 b) 52 bit
b) 0 10000101 0110 c) 64 bit
c) 0 10101010 1110 d) 72 bit
d) 0 11110100 11100
Answer: b
Answer: b Explanation: The double precision
Explanation: Normalized format is also called as 64 bit
representation is done by shifting the representation.
decimal point.
316. The DMA differs from the
313. The 32 bit representation of the interrupt mode by
decimal number is called as a) The involvement of the processor
for the operation
a) Double-precision b) The method of accessing the I/O
b) Single-precision devices
c) Extended format c) The amount of data transfer
d) None of the mentioned possible
d) None of the mentioned
Answer: b
Explanation: None. Answer: d
Explanation: DMA is an approach of
314. In 32 bit representation the
performing data transfers in bulk
scale factor as a range of
between memory and the external
a) -128 to 127

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device without the intervention of c) WMFC signal

the processor. d) None of the mentioned

317. The DMA transfers are Answer: b

performed by a control circuit called Explanation: The controller raises an
as interrupt signal to notify the
a) Device interface processor that the transfer was
b) DMA controller complete.
c) Data controller
320. The DMA controller has
d) Overlooker
registers.
Answer: b a) 4
Explanation: The Controller performs b) 2
the functions that would normally be c) 3
carried out by the processor. d) 1

318. In DMA transfers, the required Answer: c

signals and addresses are given by Explanation: The Controller uses the
the registers to store the starting
a) Processor address, word count and the status of
b) Device drivers the operation.
c) DMA controllers
330. When the R/W bit of the status
d) The program itself
register of the DMA controller is set
Answer: c to 1.
Explanation: The DMA controller acts a) Read operation is performed
as a processor for DMA transfers and b) Write operation is performed
overlooks the entire process. c) Read & Write operation is
performed
319. After the completion of the DMA
d) None of the mentioned
transfer, the processor is notified by
Answer: a
a) Acknowledge signal Explanation: None.
b) Interrupt signal

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331. The controller is connected to Answer: c

the Explanation: The controller takes
a) Processor BUS over the processor‟s access cycles
b) System BUS and performs memory operations.
c) External BUS
334. The technique where the
d) None of the mentioned
controller is given complete access to
Answer: b main memory is
Explanation: The controller is directly a) Cycle stealing
connected to the system BUS to b) Memory stealing
provide faster transfer of data. c) Memory Con
d) Burst mode
332. Can a single DMA controller
perform operations on two different Answer: d
disks simultaneously? Explanation: The controller is given
a) True full control of the memory access
b) False cycles and can transfer blocks at a
faster rate.
Answer: a
Explanation: The DMA controller can 335. The side of the interface circuits,
perform operations on two different that has the data path and the
disks if the appropriate details are control signals to transfer data
known. between interface and device is

333. The technique whereby the

a) BUS side
DMA controller steals the access
b) Port side
cycles of the processor to operate is
c) Hardwell side
called
d) Software side
a) Fast conning
b) Memory Con Answer: b
c) Cycle stealing Explanation: This side connects the
d) Memory stealing device to the motherboard.

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336. What is the interface circuit? Answer: b

a) Helps in installing of the software Explanation: The Interrupt-request
driver for the device line is a control line along which the
b) Houses the buffer that helps in device is allowed to send the
data transfer interrupt signal.
c) Helps in the decoding of the
339. The return address from the
address on the address BUs
interrupt-service routine is stored on
d) None of the mentioned
the
Answer: c a) System heap
Explanation: Once the address is put b) Processor register
on the BUS the interface circuit c) Processor stack
decodes the address and uses the d) Memory
buffer space to transfer data.
Answer: c
337. The conversion from parallel to Explanation: The Processor after
serial data transmission and vice servicing the interrupts as to load the
versa takes place inside the interface address of the previous process and
circuits. this address is stored in the stack.
a) True
340. The signal sent to the device
b) False
from the processor to the device
Answer: a after receiving an interrupt is
Explanation: By doing this the
interface circuits provide a better a) Interrupt-acknowledge
interconnection between devices. b) Return signal
c) Service signal
338. The interrupt-request line is a
d) Permission signal
part of the
a) Data line Answer: a
b) Control line Explanation: The Processor upon
c) Address line receiving the interrupt should let the
d) None of the mentioned device know that its request is
received.

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341. When the process is returned c) Real-time processing

after an interrupt service d) Multi-user
should be loaded again.
Answer: c
i) Register contents
Explanation: This forms an important
ii) Condition codes
part of the Real time system since if a
iii) Stack contents
process arrives with greater priority
iv) Return addresses
then it raises an interrupt and the
a) i, iv
other process is stopped and the
b) ii, iii and iv
interrupt will be serviced.
c) iii, iv
d) i, ii 344. A single Interrupt line can be
used to service n different devices.
Answer: d
a) True
Explanation: None.
b) False
342. The time between the receiver
Answer: a
of an interrupt and its service is
Explanation: None.
a) Interrupt delay 345. *@Ac# is a type of
b) Interrupt latency data.
c) Cycle time a) Symbolic
d) Switching time b) Alphanumeric
c) Alphabetic
Answer: b d) Numeric
Explanation: The delay in servicing of
an interrupt happens due to the time Answer: b
Explanation: Alphanumeric data
is taken for contact switch to take
consists of symbols. Alphanumeric
place. data may be a letter, either in
343. Interrupts form an important uppercase or lowercase or some
special symbols like #,^,*,(, etc.)
part of systems.
a) Batch processing 346. Which of the following is not a
b) Multitasking valid representation in bits?
a) 8-bit

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b) 24-bit Int is for the representation of

c) 32-bit integers, char is for strings and
d) 64-bit characters, float and double are for
floating point numbers whereas void
Answer: b is a valueless special data type.
Explanation: There are no criteria like
the 24-bit representation of 349. BOOLEAN is a type of data type
numbers. Numbers can be written in which basically gives a tautology or
8-bit, 16-bit, 32-bit and 64-bit as per fallacy.
the IEEE format. a) True
b) False
347. What are the entities whose
values can be changed called? Answer: a
a) Constants Explanation: A Boolean
b) Variables representation is for giving logical
c) Modules values. It returns either true or false.
d) Tokens If a result gives a truth value, it is
called tautology whereas if it returns
Answer: b a false term, it is referred to as
Explanation: Variables are the data fallacy.
entities whose values can be
changed. Constants have a fixed 350. What does FORTRAN stands for?
value. Tokens are the words which a) Formula Transfer
are easily identified by the compiler. b) Formula Transformation
c) Formula Translation
348. Which of the following is not a d) Format Transformation
basic data type in C language?
a) float Answer: c
b) int Explanation: FORTRAN is a type of
c) real computer language. It was developed
d) char for solving mathematical and
scientific problems. It is very
Answer: c commonly used among the scientific
Explanation: There are 5 basic data community.
types in C language: int, char, float,
double, void.

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351. The program written by the d) Data Objects

programmer in high level language is
called Answer: b
a) Object Program Explanation: Attributes can
b) Source Program determine how any location can be
c) Assembled Program used. Attributes can be type, name,
d) Compiled Program component, etc. Data objects are the
variables and constants in a program.
Answer: b
Explanation: The program written by 354. The decimal equivalent of the
the programmer is called a source binary number (1011.011)2 is
program. The program generated by
the compiler after compilation is a) (11.375)10
called an object program. The object b) (10.123)10
program is in machine language. c) (11.175)10
d) (9.23)10
352. A standardized language used
for commercial applications. Answer: a
a) C Explanation: Binary to Decimal
b) Java conversion is obtained by multiplying
c) COBOL 2 to the power of base index along
d) FORTRAN with the value at that index position.
1 * 23 + 0 * 22 + 1 * 21 +1*20 + 0 * 2-
1
Answer: c +1 * 2-2 + 1 * 2-3 = (11.375)10
Explanation: COBOL is a language Hence, (1011.011)2 = (11.375)10
used in business and commercial
applications. It stands for Common 355. An important drawback of
Business Oriented Language. It is binary system is
imperative, procedural as well as a) It requires very large string of 1‟s
object oriented language. and 0‟s to represent a decimal
number
353. define how the b) It requires sparingly small string of
locations can be used. 1‟s and 0‟s to represent a decimal
a) Data types number
b) Attributes c) It requires large string of 1‟s and
c) Links small string of 0‟s to represent a
decimal number

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d) It requires small string of 1‟s and d) (EF)16

large string of 0‟s to represent a
decimal number Answer: c
Explanation: (FE)16 is 254 in decimal
Answer: a system, while (FD)16 is 253. (EF)16 is
Explanation: The most vital drawback 239 in decimal system. And, (FF)16 is
of binary system is that it requires 255. Thus, The largest two-digit
very large string of 1‟s and 0‟s to hexadecimal number is (FF)16.
represent a decimal number. Hence,
Hexadecimal systems are used by 358. Representation of hexadecimal
processors for calculation purposes number (6DE)H in decimal:
as it compresses the long binary a) 6 * 162 + 13 * 161 + 14 * 160
strings into small parts. b) 6 * 162 + 12 * 161 + 13 * 160
c) 6 * 162 + 11 * 161 + 14 * 160
356. The decimal equivalent of the d) 6 * 162 + 14 * 161 + 15 * 160
octal number (645)8 is
a) (450)10 Answer: a
b) (451)10 Explanation: Hexadecimal to Decimal
c) (421)10 conversion is obtained by multiplying
d) (501)10 16 to the power of base index along
with the value at that index position.
Answer: c In hexadecimal number D & E
Explanation: Octal to Decimal represents 13 & 14 respectively.
conversion is obtained by multiplying So, 6DE = 6 * 162 + 13 * 161 + 14 *
8 to the power of base index along 160.
with the value at that index position.
The decimal equivalent of the octal 359. The quantity of double word is
number (645)8 is 6 * 82 + 4 * 81 + 5 *
a) 16 bits
80 = 6 * 64 + 4 * 8 + 5 = 384 + 32 + 5 =
b) 32 bits
(421)10.
c) 4 bits
357. The largest two digit d) 8 bits
hexadecimal number is
a) (FE)16 Answer: b
b) (FD)16 Explanation: One word means 16 bits,
c) (FF)16 Thus, the quantity of double word is
32 bits.

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1+0=1
360. What is the addition of the 1 + 1 = 0 ( Carry 1)
binary numbers 11011011010 and 111111
010100101? 101101
a) 0111001000 +011011
b) 1100110110
c) 11101111111 1001000
d) 10011010011
Therefore, the addition of 101101 +
Answer: c
011011 = 1001000.
Explanation: The rules for Binary
Addition are : 362. Perform binary subtraction:
0+0=0 101111 – 010101 = ?
0+1=1 a) 100100
1+0=1 b) 010101
1 + 1 = 0 ( Carry 1) c) 011010
d) 011001

11011011010 Answer: c
Explanation: The rules for Binary
+00010100101 Subtraction are :
0–0=0
11101111111 0 – 1 = 1 ( Borrow 1)
1–0=1
1–1=0
101111
-010101
a) 011010
b) 1010100
011010
c) 101110
d) 1001000
Therefore, The subtraction of 101111
Answer: d – 010101 = 011010.
Explanation:The rules for Binary
Addition are : 363. Binary subtraction of 100101 –
0+0=0 011110 is
0+1=1 a) 000111

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b) 111000 01001
c) 010101 010010
d) 101010 0000000
01001000
Answer: a 000000000
Explanation: The rules for Binary
Subtraction are :
0–0=0
0 – 1 = 1 ( Borrow 1)
Therefore, 01001 × 01011 =
1–0=1
001100011.
1–1=0
100101 365. 100101 × 0110 = ?
-011110 a) 1011001111
b) 0100110011
000111 c) 101111110
d) 0110100101
Therefore, The subtraction of 100101
– 011110 = 000111. Answer: c
Explanation: The rules for binary
364. Perform multiplication of the multiplication are:
binary numbers: 01001 × 01011 = ? 0*0=0
a) 001100011 0*1=0
b) 110011100 1*0=0
c) 010100110 1*1=1
d) 101010111 100101
x 0110
Answer: a
Explanation: The rules for binary 000000
multiplication are: 1001010
0*0=0 10010100
0*1=0 000000000
1*0=0
1*1=1 011011110
01001 _
x01011
Therefore, 100101 x 0110 =
_
011011110.

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366. On multiplication of (10.10) and accomplished using long division

(01.01), we get method.
a) 101.0010 1001)111101(11
b) 0010.101 1001
c) 011.0010
d) 110.0011 01100
1001
Answer: c
Explanation: The rules for binary 0111
multiplication are:
0*0=0
1001 = 0111.
0*1=0
1*0=0 368. CPU has built-in ability to
1*1=1 execute a particular set of machine
1 0.1 0 instructions, called as _
x 0 1.0 1
a) Instruction Set
1010 b) Registers
00000 c) Sequence Set
101000 d) User instructions
0000000
Answer: a
0 1 1.0 0 1 0 Explanation: An instruction is any task
which is to be performed by the
Therefore, 10.10 x 01.01 = 011.0010. processor. Instructions are stored in
the register. Instruction set is the set
367. Divide the binary numbers: of machine instructions.
111101 ÷ 1001 and find the
remainder 369. Opcode indicates the operations
a) 0010 to be performed.
b) 1010 a) True
c) 1100
b) False
d) 0011
Answer: a
Answer: d Explanation: Every instruction has an
Explanation: Binary Division is
opcode. Additionally, it may have one

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or more operands and the op code a) General Purpose Registers

indicates the operation to be b) Address Register
performed. c) Status Register
d) MAR
370. The length of a register is called
Answer: d
a) word limit Explanation: MAR or the memory
b) word size address register is not a visible
c) register limit register. This register is user
d) register size inaccessible. It contains the address
of the memory block to be read or
Answer: b
written to.
Explanation: The length of a register
is called word size. It tells the number 373. Which of the following is a data
of bits a register can store. transfer instruction?
Registers are a part of the CPU. a) STA 16-bit address
b) ADD A, B
371. The holds the
c) MUL C, D
contents of the accessed memory
d) RET
word.
a) MAR Answer: a
b) MBR Explanation: The instruction STA 16-
c) PC bit address is a data transfer
d) IR instruction.
STA means Store in Accumulator.
Answer: b
Explanation: The MBR holds the 374. What is correct instruction if you
contents of the accessed want the control to go to the location
(read/written) memory word. 2000h?
MBR stands for Memory Buffer a) MOV 2000h
Register. b) MOV A, 2000h
c) JMP 2000h
372. Which of the following is not a
d) RET 2000h
visible register?

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Answer: c 377. New CPU whose instruction set

Explanation: The JMP instruction is includes the instruction set of its
used to move to a particular location. predecessor CPU is said to be
In 8085 microprocessor, JMP with its predecessor.
statement tells the processor to go to a) fully compatible
location 2000h (here). b) forward compatible
c) compatible
375. What kind of a flag is the sign
d) backward compatible
flag?
a) General Purpose Answer: d
b) Status Explanation: The CPU is called
c) Address backward compatible since it
d) Instruction contains the instruction set of its
predecessor. Manufacturers tend to
Answer: b
group their CPUs into families having
Explanation: Sign flag is a type of
similar instruction set.
status register or the flag register. It
is used to indicate the sign of certain 378. What does ASCII stand for?
bits. a) American Standard Code for
Information Interchange
376. The number of sign bits in a 32-
b) American Scientific Code for
bit IEEE format
Information Interchange
a) 1
c) American Scientific Code for
b) 11
Interchanging Information
c) 9
d) American Standard Code for
d) 23
Interchanging Information
Answer: a
Answer: a
Explanation: There is only 1 sign bit in
Explanation: The ASCII codes are used
all the standards. In a 32-bit format,
to represent the bits into symbols
there is 1 sign bit, 8 bits for the
and vice versa. ASCII is the American
exponent and 23 bits for the
Standard Code which is used to
mantissa.
exchange information.

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379. The decimal representation for b) Symbols

the character „!‟ in ASCII is c) Bits
d) Bytes
a) 31
Answer: a
b) 32
Explanation: We refer to the digits
c) 33
and alphabets generally as
d) 34
characters. A character is generally a
Answer: c unit of information in computers.
Explanation: The decimal
382. The first 128 characters are the
representation of a few basic
same in both the types of ASCII i.e.
characters are:
ASCII-7 and ASCII-8.
33 : !
a) True
34 : ”
b) False
35: #
36 :$. Answer: a
Explanation: There are two types of
380. The two types of ASCII are
ASCII codes: ASCII-7 and ASCII-8.
and
ASCII-7 uses 7 bits to represent a
a) ASCII-4 and ASCII-8
number whereas ASCII-8 uses 8-bits
b) ASCII-8 and ASCII-16
to represent a number.
c) ASCII-7 and ASCII-8
d) ASCII-4 and ASCII-16 383. The number of characters that
can be represented in ASCII-8 are
Answer: c
Explanation: The two types of ASCII
a) 128
are ASCII-7 and ASCII-8. ASCII-7 uses
b) 256
7 bits for the representation of
c) 32
numbers and ASCII-8 uses 8-bits.
d) 64
381. Any set of digits or alphabets are
Answer: b
generally referred as
Explanation: ASCII-8 can represent
256 different characters. ASCII-8 uses
a) Characters

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8-bits for the representation of 386. Binary Coding for the letter X is
numbers i.e. it can represent 28 = 256
different characters. a) 01011000
b) 00111000
384. The zone of alphabetic
c) 10001000
characters from A to O in ASCII is
d) 00010100
a) 1000 Answer: a
b) 0100 Explanation: The binary coding for
c) 0010 the letter X is 01011000. Here, 0101
d) 0001 is the zone whereas 1000 is the digit.
The alphabets from P to Z have the
Answer: b
zone 0101.
Explanation: The zone used by ASCII
for alphabets is 0100. For e.g. A is 387. Express the ASCII equivalent of
represented as the signed binary number
0100(zone)0001(digit). The hex (00110010)2.
equivalent is 41 for A. The zone used a) 2
by numbers is 0011. b) 1
c) A
385. The representation of the
d) ,
number 8 in binary in ASCII-8 format
Answer: a
a) 00111000 Explanation: The ASCII characters for
b) 01001000 the remaining options are:
c) 1000 1 : 00110001
d) 00011000 A : 01000001
Answer: a , : 00101100.
Explanation: The ASCII-8 format will 388. Computer has a built-in system
have 8 bits. The zone for the clock that emits millions of regularly
character 8 is 0011 and the digit is spaced electric pulses per
1000. Therefore, its representation is called clock cycles.
00111000. a) second

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b) millisecond Installation of a device is done by the

c) microsecond system on its own.
d) minute
391. The number of clock cycles per
Answer: a second is referred as
Explanation: The regularly spaced a) Clock speed
electric pulses per second are b) Clock frequency
referred to as the clock cycles. All the c) Clock rate
jobs performed by the processor are d) Clock timing
on the basis of clock cycles.
Answer: a
389. It takes one clock cycle to Explanation: The number of clock
perform a basic operation. cycles per second is the clock speed.
a) True It is generally measured in
b) False gigahertz(109 cycles/sec) or
megahertz (106 cycles/sec).
Answer: a
Explanation: It takes exactly one clock 392. CISC stands for
cycle to perform a basic operation, a) Complex Information Sensed CPU
such as moving a byte of memory b) Complex Instruction Set Computer
from a location to another location in c) Complex Intelligence Sensed CPU
the computer. d) Complex Instruction Set CPU

390. The operation that does not Answer: b

involves clock cycles is Explanation: CISC is a large
a) Installation of a device instruction set computer. It has
b) Execute variable length instructions. It also
c) Fetch has variety of addressing modes.
d) Decode
393. Which of the following processor
Answer: a has a fixed length of instructions?
Explanation: Normally, several clock a) CISC
cycles are required to fetch, execute b) RISC
and decode a particular program.

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c) EPIC Answer: a
d) Multi-core Explanation: EPIC stands for Explicitly
parallel instruction computing. It has
Answer: b
a tighter coupling between the
Explanation: The RISC which stands
compiler and the processor. It
for Reduced Instruction set computer
enables the compiler to extract
has a fixed length of instructions. It
maximum parallelism in the original
has a small instruction set. Also has
code.
reduced references to memory to
retrieve operands. 396. MAR stands for
a) Memory address register
394. Processor which is complex and
b) Main address register
expensive to produce is
c) Main accessible register
a) RISC
d) Memory accessible register
b) EPIC
c) CISC Answer: a
d) Multi-core Explanation: The MAR stands for
memory address register. It holds the
Answer: c
address of the active memory
Explanation: CISC stands for complex
location.
instruction set computer. It is mostly
used in personal computers. It has a 397. A circuitry that processes that
large instruction set and a variable responds to and processes the basic
length of instructions. instructions that are required to drive
a computer system is
395. The architecture that uses a
a) Memory
tighter coupling between the
b) ALU
compiler and the processor is
c) CU
d) Processor
a) EPIC
b) Multi-core Answer: d
c) RISC Explanation: The processor is
d) CISC responsible for processing the basic
instructions in order to drive a

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computer. The primary functions of a 400. The 2‟s complement of 15 is

processor are fetch, decode and
execute. a) 0000
b) 0001
398. The value of base in a decimal
c) 0010
number system is
d) 0100
a) 8
b) 2 Answer: b
c) 10 Explanation: 2‟s complement is
d) 16 obtained by adding 1 to the 1‟s
complement of the number.
Answer: c
Here, Binary of 15 = 1111
Explanation: A decimal number
1‟s complement of 15= 0000
system consists of 10 digits from 0 to
2‟s complement of 15= 0000+1=0001.
9.
The definition of base describes it as 401. Another name for base is
a quantity to represent the number
of digits present in that particular a) root
number system. b) radix
Therefore, here, the base is 10. c) entity
d) median
399. Convert : (110)2 = ( )10.
a) 4 Answer: b
b) 5 Explanation: Another name for base
c) 6 is radix. Base refers to the number of
d) 9 digits that a particular number
system consists of.
Answer: c
The base of decimal number system
Explanation: The base 2 represents
is 10, binary is 2 and so on.
that the number is binary ,whereas,
the base 10 represents that it is to be 402. The decimal equivalent of
converted to the decimal format. (0.101)2 will be _
Conversion: 22 * 1 + 21 * 1 + 20 *0 = 6. a) 0.5
b) 0.625

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c) 0.25 Answer: a
d) 0.875 Explanation: In a binary number
system, the value of base or radix is
Answer: b
2. The binary system uses only two
Explanation: Since the base is 2 , it
digits for the representation of
could be easily guessed that the
numbers, therefore its base id has
number is binary. Conversion: 2-1 * 1
chosen to be 2.
+ 2-2 * 0 + 2-3 * 1 = 0.625.
405. The binary equivalent of the
403. Which of the following is not a
decimal number 10 is
positional number system?
a) 0010
a) Roman Number System
b) 10
b) Octal Number System
c) 1010
c) Binary Number System
d) 010
d) Hexadecimal Number System
Answer: c
Answer: a
Explanation: To get the binary
Explanation: The Roman number
equivalent of any number, we need
system isn‟t a positional number
to divide the number by 2 and obtain
system since it uses symbols to
the remainders as :
represent numbers.
The octal number system uses digits
from 0-7, the binary number system
uses digits from 0-1 whereas, the
hexadecimal number system uses We then write the remainders in the
digits from 0-15. reverse order as 1010 .
404. The value of radix in binary 406. A computer language that is
number system is written in binary codes only is
a) 2 a) machine language
b) 8 b) C
c) 10 c) C#
d) 1 d) pascal

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Answer: a i.e. 145.12 is the octal equivalent of

Explanation: Machine Language is the number.
written in binary codes only. It can be
408. The input hexadecimal
easily understood by the computer
representation of 1110 is
and is very difficult for us to
understand. A machine language,
a) 0111
unlike other languages, requires no
b) E
translators or interpreters.
c) 15
407. The octal equivalent of d) 14
1100101.001010 is
Answer: b
a) 624.12
Explanation: In hexadecimal number
b) 145.12
system, 1110 = 15, which is
c) 154.12
represented by the alphabet E.
d) 145.21
Some representations are:
Answer: b A 10
Explanation: The octal equivalent is B 11
obtained by grouping the numbers C 12
into three, from right to left before D 13
decimal and from right to left after E 14
the decimal place. F 15.
Here,
409. What could be the maximum
value of a single digit in an octal
number system?
a) 8
b) 7
c) 6
d) 5

Answer: b
Explanation: The maximum value in
any number system is one less than

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the value of the base. The base in an 412. The binary number 111 in octal
octal number system is 8, therefore, format is
the maximum value of the single digit a) 6
is 7. It takes digits from 0 to 7. b) 7
c) 8
410. In a number system, each
d) 5
position of a digit represents a
specific power of the base. Answer: b
a) True Explanation: Certain binary to octal
b) False representations are :
000=0
Answer: a
001=1
Explanation: In a number system,
010=2
every digit is denoted by a specific
011=3
power of base. Like in an octal
100=4
system, consider the number 113, it
101=5
will be represented as :
110=6
82 * 1 + 81 * 1 + 80 *3.
111=7.
411. The maximum number of bits
413. Convert (22)8 into its
sufficient to represent an octal
corresponding decimal number.
number in binary is _
a) 28
a) 4
b) 18
b) 3
c) 81
c) 7
d) 82
d) 8
Answer: b
Answer: b
Explanation: To convert an octal
Explanation: The octal number
number to decimal number:
system comprises of only 8 digits.
81 * 2 + 80 * 2 = 16 + 2 = 18.
Hence, three bits (23 = 8) are
Hence, the decimal equivalent is 18.
sufficient to represent any octal
number in the binary format. 414. What does the symbol D
represent in a hexadecimal number

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system? c) 7
a) 8 d) 8
b) 16
Answer: a
c) 13
Explanation: The hexadecimal
d) 14
number system comprises of only 15
Answer: c symbols: 10 digits and 5 symbols.
Explanation: The symbols A, B, C, D, E Hence, three bits (24 = 16) are
and F represent 10, 11, 12, 13, 14 and sufficient to represent any
15 respectively in a hexadecimal hexadecimal number in the binary
system. This system comprises of 15 format.
numbers in total: digits from 0-9 and
417. The binary number 1110 in
symbols from A to F.
hexadecimal format is
415. ABC is a valid hexadecimal
number. a) 6
a) True b) E
b) False c) 14
d) 15
Answer: a
Explanation: In a hexadecimal Answer: b
number system, alphabets are used Explanation: Certain binary to
for the representation of numbers hexadecimal representations are :
from 10 to 15. Here, A represents 10, 1010=A
B represents 11 and C represents 12. 1011=B
Therefore, it is a valid hexadecimal 1100=C
number. 1101=D
1110=E
416. The maximum number of bits
1111=F.
sufficient to represent a hexadecimal
number in binary:
a) 4
b) 3

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