HW1 - Short Channel Effects
Jorge Eduardo Angarita Pérez
MSc student in Electronic Engineering
Universidad Industrial de Santander
Bucaramanga, Santander
jorge2248431@correo.uis.edu.co
Abstract—With the evolution of CMOS manufacturing pro- These expressions, while providing an understanding of
cesses, it has been observed that transistors have become smaller general trends in transistor behavior, have shortcomings when
and smaller. Although this has made it possible to achieve higher making an accurate prediction of the electrical characteristics
speeds and implement more complex systems with less area, it
has made the modeling of the device more complicated, due to of the MOS transistor, which can be seen in Figure 1, where
the existence of different phenomena that alter its behavior. This the current of a 180nm technology transistor is plotted, in
report presents 5 different effects that affect the operation of the addition to the approximations mentioned above [3].
MOS when it has small dimensions, giving a brief description of
each phenomenon and its mathematical modeling.
I. I NTRODUCTION
One of the most basic models, which is nevertheless widely
used by industry and academia for modeling a MOSFET, is
based on defining its current for three different states: the
subthreshold, triode, and saturation regions [1]. These states
are defined by the relationships between the voltages VGS ,
VDS , and VT H , as shown in Equations 1, 2, and 3, respectively.
Subthreshold region (VGS < VT H ): The current in this
region follows an exponential behavior, given by Equation 1.
VGS −VT H
ID = ID0 e nVT
(1) Figure 1. Comparison of MOSFET current between theoretical models and
real measurements for a 180nm transistor [3].
where:
• ID0 is the threshold current,
Therefore, it is essential for the designer to consider a new
• n is the ideality factor,
set of factors that affect the devices used to ensure proper
kT
• VT = q is the thermal voltage.
circuit design. Some of these factors will be detailed in the
following section, which become more noticeable when the
Triode region (VDS < VGS − VT H ): In this region, the
transistor dimensions are reduced. This phenomenon is known
current depends linearly on VDS and is given by Equation 2.
as Small-Dimensions or Short-Channel Effects.
V2
W II. S MALL DIMENSION EFFECTS
ID = µn Cox (VGS − VT H )VDS − DS (2)
L 2 As the size of a transistor is reduced, it is common to
where: observe that many effects that were previously negligible,
such as fringe effects, become relevant in determining its
• µn is the electron mobility,
electrical characteristics. Most importantly, certain parameters
• Cox is the oxide capacitance per unit area,
that seemed fixed in the basic model (mobility, carrier velocity,
• W is the channel width,
or threshold voltage) actually depend on the voltages or
• L is the channel length.
dimensions of the device.
Saturation region (VDS ≥ VGS − VT H ): The current
in this region is independent of VDS in the ideal case but A. Carrier Velocity Saturation
can be affected by channel-length modulation, as shown in The current passing through a certain transverse region can
Equation 3. be determined by multiplying the net charge passing through
it by the velocity of the charge carriers, as expressed in
1 W
ID = µn Cox (VGS − VT H )2 (1 + λVDS ) (3) Equation 4 [1].
2 L
where λ is the channel-length modulation coefficient. I = Qv (4)
At the same time, the carrier velocity can be related to B. Channel Length Modulation (CLM)
the electric field strength over the channel using the mobility The phenomenon of channel modulation is perhaps one
parameter µ, as shown in Equation 5: of the best-known second-order effects when modeling a
MOSFET. In fact, it is the first short-channel effect to be
v = µE (5) studied, although it is not usually classified as such. This is
observed when the VDS voltage is greatly increased, causing
Although the above expression allows the electrodynamic the electrons to begin to saturate due to velocity near the drain
′
phenomenon to be modeled for most situations, it has a once VDS exceeds a certain threshold VDS . If the increase
limitation when the electric field strength becomes very large, continues, it will cause the channel length to decrease, as
typically on the order of 104 V/cm [2]. In this regime, the shown in Figure 3 [2].
relationship between velocity and electric field is no longer
linear but exhibits an asymptotic behavior, tending towards
a maximum drift velocity vd,max , which typically saturates at
values around 106 cm/s [2]. This behavior is illustrated in
Figure 2.
Figure 2. Velocity vs Electric Field [2].
Figure 3. Channel length modulation effect in a MOSFET [2].
By modelling this phenomenon mathematically, we arrive at
the following current expression, which accounts for velocity Taking into account this reduction of the effective channel,
saturation, as shown in Equation 6: an approximation of the current can be made using the
expression obtained for ID at velocity saturation, which is
IDS w/o Sat shown in Equation 9. Again, we can see how this effect
IDS V el Sat = (6)
1+ VDS becomes more pronounced as the channel length decreases
LECrit
[2].
It can be observed that velocity saturation becomes more
′ lp ′
noticeable when VDS ≫ LEc , which occurs, for instance, for IDS = IDS 1+ , VDS ≥ VDS (9)
small values of L. In this case, an approximation can be made, L
leading to the following expression for the drain current, as By performing a physical analysis of the problem, the
shown in Equations 7 and 8: following equation is obtained:
′
W
VDS − VDS
µCox L (VGS − VT )VDS lp = la ln 1 + (10)
IDS ≈ (7) VE
VDS /(LECrit )
where the parameter la is given by:
r
ϵs p
≈ W Cox (VGS − VT )µECrit , (8) la = tox dj ≈ 3tox dj (11)
ϵox
What stands out is the fact that the current does not depend And VE is another parameter that is usually less than 1V
on the length of the channel. and depends on several quantities associated with the transistor
and the channel. In addition, if this value is much larger than where µ0 represents the low-field mobility and θ is a fitting
′
the difference VDS − VDS , the current can be approximated parameter that depends on the oxide thickness [1].
by the following expression [2]:
′
′ VDS − VDS E. Hot Carrier Effects
IDS ≈ IDS 1 + (12)
VA As already mentioned, an increase in the electric field of
where VA is given by: the channel leads to saturation by the speed of the carriers,
but their kinetic energy will continue to increase [2]. If this
L increase becomes significant, we begin to refer to hot carriers,
VA = VE (13)
la which can cause the appearance of electrical effects. One of the
C. Drain Induced Barrier Lowering (DIBL) most notable is the appearance of a drain-bulk current, which
This effect is related to the fact that a high drain voltage, in occurs because the high-energy carriers end up hitting the
addition to causing pinch-off, can reduce the energy required silicon lattice atoms, creating new electrons/holes. Something
for conduction near this terminal. As a result, the barrier similar can happen in the silicon-oxide barrier, so a gate
potential decreases when the channel length is small, as shown current is also generated. These phenomena are illustrated in
in Figure 4 [4]. Figure 5.
Figure 4. Barrier potential reduction due to high drain voltage (DIBL effect).
This change results in a variation of the threshold voltage,
which is characterized by equation (14). The difference be-
tween Vth and the threshold for a long-channel device depends
on the gate length, as shown below:
Vth − Vth,long = − (Vds + 0.4V ) e−Lg /ℓd (14)
where ℓd , is approximated by equation (15):
1/3
ℓd ≈ (Toxe Wdep Xj ) (15) Figure 5. Hot carrier effects [2].
Finally, it should be noted that this phenomenon is charac- If VDS continues to increase further, the generated carriers
terized by the relationship in equation (16), which compares will gain enough energy to release additional carriers, leading
how much variation in VGS is necessary to maintain the same to an avalanche effect in the semiconductor region. This phe-
current Id . nomenon, known as channel breakdown, results in a significant
increase in the drain current ID , as shown in Figure 6 [2].
∆Vgs
DIBL = (16)
∆Vds III. OTHER E FFECTS
D. Mobility degradation A. Punchthrough Mechanism
Mobility degradation with vertical field occurs due to the Punchthrough is defined as a severe case of barrier lowering
high electric field developed between the gate and channel [1], that facilitates electron flow from the source to the drain.
which confines carriers to a narrow region below the oxide- This phenomenon can occur along the surface, known as
silicon interface. This confinement increases carrier dispersion surface punchthrough, or through the bulk, referred to as
and reduces mobility. As device scaling continues to deviate bulk punchthrough. Surface punchthrough occurs when the
from the constant field scenario, small geometry transistors depletion regions of the source and drain merge in the absence
experience significant mobility degradation. The effective mo- of any gate-induced depletion. Conversely, bulk punchthrough
bility, µeff , can be modeled by the equation 17. is distinguished by a "bottoming out" of the drain current ID
µ0 as the gate-source voltage VGS decreases, reaching a level that
µeff = (17) remains nearly constant even when the VGS is reduced [2].
1 + θ(VGS − VT H )
IV. C ONCLUSIONS
This article briefly discusses the different short-channel
effects in MOSFET transistors, emphasizing how most
of these effects show a dependence of various electrical
characteristics on the device dimensions (W and L) and
terminal voltages. This dependence becomes particularly
significant as the device dimensions decrease.By integrating
this knowledge with basic transistor models, a more accurate
description of transistor behavior, and consequently, circuit
performance, can be achieved.
R EFERENCES
[1] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill,
2017.
Figure 6. Channel breakdown effect on the current by Tsividis. [2] Y. Tsividis, Operation and Modeling of the MOS Transistor, Oxford
University Press, 2011.
[3] B. Murmann, Design Fundamentals (Basic sizing, OTAs, etc), Chipathon
2024.
B. Gate-Induced Drain Leakage [4] Stephen Remillard, “Drain Induced Barrier Lowering (DIBL) in Short-
Channel MOSFETs, Lecture 73,” Semiconductor Devices for VLSI
Large electric fields can induce band-to-band tunneling, (ENGS/PHYS 495), Fall 2020.
generating electron-hole pairs. The resulting electrons move
toward the drain, while holes contribute to the bulk current.
This leakage mechanism is known as gate-induced drain
leakage (GIDL), which is primarily observed in the drain cur-
rent. Additionally, trap-assisted tunneling can enhance GIDL,
leading to increased leakage currents, especially as the gate
bias decreases [2].
C. Polysilicon Depletion
Polysilicon is widely used for gate formation in modern
MOSFET technologies. Although it is often assumed to be
highly doped and behave like a metal, in many technolo-
gies the doping concentration is not high enough, leading
to accumulation, depletion, and inversion effects similar to
those in the body region. In NMOS devices, the repulsion
of negative charges in the body creates a depleted region in
the polysilicon gate adjacent to the oxide. This phenomenon,
known as polysilicon depletion or poly depletion, affects the
electrical behavior of the transistor [2].
D. DC Gate Current and Tunneling
CMOS technologies have evolved to support increased
MOS transistor currents and enhanced switching speeds, with
gate dielectric thickness being adjusted accordingly. However,
at smaller nodes, the oxide’s thinning may compromise its
ability to function as an effective insulator, introducing the
need for quantum mechanical analysis. Even in the absence
of sufficient kinetic energy, electrons exhibit a nonzero
probability of crossing the barrier, a phenomenon known as
tunneling. For oxides with a thickness greater than 4 nm,
tunneling can still occur through Fowler-Nordheim tunneling,
where electrons penetrate the triangular energy barrier and
reach the oxide’s conduction band [2].
