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Combinational Logic Circuits

The document outlines an experiment to construct various combinational logic gates using NOR gates, including NOT, OR, AND, and buffer gates. It details the objectives, necessary equipment, and step-by-step procedures for building and testing these circuits. The results indicate that NOR gates can effectively create any basic logic gate and discusses potential faults in circuit simulations.

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21 views5 pages

Combinational Logic Circuits

The document outlines an experiment to construct various combinational logic gates using NOR gates, including NOT, OR, AND, and buffer gates. It details the objectives, necessary equipment, and step-by-step procedures for building and testing these circuits. The results indicate that NOR gates can effectively create any basic logic gate and discusses potential faults in circuit simulations.

Uploaded by

cpt.price.australia
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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COMBINATIONAL LOGIC

CIRCUITS
NOR GATE CIRCUIT EXPERIMENT

Ahmed M. Jasim
Sara Q, Hassan
Alaa S. Ibrahim
Omar A. Yaseen
Ali Haidar
Abdulwadood

First course
2024/12/12
OBJECTIVE
Understanding how to construct other combinational logic gates using NOR gates

DISCUSSION
The symbol of a NOR gate is shown in Fig. 2-1. The Boolean expression for the NOR gate is
F=A+B; in de Morgan's theorem, F= A + B = A*B

When A=B, F=A+B A+A A. When B=0, F=A+B A+0=A. Therefore, the NOR gate can be
used to construct NOT: OR; AND: NAND; and XOR gates. We will attempt to construct
various logic gates in this experiment by connecting NOR gates in different ways.

FIG 2-1

EQUIPMENTS REQUIRED
KL-31001 DIGITAL LOGIC LAB; MODULE KL-33002

PAGE 1
PROCEDURES
1. U1A OF FIG. 2-2 (A) WILL BE USED TO CONSTRUCT A NOT GATE.
2. 2. CONNECT INPUTS A, B TO DATA SWITCHES SWO, SW1 AND
OUTPUT F1 TO LOGIC INDICATOR L1. SET SWO TO "0", OBSERVE
STATES OF F1 AT SW1="0" AND SW1="1"

DOES THE CIRCUIT ACT AS A NOT GATE?

3. INSERT A CONNECTION CLIP BETWEEN A AND B. CONNECT A


TO SWO AND F1 TO L1. WHAT IS THE STATE OF F1 WHEN SW0-0
AND SWO=1?

DOES THE CIRCUIT ACT AS A NOT GATE?

FIG2.2

USE U1A AND UTC TO CONSTRUCT A BUFFER SHOWN ON THE LEFT


SIDE OF FIG. 2-2 (C). INSERT CONNECTION CLIPS BETWEEN A~B; F1-A1;
A1-B1. CONNECT INPUT A TO SWO AND OUTPUT F3 TO L1 WHAT IS
THE STATE OF F3 WHEN SWO=0 AND SWO=1?

DOES THE CIRCUIT ACT AS A BUFFER?

PAGE 2
PROCEDURES

5. USE U1A AND U1C TO CONSTRUCT AN OR GATE SHOWN ON THE


RIGHT SIDE OF FIG. 2-2 (C). INSERT CONNECTION CLIPS BETWEEN F1-
A1 AND A1-B1. CONNECT INPUTS A TO SWO, B TO SW1, AND OUTPUT
F3 TO L1. FOLLOW THE INPUT SEQUENCES SHOWN BELOW AND
RECORD THE OUTPUT STATES IN TABLE 2-1.

INSERT CONNECTION CLIPS ACCORDING TO THE FIGURE BELOW.


THE CIRCUIT WILL ACT AS AN AND GATE.
(1) CONNECT A TO SWO; D TO SW1; F1 TO A1; F2 TO B1; F3 TO L1.
(2) FOLLOW THE INPUT SEQUENCES GIVEN BELOW, RECORD THE
OUTPUT STATES IN TABLE 2-2.

RESULTS
− 1. NOR gate can be used to construct just about any basic logic gate.

− 2. There are two ways to use NOR gate as an inverter. Since TTL gates have
higher current when the input is grounded, if TTL NOR gate is to be used as
an inverter, its two inputs should be connected together.

PAGE 3
FAULT SIMULATION

1. U1a and U1c are used as a buffer and the outputs stay in high
state. Try to locate all possible faults.

2. The outputs stay at low state when U1a and U1c are used as a
buffer. Try to locate all possible faults.

3. When U1a, U1b, U1c are used as an AND gate, the output F is
only affected by the input A. What could be the faults?

PAGE 4

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