A 6mW, 115GHz CMOS Injection-Locked

Frequency Doubler with Differential Output

Enrico Monaco1, Massimo Pozzoni2, Francesco Svelto3, Andrea Mazzanti3
1
Università degli Studi di Modena e Reggio E. and Istituto Universitario Studi Superiori di Pavia, Italy
2
STMicroelectronics, Pavia, Italy
3
Università degli Studi di Pavia, Italy

Abstract — A millimeter-wave CMOS frequency multiplier by

two (doubler) is reported. The circuit consists of a Pierce
oscillator injection-locked by a push-push pair. Compared to
traditional frequency multipliers, which exploit the non-linearity
of active devices to produce harmonics of the input signal, this
technique provides a differential output with balanced signals,
low core power dissipation and large swing. A model of the
circuit is proposed to derive a closed form expression for the
frequency locking range. Figure1. Voltage controlled oscillator followed by a
Prototypes of the frequency doubler have been realized in a 65nm
frequency doubler.
CMOS technology, show an operation bandwidth from 106GHz
to 128GHz, with 6mW core power dissipation. With 0dBm input A resonant output network selects the desired frequency
power, the output peak voltage swing, is 330mV, at 115GHz. component (e.g. 2nd harmonic for frequency doublers).
With CMOS devices, this technique suffers from low-
I. INTRODUCTION conversion gain or even loss and large input capacitance
The ever increasing speed of CMOS devices in ultra-scaled loading the VCO. Moreover, the multiplier output is typically
nodes enables new applications in the millimeter-wave single-ended not suited, in general, to drive high performance
frequency range. Around 60GHz, 7GHz of unlicensed monolithic mixers [6-8].
spectrum, have been allocated for gigabit/sec wireless We have recently presented a new topology of frequency
connectivity. Next generation of automotive radars will doublers, based on an injection locking technique, which
operate at 77GHz. Several CMOS transceivers realizations, provides differential output, large swing and low core power
tailored to these applications have been recently presented. dissipation. Combining the multiplier and a half frequency
Beyond 100GHz, envisioned applications include imaging VCO, we have realized a frequency generator showing 13.1%
systems for security, medical diagnostic, industrial control tuning range at 115GHz [9].
and chemical sensors. Still a long path toward complete This paper focuses on the frequency doubler, shown in figure
systems of any commercial interest is required, even though 2, describing the operating principle and detailed experiments.
simple building blocks in CMOS technologies have already The doubler alone, driven by an off-chip signal source, has
been presented [1-5]. been realized in a 65nm CMOS technology. It displays a
A major obstacle to low power high frequency transceiver
locking bandwidth ranging from 106GHz to 128GHz and a
realizations beyond 100GHz is due to the degradation, with
single-ended on-chip peak output swing, at the center output
increasing frequency, of key passive components on silicon
frequency, of 330mV, with a core power dissipation of 6mW
substrates. For frequency synthesis, adoption of Voltage
Controlled Oscillators (VCOs) at fundamental frequency sets only.
an increasingly severe trade-off between high spectral purity Section II describes the principle of operation. The circuit
and frequency tuning range due to a dramatic reduction of design is described in Section III while the experimental
varactors quality factor and large device parasitics. State of the results are presented in Section IV. Finally, Section V draws
art varactors-tuned VCOs beyond 100GHz, in standard CMOS conclusions.
technology, display a tuning range of less than 3%, not enough
to cover processing spreads[3-5]. II. FREQUENCY DOUBLER
An alternative approach, usually pursued with compound The proposed frequency doubler topology is shown in figure
semiconductor technologies, relies on a frequency multiplier 2. The circuit relies on sub-harmonic injection locking of a
driven by a VCO running at a lower frequency, as shown in differential oscillator. A Pierce oscillator is formed by the π-
figure 1. Circuits for frequency multipliers usually exploit the network (C-L-C) and transistor M1. Transistors M2’-2’’, are
non-linearity of active devices to generate harmonics of the connected as a push-push pair and inject a current in the
input signal. resonator node 1 at twice the input signal frequency to lock the
oscillator.

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 Figure 2. Schematic of the injection locked frequency
doubler.
Two current mirrors Mb, bias the core transistors
independently at constant DC current. Capacitors Cb are large
enough to behave as AC shorts. The supply to the circuit is
provided through a choke inductor (Lck) to the center tap of the
resonator. Notice that grounded capacitors are explicitly
required in each node of the circuit, for proper operation, and Figure 3. Amplitude and phase errors of the two outputs
absorb all the device parasitics, making the circuit particularly with and without CCM.
suited for a very high operation frequency.
Notice that, even if transistor M1 sets 180° between V1 and the where
current injected in the resonator node 2, the two ports of the π- 2
network are not driven symmetrically and the outputs are not ω0 = ; Q=ω0 RC (2)
LC
balanced. Capacitor CCM is introduced to suppresses the output
Under large signal operation, the magnitude of the current
common mode voltage (VCM). As an intuitive view, VCM is (Iosc) is constant while the phase is the same of the driving
shorted to ground by the low impedance provided by the series
voltage (ϕ1).
resonator formed by CCM and the L/2 branches. To gain
The operation of the circuit is captured by the following
quantitative insight on the effect of capacitor CCM, figure 3
system of equations, which links the two output voltages (in
shows the simulated amplitude mismatch and phase deviation
magnitude and phase) to the resonator impedances and
from 180° of the two outputs of the circuit in figure 2 with and
currents:
without capacitor CCM. Without CCM the amplitude and phase
mismatches, over a bandwidth of 20GHz around 115GHz, are ⎧⎪V1e jϕ1 = − ZT ⋅ I osc e jϕ1 − Z ⋅ I inj
up to 6dB and 30° respectively. When CCM is introduced, the ⎨ jϕ2 jϕ1 (3)
errors are suppressed down to about 1dB and 5° respectively. ⎪⎩V2 e = − Z ⋅ I osc e − ZT ⋅ I inj
The frequency locking range of the doubler can be estimated Solution of the system proves that the two outputs are
by the analysis of the equivalent circuit in figure 4. The push- balanced (e.g. |V1|=|V2| and ϕ2=ϕ1+ π), as expected, and
push locking pair is modeled by the current generator Iinj. The provides expressions for the output signal swing and the
voltage controlled current source represents transistor M1. The frequency locking range of the circuit (Δωmax). In particular,
resonator is represented by the π-network, characterized by the the latter is given by:
2x2 impedance matrix. Being the network passive a
symmetric, Z11=Z22=Z and Z12=Z21=ZT. Δωmax 1 I inj 1
By inspection, the following two simplified expressions for = (4)
the impedances can be derived: ω0 2Q I osc ⎛I ⎞
2

1 − ⎜ inj ⎟
R 1 ⎝ I osc ⎠
Z (ω ) ≈ From the above equation, given the tank quality factor, the
2 1 + j 2Q Δω (1) locking range increases by increasing Iinj/Iosc. Actually, when
ω0 designing the circuit, being the oscillation amplitude primarily
ZT (ω ) ≈ − Z (ω ) set by the oscillator core current, Iosc, the locking range is
determined by the magnitude of Iinj. Referring to the schematic
in figure 2, a larger Iinj is achieved either maximizing the
driving amplitude (Vi), the biasing current (I2) or the aspect
ratio of the push-push devices (M2’-2’’).

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 Figure 6. Photomicrograph of the test-chip.

Figure 4. Equivalent circuit of the Injection Locking

Frequency Doubler.

Figure 7. Measured input matching.

Figure 5. Schematic of the balun to make the input signal The locking signal at half the output frequency is provided by
differential. an off-chip millimeter-wave synthesizer. To make the signal
differential, a balun has been integrated. The schematic is
III. CIRCUIT DESIGN shown in figure 5. It is a lumped transformer where the
A test chip of the doubler has been designed, in a 65nm secondary winding, driving the doubler, resonates with the
CMOS provided by STMicroelectronics, targeting a center gate capacitance of transistors M2’-2’’ of figure 2 and an
output frequency of 115GHz. Capacitors of the resonator are explicit capacitor C2. Resistor R shunts the primary winding
device parasitics only. The center capacitor is also realized and the input pad and realizes the input signal termination.
with the gate capacitance of a dummy nMOS device. The The biasing voltage for the push-push pair (M2’-2’’) is provided
resonator inductor has been maximized for maximum output through the center tap of the secondary winding.
amplitude at given power consumption. It is a 80pH single For measurement purposes, the doubler drives a two stages
turn spiral of 2.6μm width trace, realized shorting together the buffer. The first stage is a pseudo differential common-source
two top-most Cu metal layers. Estimated quality factor is 15. amplifier with a resonant load while the second stage is an
The loaded resonator quality factor is much lower (~4). Losses open-drain differential pair, driving the 50Ω impedance of the
are primarily determined by series resistances of capacitors measurement setup and supplied off-chip with bias tees. The
(gate and bulk resistances) and output conductances of the power dissipation of the buffer is 17mW and the estimated
active devices. For maximum series impedance and self loss is 3dB.
resonance frequency, the choke inductor (Lck), which provides
the supply to the circuit, is realized as a 15μm diameter 3.5 IV. MEASUREMENTS
turns spiral of a thin trace in the topmost metal only. From A photomicrograph of the realized test-chip is shown in figure
electromagnetic simulations, the self resonant frequency of the 6. The core active area is 150μm x 180μm. For
two inductors is close to 200GHz. M1 is 20μm/65nm while characterization, dies have been glued on PCB. Supply and
M2’,2’’ are 10μm/65nm each one. Transistors sizes are biasing signals have been connected through wire bonding
relatively small, leading to a low capacitance (~15fF on each while the high frequency input and output signals are provided
input) loading the half-frequency signal source. The two with microprobes. Measured S11 at the input of the on-chip
biasing currents have been set equal to 3mA and supply balun is shown in figure 7. The minimum of S11 is at a
voltage is 1V. From simulations, assuming 300mV input frequency slightly lower than expected. However the balun
swing on each push-push transistor, the frequency locking provides a relatively good input matching over a broad
range is 18% while the single-ended peak output swing, at frequency range.
center frequency, is 340mV.

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 Ref. fout Conv. Gain Pdiss (core+buffer) Out.
[GHz] [dB] [mW]
[6] 27 1.5 10 s.e.
[7] 40 -15.8 4 s.e.
[7] 60 -15.3 4 s.e.
[8] 54 -0.45 9 (4+5) s.e.
This
115 6 23 (6+17) diff.
work
Table I. Performance summary and comparison against
CMOS doublers.

V. CONCLUSIONS
Frequency doublers are key building blocks for frequency
synthesis at millimeter-waves. Traditional circuit topologies in
Figure 8. Measured single-ended output swing. CMOS technology have poor performances leading to large
conversion loss and a single-ended output. In this work a new
circuit topology has been described. A pair of transistors,
arranged in push-push configuration, generates the 2nd
harmonic current component to lock a differential LC
oscillator. The circuit, provides a differential output and large
swing at limited core power dissipation. From experimental
results on a 65nm CMOS test chip, working a 115GHz, the
performances of the proposed solution compares favorably
against state of the art.

ACKNOWLEDGMENT
This work has been partially supported by Italian national
funding programs PRIN, contract # 2007B5RZLE and FIRB,
contract # RBA06L4S5.

REFERENCES
Figure 9. Amplitude difference between the two outputs. [1] S. T. Nicolson, A. Tomkins, K. W. Tang1, A. Cathelin, D. Belot, S. P.
Voinigescu “A 1.2V, 140GHz Receiver with On-Die Antenna in 65nm
CMOS’’, Proc. IEEE Radio Frequency Integrated Circuits Symposium,
The input signal is provided by an Agilent E8257G continuous pp. 229-232, 2009.
wave signal source, while the output signals have been [2] D. Huang et al. “Terahertz CMOS Frequency Generator Using Linear
Superposition Technique” IEEE J. of Solid-State Circuits, vol. 43, no.
monitored single-ended on a spectrum analyzer. An external 12, pp. 2730-2738, Dec. 2008.
compatible harmonic mixer has been adopted to extend the [3] C. Cao, K.K. O, ‘‘Millimeter-Wave Voltage-Controlled Oscillators in
bandwidth coverage of the spectrum analyzer. The measured 0.13μm CMOS Technology’’, IEEE J. of Solid-State Circuits, vol. 41,
single ended output power versus frequency, with a constant no. 6, pp. 1297-1304, Jun. 2006.
[4] P.-C. Huang, M.-D. Tsai, H. Wang, C.-H. Chen, C.-S. Chang, ‘‘A
input power of 0dBm, at half frequency, is shown in figure 8. 114GHz VCO in 0.13μm CMOS Technology’’, IEEE International
The doubler is locked over a frequency range spanning from Solid-State Circuits Conference, Digest of Technical Papers, pp. 404-
106GHz to 128GHz. The peak output power, at center 406, Feb. 2005.
frequency is -2.6dBm. Considering the loss of the buffer, the [5] C. Cao, K.K. O, ‘‘A 140-GHz Fundamental Mode Voltage-Controlled
Oscillator in 90nm CMOS Technology’’, IEEE Microwave and
estimated on-chip single ended voltage swing is about 330mV Wireless Components Letters, vol. 16, no. 10, pp. 555-557, Oct. 2006.
zero-peak, in good agreement with simulations. The estimated [6] F. Ellinger and H. Jäckel, “Ultra Compact SOI CMOS Frequency
peak voltage conversion gain, from the single-ended input of Doubler MMIC for Low Power Applications at 26.5–28.5 GHz”, IEEE
the balun to the differential output of the doubler is ~6dB. Microwave and Wireless Components Letters, vol. 14, no. 2, pp. 53-55,
Feb. 2004.
The measured amplitude matching between the two outputs, is [7] M. Ferndahl, B.M. Motlagh, H. Zirath, “40 and 60 GHz Frequency
shown in figure 9. With the available experimental setup, Doublers in 90-nm CMOS”, IEEE International Microwave Symposium
measurements of the phase difference of the two output Digest (MTT-S), vol. 1, pp. 179-182, Jun. 2004.
signals was not possible. On the other hand, the multiplier [8] D. Y. Jung, C. S. Park, “A Low-Power, High-Suppression V-band
Frequency Doubler in 0.13 μm CMOS”, IEEE Microwave and Wireless
provides very well balanced outputs, being the maximum Components Letters, vol. 18, no. 8, pp. 551-553, Aug. 2008.
amplitude difference, from figure 9, always below 1dB, i.e. [9] A. Mazzanti, E. Monaco, M. Pozzoni ,F. Svelto “A 13.1% Tuning Range
within the estimated accuracy of the setup. 115GHz Frequency Generator Based on Injection-Locked Frequency
Finally the experimental performances of the circuit are Doubler in 65nm CMOS”, IEEE International Solid-State Circuits
Conference, Digest of Technical Papers, Feb. 2010.
summarized in Table I and compared against recently reported
CMOS frequency doublers for millimeter-wave applications.

978-1-4244-5775-5/10/$26.00®2010IEEE 239 ICICDT-10