68000 Poclk<etbook

68000

Pocketbook

K"D . Peel
 SEPTEMBER 1986

No part of this publication may be copied, transmit-

ted or stored in a retrieval system or reproduced in
any way including but not limited to photography,
photocopy, magnetic or other recording means, with-
out prior permission from the publishers, with the
exception of material entered and executed on a
computer system for the reader's own use

COPYRIGHT © Glentop Publishers Ltd 1986

World rights reserved

Typeset directly from the publisher's w-p disks by

NWL Editorial Services, Langport, Somerset

][SBN 1 85181 045 5

Published by: Glemop Publishers Ltd

Standfast House
Bath Place
High Street
Barnet
Herts ENS SXE
Tel: 01-441-4130
 CONTENTS

Preface 9

General resources 11
The MC68000 family of microprocessors II
Data types 14
MC68000 data storage 15
The Internal register set 16
Condition codes 20
Organization of data in registers 22
Organization of data in memory 23
Address modes overview 24
Accessing program code in memory 25
Addressing modes 26
Register direct 26
Data register 26
Address register 28
Register indirect 30
Register indirect with postincrement 31
Register indirect with predecrement 32
Address register indirect
with displacement 33
Address register indirect with index 34
Special modes 35
Absolute short 35
Absolute long 36
Program counter with displacement 37
Program counter with index 38
Immediate data 40

5
 Immediate quick 40
Implied 41

Programming techniques 43
Stacks 43
User defined stacks 45
Access to system stack 46
Queues 47
Open ended 48
Circular buffer 49
Linked List 51
Add item to list 52
Remove item from list 53

Processing states 55
Normal 56
User state 56
Supervisor state 57
Exception processing 58
Multiple exceptions 59
Exception vectors 60
Reset 61
Interrupts 61
Bus error 62
Internal 64
Address error 64
Trace 64
Illegal instruction 65
Unimplemented instruction 66
Privileged instruction 66
Traps 66
Halted state 67

6
instruction summary 68
Instructions A to Z 68

Processor 98
Signal 1/0 98
Address bus 99
Data bus 99
Bus arbitration 99
Interrupt control 99
System control 100
Processor status 100

Appendices 103

Motorola MC68000 instruction encoding 105

Address modes 115

Encoding 115
Allowable types 117
Assembly language and BASIC equivalents 118

MC68000 instruction execution times 120

Processor series differences summary 125

Hexadecimal to decimal table 126

Instruction extensions, MC68010 Processor 127

Instruction extensions, MC68020 Processor 130
User programming model 132
Supervisor programming model 133
Virtual facilities 135
Virtual machine 135

7
 Virtual memory 136
Cache memory 137

Index 141

8
 Preface

The Motorola MC68000 series assembly language

pocket book provides essential programming inform-
ation for the MC68000 microprocessor, starting with
a brief overview of the series of microprocessors and
detailed explanations of the resources available to the
programmer: the register set, data types and the
many possible ways of addressing registers and mem-
ory. Descriptions of the state that the processor may
be in, normal, exception and halted, are given;
followed by the instruction set details in alphabetical
order, a brief resume of some essential 68000 series
programming techniques of stacks, queues and
linked lists, and the hardware signal I/O. Finally, the
appendices contain tables for encoding instructions
and addressing modes by hand, the relative execution
times of MC68000 series instructions, BASIC equi-
valents of the addressing modes, a table of the main
differences between the MC68000 series of devices,
and the additional instructions and facilities provided
by the MC68010 and MC68020 microprocessors.

Kathleen Peel
January 1986

9
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
 General
Resources
The MC68000 Family of
Microprocessors
There are currently four devices in the 68000 range
of 16/32-bit microprocessors, they are developments
from the earlier 8-bit Motorola 6800 and the highly
acclaimed 6809 microprocessors. The 68000 series is
designed to be compatible with the less expensive
and less sophisticated 8-bit synchronous peripheral
support chips as well as the more powerful asyn-
chronous 16-bit support devices. All the 68000 series
processors share the same 56 instruction types with
only a few minor variations; most instructions may
use anyone of 14 different addressing modes, provid-
ing a range of well over 1000 instructions. The very
much more powerful MC68020 can run virtually all
software written for the standard MC68000, but
because of its greatly improved performance, soft-
ware is best written specifically for it to gain max-
imum benefit.

MC68000:
The standard MC68000 microprocessor, housed in a
64-pin dual-in-line package, consists of 8 x 32-bit
data registers, 7 x 32-bit address registers, two 32-bit
11
stack pointers,a program counter that may address 16
Megabytes through 24 active address lines and a 16-
bit status register, all operating within a 32-bit
internal architecture. The processor has memory
mapped I/O and performs operations on bit, nibble,
byte, word and longword sized data. The processor
supports both a prioritized interrupt capability, 6
levels, and a non-maskable interrupt set by the
seventh level.

MC68008:
The MC68008 is housed in a smaller 48-pin package
that limits the addressing range to 1 Megabyte via 20
address lines and provides only three levels of inter-
rupt including the non-maskable interrupt. The data
bus is 8-bits wide and consequently the instruction
and data fetch operations from memory tend to take
twice as long as those of the 16-bit wide bus,
increasing the average program execution time by
about 30"0.

MC68010:
The MC6801O, packaged in the same 64-pin layout
as the MC68000, has a slightly increased instruction
set and is able to support external (not resident in
physical memory) data access - virtual memory.
There are three new registers, Vector Base Register
(32-bit VBR), Source Function Code register (3-bit
SFC) and Destination Function Code register (3-bit
DFC), supported by two new instructions MOVEC
(Move Control register) and MOVES (Move Altern-
ate Address Space). RTD performs return and deal-
12
locate, there is a 1'v10VE from CCR instruction and
MOVE from SR becomes privileged in the MC68010
instruction set. There is a very small 6 byte cache
memory facility, which can be used to produce
extremely fast loop timings using the DBRA
instruction.

MC68020:
The MC68020 is the most powerful of the current
range of Motorola 68000 microprocessors, retaining
all the capabilities of the MC68010, it has a full 32-
bit data and address bus and comes in a 114 pin
package. The MC68020 can address 4 gigabytes of
memory and has much better mathematical capabilit-
ies which include improved BCD operations, 64-bit
multiplication and divisions. An enhanced instruct-
ion set, with 62 addressing modes, include Check
Register with Bounds, Pack and Unpack BCD, Com-
pare and Swap, and Call and Return from Module.
The cache memory is increased in size to 256 bytes
capacity and there are also additional registers which
include a Master Stack Pointer and two extra active
bits in the system byte of the Status Register.

13
 Data Types
The MC68000 and MC68008 processors support
five different data types, in some instances instruct-
ions are limited to a specific data type, but mostly
there is a range of allowable types with the default of
word. Where the choice is not implicit, it is defined
in the instruction word extension as either byte, word
or longword.
Word
Byte, Word
MSB LSB
and Longword
Data Types
Hi order byte
Lo order Byte

31 23 15 o

t Byte t
t Hi mid order byte t Low Byte
High Byte La mid order byte
l
Longword
MSB LSB

Bit data
MSB LSB

Byte 17 1 1 14 1 1 1 10 1
~~
BCDO BCD 1

Most Significant Least Significant

BCD Byte BCD Byte

14
Motorola MC68000 Data
Storage
The Motorola MC68000 and MC68008 access two
internal locations for storage:

Internal registers: of which there are seventeen, store

data inside the microprocessor itself. They are very
limited in the amount of data they can store, but
provide extremely fast access.

External RAM/ROM data access is still quick, but

not as fast as the internal register data access.

External Internal registers

processor
Memory
I Data
registers I External data
storage
RAM
(Random Access
memory)
•• I l Address
registers

Program counter
J
I
(Hard/floppy
disks)

ROM
(Read only
I Status register I
memory)

Internal memory MC68000 processor

devices internal register layout

The MC68000 and MC68008 registers and memory layout

15
 The Register Set
The Motorola MC68000 series has seventeen 32-bit
registers, a program counter with 24 active address
lines in the MC68000 and 20 active lines in the
MC68008, and a 16-bit status register. Eight of the
32-bit registers (DO to D7) are used as data registers
for operations involving single bit, bcd (4-bit), byte
(8-bit), word (16-bit) and longword (32-bit) data.
The remaining nine registers are split in two, seven
(AO to A6) acting as address registers and two as
stack pointers. Only one Stack Pointer may be ac-
cessed at a time, hence the convention of calling both
A 7. The address register operations are based on
word and longwords only.

Data Registers

31 16 15 8 7 o
DO
Byte D1
D2
Eight
Word D3
Data
D4 Registers
Longword D5
D6
D7

Data storage of byte, word and longword is always

performed in the part of the data registers shown;
unused parts of registers are not altered.
16
Address Registers

31 16 15 8 7 o
AO
A1
Word A2
A3 Seven
Address
Longword A4
Registers
A5
A6
A7

The Address Registers are used as pointers to user

stacks, as base address registers and temporary
storage for computed addresses that are not to affect
the Status Register. Address storage is always perfor-
med in the part of the address registers shown.

When used as a destination operand, the entire

address is changed regardless of the operation size.
Address registers do /lot support byte sized oper-
ations as either a source or destination. Words are
sign-extended to longwords before an operation is
performed. When used to specify a memory location,
the value is limited to those address lines actually
available to output the memory address.
i.e.
MC68008 1 Mbyte (20 address lines)
MC68000 16 Mbyte (24 address lines)

17
Stack Pointer
31 o
User Stack Pointer A Two Stack
Pointers
Supervisor Stack Pointer 7

The User Stack Pointer typically saves subroutine

returns when in user mode. The Supervisor Stack
Pointer saves the Status register contents during
trap and interrupt routines as well as the supervisor
subroutine returns. Only one of the stack pointers is
addressable at a time, so they are both called A 7.
Bytes pushed on a stack are stored in the high order
half of a word.

Program Counter
31 x o

1000000 I Program
Counter

The Program Counter provides the MC68000

with an address range of 16 Megabytes (X=23) and
the MC68008 with 1 Mbyte (X = 19). As instructions
are based on word sized operands, the program
counter must always hold an even address, attempts
to address odd numbered locations will cause an
error trap.

18
 Status Register

15 8 7 o
Status
System User register

The Status register is split into User and System

bytes. The User byte is evaluated for the condition
codes used in the branching instructions. The codes
are affected by all instructions that alter the contents
of the data registers or memory, but not by changes
to the address registers.

Status Register User Byte - Condition Codes

liIi I Soc
X
I
I 4

E
X
N
E
Z
E
0
V
0

C
A
us.:d
T G R E R
E A 0 R R
N T F Y
D L
V 0
E \\"

Status Register System Byte

I
l'
Trace
mode
15 I X
l'
13

Supcn·isor
state
I X X

'=£1Interrupt
mask
9 I 8
I
J

x = bilS wJl used

19
 Condition Codes
The condition codes are set automatically after the
execution of an instruction, in a predefined manner.
Based on the condition codes,a jump or the setting of
a bit or byte may then be actioned. The condition
bits found in the User Byte of the Status Register
contain four codes and an operand for multi-precis-
ion computations:

USER BYTE

x x x E N z v c Ix = bits
1 - - - - ' ' - _........._---'-_ _. 1 . - _ - 1 ._ _1--_--'-_--'. 1l00used

Bit 0: Carry (C)

Set to a 1 if a binary subtraction produces a borrow
or a binary addition produces a carry. Otherwise the
carry bit is cleared.

Bit 1: Overflow (V)

Set to a 1 if two's complement arithmetic produces
an overflow otherwise it is cleared. The overflow bit
is also set if an arithmetic shift results in a change of
the MSB.

Bit 2: Zero (Z)

Set to 1 if the result of an operation is zero, otherwise
it is cleared to o.

20
Bit 3: Negative (N)
Only of value when dealing with signed numbers. Set
to 1 if an arithmetic, logical or shift operation
produces a negative result otherwise cleared to zero.
Follows the MSB of the operand regardless of size 8,
16 or 32 bit.

Bit 4: Extend (E)

This bit functions not as a condition code but as an
operand for multi-precision computations where it
acts as a carry bit. Used by ADD, SUBTRACT,
NEGATE, SHIFT and ROTATE instructions.

Condition Code Exceptions

Some instructions do not follow the generalized
criteria for setting the condition codes, notably the
Integer Arithmetic instructions. Therefore care must
be exercised in using these codes.

SYSTEM BYTE

T X I Ix
S x I;, I, I 'I x ~
I
' - _ ' - - _ - ' - ._--'._ _-'-_-'-._ _'-_-''--_0...... 'lOT
bilS
used

Bits 8 to 10:
Illterrupt Level Mask
The MC68000 has seven levels of interrupt (1 to 7);
zero is used to indicate that there is no interrupt
present. On completion of the current instruction,
higher level interrupts than the mask will be serviced
21
and the mask set to the level of the new interrupt.
Lower or equal levels of interrupt wait on completion
of the current interrupt. Level 7 interrupts are always
serviced regardless of the current mask level. The
MC68008 only services three levels of interrupt, 2
and 5 and the non maskable interrupt level 7.

Bit 13: Supervisor (S)

Bit 13 indicates whether the processor is in Super-
visor (set) or User state (cleared).

Bit 15: Trace (T)

Bit 15 controls the built-in debug facility of the
MC68000 series. When set the processor single-steps
through a program trapping to a user-written service
routine after each instruction. Registers, Addresses
and Memory may then be examined.

The unused bits in the Status Register are read as

zero; they are available for the expanded instruction
set used in the Motorola MC68020 microprocessor,
permitting upward compatibility with the existing
instruction set.

22
Organization of Addresses in
Memory

A
Memory
bottom

Any
Byte

M High byte
address

~
Even
address
+1
Longword
"" "'"
Low byte
+2
+3

Even
+- address
Word
+1

F Memory
top

For word and longword memory operations, the high

byte is on a word boundary (even address), the
following bytes are in order higher in memory.
By convention, system stacks grow downwards in
memory towards memory bottom.

23
 Addressing Modes
Overview
There are fourteen different addressing modes, made
up of six basic types of instruction. These are:

Register Direct:
Instructions referring to the data and address regist-
ers directly.

Register Indirect:
Instructions which use the contents of a register to
point to the required memory address. This may be
supplemented by automatic increase or decrease of
the register value, or extended with a l6-bit dis-
placement value or index register.

Absolute:
The absolute instruction uses a constant, which may
be either a word (± 32 KBytes) or longword to
provide an address in memory (up to 16 Mbytes
MC68000,1 Mbyte MC68008).

Immediate:
These instructions use a constant (byte, word or
longword) as the source operand. If the destination is
an address register, the data will be sign extended
and is limited to a word or longword only.

24
Program Counter Relative:
This instruction enables code to be written using
either a displacement (± 32K) or an offset (± 127)
and an index register(DO-D7, AD-A 7), that will work
irrespective of where it is located in memory (po-
sition independent code).

Implied:
Some instructions use internal registers without
specifically referring to them. BRANCH and JUMP
instructions alter the Program Counter, PEA affects
the Stack Pointer etc.

Accessing Program
Code in Memory
The operation words (instructions) are stored in
memory as words in a list of operation words that
form the machine code.

hI-ns-t"'-'n--=-1--! Low memory

OpWord
OpWord Inst'n 2 Block of
Op Word equivalent Inst'n 3 machine code
OpWord [0 Inst'n 4 in memory

High memory

25
Some instructions include additional data that is
located in the words (Operands) that immediately
follow the instruction. Data referring to the source is
located before data referring to the destination.

MOVE.L #4000,20000 Low memory

The prefix notation Op word

used is:
Immediate Source
# Immediate data data (#4000) operand
$ Hexadecimal
Abs.L (addr) Destination
There is no prefix 20000 operand
for absolute decimal
addresses. High memory

Addressing Modes
The effective address of the operand can be specified
in a wide variety of ways.

Register Direct Addressing

Data Register Direct

Used where one might wish to MOVE the contents
of the data register DO to the data register D 1.
(MOVE.B DO,D1). The ability of the Motorola
MC68000 series to handle bytes, words and long-
26
words requires that the user also specifies how much
of the data is to be moved. i.e:
MOVE.BDO,D1

Whele the. B in MOVE. B is referred to as the operand

size and may be:
· B for Byte
· W for Word, default if omitted
· L for Longword

MOVE is the operation word, sometimes referred to as

the op-code.

r------.--,..,,----, Data
MOVE.BDO,DI
L-------L---L-~DO
byte IRegister

MOVE. B DO, D1 moves byte from the low order byte

position of the data register DO to the low order byte
position of the data register D 1.

r -_ _ _ _-.-_-.-_....,Data

L-----~-~~-"DI
byte IRegister
IOpWord Single \X'ord Instruction

The operand is in the specified data register.

27
Address Register Direct
Address registers do not support byte sized operands
as either a source or a destination. If the previous
example had been to move the data into an address
register (AO) instead of a data register, then it would
be illegal. Operations using address registers as the
destination for data are limited to word and longword
operations only and affect the whole of the address
register; that is the data is sign extended.

MOVEA.WDl,AO
!
Iyxx word xx IDara
Register
01

MOVEA. WD1 . AO moves word from the word position

of data register D 1 to the word position of address
register AO. Data loaded into an address register is
sign extended and affects the whole of the address
register. Byte sized data movement is not permitted.

Address
Register
AO

sign-extend MSB of moved data

IOPWord Single \X'ord Instruction

The operand is in the specified data register.

28
Operations that use an address register as the destin-
ation do not affect the condition code flags. In
assembly language, address register direct destin-
ation instructions are given the notation MOVEA.
The 'A' implies an address register destination oper-
ation and can be appended to other instructions,
ADD, CMP etc.

The direct addressing modes are the simplest, either

fetching a piece data (operand) from the specified
data or address register and or loading the data back
into another data or address register.

29
 Register Indirect Addressing

Register Indirect
The contents of the specified address register are
used as a pointer to the address in memory where the
data is to be moved from if source and to if
destination.

Address
MOVE.W (AI ),DO yyy~ Register
Al

(AI). MOVE.W(AI),DO

~ -yyyy
+1
The word content of the memory

R at address yyyy is moved into the

data register DO

Data
IHighl Low I Register
DO

IOpWord I Single Word Instruction

The operand address is in the specified address

register.

There are four very powerful derivatives of indirect

addressing which enable the programmer to man-
ipulate tables, stacks, and arrays.

30
Register Indirect with
Postincrement
The contents of an address register point to a mem-
ory address. After execution of the current instruc-
tion, the address register contents are increased by
the size of the operand.

MOVE. \X' (A I, + ,(AO),

zzzz AO Address
I - - - -y- y-n -,- - - i Al Registers

Source Low wlcmory This instruction is typically used in a

(AI)

~
loop where Al points to the address yyyy
yyyy and AO points to address zzzz. The
Low
- -2
contents of yyyy are moved into address
zzzz and then both address registers arc

- +~
increased by the size of the operand, that
is:
I for a byte
2 for a word
4 for a longword
The effect of this is to set the pointers

D~ -
(AO)
HIgh zzzz ready to move the next piece of data. It is
Low not necessary for the programmer to

- +2 increment the pointers as it is done

automatically .
.. ~

If the stack pointer is one of the address registers,

then a minimum step size of the operand must be two
to keep the stack pointer at an even address.

OpWord Single \Vord Instruction (An)+

31
Register Indirect with
Predecrement
The address register contents are decreased by the
size of the operand before instruction execution, the
new value of the contents of the address register
point to the operand address.

MOVE.W -(AO),-(Al)

zzzz
1-----::y=Y):':,)C'".---I
IAAOI Address
Registers
1....-_ _..:...:...:..'-----'

~~
This instruction is typically used in a
High -2
loop where AO points to address zzzz and
Low
Al points to address yyyy, Both
zzzz addresses arc decreased by the size of the
(AO) operand, that is:
I for a byte

D~
2 for a word
High -2 4 for a longword
Low and then the data in the memory at
yyyy address zzzz-2 is moved into address
(AI) yyyy-2,
If the stack pointer is one of the address
registers, then only even addresses may
be used to keep the stack pointer aligned.

OpWord Single Word Instruction -(An)

The postincrement and predecrement addressing

modes besides being able to move blocks of data and
read tables, have another very important function,
that of manipulating stacks and queues.

32
Address Register Indirect with
Displacement
The content of the address register is added to the
displacement word and used to obtain the address of
the operand, the displacement is in the word that
follows the op word (instruction).

MOVE.W DO,IOO(AO)
~ _ _ _ _ _ _ _--. Address
yyy Register
An
The Register An contains a memory address yyy. The memory address
yyy is added to the displacement that is located in the word after the op
word. The result is the address of the operand.
Low memory
- Memory address
yyy (An)
This type of addressing mode is
vcry useful for reading and writing
lists and tables of system variables
displacement which move in memory. The
(100) address register contents usually
point to the start address of the
Operand table and the displacement gives the
offset of the required variable.
~

The displacement word has a possible range of

+ 32767 to -32768 bytes of memory. If the tables or
variables are word or longword data, then the range is
+ 16383 to -16384 words or 8191 to -8192
longwords.

Two Word Instruction deAn)

33
Address Register Indirect
with Index
The contents of the address register are added to the
displacement byte and the contents of an index
register, the result is the address of the operand. The
displacement and index are in the word that follows
the operation word (instruction).
MOVE.L DO,5(AO.D2.W)
Address
Register An contains a memory
yyy Register
address yyy. The memory address
An
yyy is added to the contents of the
index register (zzz) and to the Index Index
displacement value to provide the zzz Register
caleulated address of the operand. AnorDn

This type of addressing mode

Low memory
Memorvaddress enables the programmer to read and
~ yyy . (An) w.rite two dimensional arrays: The
base
dIsplacement byte has a possIble
range of + 127 to -128, the index
Index
register provides either word or
(Dn)
longword indexing by appending a
.W or.L after the index register.
The index and displacement are

Operand !Displacement
(5)
sign extended to evaluate the
effective address.

Two Word Instruction d(An+Ri) x = 0 Data register

x = 1 Address register

Operation Word

x I Reg. I y Iaaa I displacement y=O

y= I
.W Index
.L Index
15 14-12 11 10-8 7 a

34
 Special Addressing Modes
Absolute Short
The address of the operand is in the extension word
to the operation word and is sign-extended to 32 bits
before it is used, which gives the ranges:
MC68000
0-$7FFF (0-32767)
and
$FF8000-$FFFFFF (16744448-16777215)
MC68008
0-$7FFF (0-32767)
and
$F8000-$FFFFF (1015808-1048575)

The size extension to the operation word refers to the

size of the operand and not the size of the absolute
address.
Two Word Instruction
MOVE.B S4000,D2
MOVE.B 16384,D2

Moves the byte located at address 16384 into the low

order byte of data register D2.
I I

I Byte I~ Address 16384

(54000)

Data
IUnchanged byte Register
D2

35
Data registers as destinations permit the use of byte,
word and longword operands. Using an address
register limits the operation to a sign-extended word
or longword operand.

Absolute Long
The address of the operand is in the two extension
words that follow the operation word, giving access
to a range of addresses from 0 to 16 Mbytes for the
MC68000 and 0 to 1 Mbyte for the MC68008.

The size extension to the operation word refers to the

size of the operand and not the size of the absolute
address.

The absolute short addressing mode executes faster

than the absolute long addressing mode and is used
for making calls to the more frequently used parts of
memory (ROM). Absolute long could be used to
address the bottom 32K, but the instruction will take
longer to execute and use more space in memory.

Three word instruction

I---o;-~--I
L..-"":;;;;"'-----J
!
Operand
address
MOVE.BS1F7E8,03
MOVE.B 129000,03

36
Moves the byte located at address 129000 into the
low order byte of data register D3.

~ Address 119000
($IF7E8)

Data
I Unchanged byte Register
03

Data registers as destinations permit the use of byte,

word and longword operands. Using an address
register limits the operation to a sign-extended word
or longword operand.

Program Counter with

Displacement
The address of the operand is the sum of the program
counter contents and the displacement word follow-
ing the operation word. The content of the program
counter is the address of the displacement when
making the displacement calculation.

This instruction can be used to provide a branch or a

jump of ± 32 Kbytes from the current program
counter position and should be sufficient for most
displacement relative instruction needs. The instr-
uction is useful for writing position-independent
code with jumps and branches relative to the
37
 lvIOVE.W DO,100(PC) Program (PC)
Low memory I yyy Counter
.\lemory address
Op word ~ yyy (PC)
100

displacement
(100)

Operand

Program Counter. The displacement word has a

possible range of + 32767 to -32768 bytes of mem-
ory. If the tables or variables are word or longword
data, then the ranges are + 16383 to -16384 words
and + 8191 to -8192 longwords.

Opword Two word instruction d(PC)

displacement

Program Counter with Index

The contents of the program counter are added to the
displacement byte and the contents of an index
register, the result is the address of the operand. The
displacement and index are in the word that follows
the operation word. The content of the Program
Counter is the address of the extension word when
making the operand address calculation.

38
 .'vIOVE.L 00,5( PC.02. \Vl yyy Program Counter

zzz I Index Register An or On

"'iemory address
Or word yyy (PC)
indx I disp
Index (02)

f
Displacement
Operand
! (5)

This instruction provides the ability to read tables

within position-independent code. The index ext-
ends from the current program counter position to
the table start and the displacement points to the
required element.

The displacement byte has a possible range of + 127

to -128; the index register provides either word or
longword indexing by appending a .W or .L after the
index register and together with the displacement is
sign extended to a longword before the effective
address is evaluated.

Two Word Instruction d(PC+Ri) x = 0 Data register

x = 1 Address register

Operation Word

x I Reg. I I y 000
~~______L -__L -______L -__________~y=1
I displacement y=O .W Index
.LIndex

15 14-12 II 10-8
°
39
Immediate Data
The operand is the extension word of the operation
word and may be either longword, word or byte, that
is:

Three or Two LFord iusrl"llcrioll

This type of addressing is used to provide a constant

as a source operand. If the destination is an address
register the data is limited to word or longword and
the result sign-extended to longword affecting the
whole of the address register.

Note that the Immediate Addressing Mode cannot be

used as a destination operand. A shortened form of
the immediate addressing mode is immediate quick.

Immediate Quick
The operand is embedded in the operation word and
as a single word instruction can execute much faster
than the immediate equivalent.

Only three instructions are available in the 'Quick'

mode:

ADDQ and SUBQ which add or subtract integers

in the range 1 to 8;
and
40
MOVEQ which moves a value of + 127 to -128
(sign-extended to a longword) into a data register.

lop \X'ord Data S'iJ/J:le [fIord i1lS(l'lIcriCH/

Implied Addressing
Several instructions use registers that are not spec-
ifically mentioned in the operation word. For inst-
ance, conditional subroutine branches are relative to
the program counter and store a return address on
the stack. Other implied address instructions use the
status register as well as user and supervisor stacks.

Implied Addressing Instructions

"tuc.'l1/ouic /n:;(rllctioll Implied

Rl3uistcrs

Bee Branch Conditional PC

BRA Branch Always PC
BSR Branch to Suhroutine PC SP
CHK Check Reg Against Bounds SSP SR
DBee Decrement and Condo Branch PC

DIVS Signed Divide SSP SR

DIVU Unsigned Dividt.: SSP SR
JMP Jump PC
JSR Jump to Subroutine PC SP
LINK Link and Allocate SP

MOVECCR J\;lon~
Condition Codes SR
MOVESR Sratus Register
1\1.0\'C SSP
,\IOVE USP Move Ust:r Stack Pointer SSP

41
A11lel11Ollic /llslruClioll Implied
Registers

PEA Push Effective Address SP

RTE Return From Exception PC SP SR
RTR Return and Restore PC SP SR
Condition Codes

RTS Return From Subroutine PC SP

TRAP Trap SSP SR
TRAPV Trap On Overflow SSP SR
UNLK Unlink SP

logical CCR Logical Immediate to CCR SSP SR

logical SR Logical Immediate to SR SSP SR

** Privileged and Trap instructions affect the SSP

42
 Programming
Techniques
Stacks
A stack is a sequence of consecutive memory locat-
ions referenced by an address register, usually the
stack pointer, where a programmer can store inter-
mediate data, subroutine return addresses etc. that
are to be used later during the execution of a
program. If the stack pointer is used for storing
addresses then the stack must be implemented with
each address on an even boundary using either word
or longword sized data storage.
Low memory
G rowt h
i

High memory
Base

System stack growth is from high memory to low

memory by convention and data is pushed onto the
stack and pulled off.

The indirect address pre decrement instruction -(An)

pushes data onto the stack; the indirect address
postincrement instruction (An) + pulls data off.
After either operation the stack pointer points to the
top item on the stack (TOS).
43
System Stack

User Stack Pointer (USP)

Stack pointers
Supervisor Stack Pointer (SSP)

Both system stack pointers are referenced as A 7 with

only the user stack is accessible in user mode but the
programmer may access the user stack in supervisor
mode via a MOVE USP instruction. The default
system stack depends upon the setting of the S-bit of
the system byte part of the status register (bit 13).

Byte data on either of the system stacks is always

pushed onto a word boundary (even address) and
occupies the high byte of the word, the low byte of
the word is left unchanged. It is essential to keep the
stack properly aligned on word boundaries.

Low memory

7 o 15 8 7 o
E,"en -+ Byte Byte Byte Unchanged
address unchanged entry

HI byte Lo byte
E,"en -+ Hi Byte Word
address LoB)"tc entry

High memory

Presentation of stacked data in word and byte wide memory

44
In normal use subroutines push the program counter
return address onto the active stack, but during the
processing of a trap or interrupt, both the program
counter and the status register are saved on the
supervisor stack.

User-Defill1ed Stacks
The seven address registers (AO to A6) may be
employed as additional user stack pointers. User
defined stacks can be made to grow in either direc-
tion in memory, the indirect addressing modes with
postincrement and predecrement are specifically de-
signed to enable the programmer to handle stacks
and queues with the minimum of fuss and should be
used.
Addrcss
yyyy Register A6

PUSH
I.ow memory MOVE. WD5, - (A6)
Growth Consider using A6 as a pointer to a
Hi byte -2 user-defined stack. The contents of
La byte the register A6 arc decreased by the
Start yyyy operand size and the data in a
(A6) specified register (say 1)5) is placed
in rhe memory location given by the
nc\\' \"alue of A6 in high-low order.
PUl.L
I.ow memory MOVE. W (A6) + , D5
The contents of memory address
Hi byte 'yyyy pointed to by contents of A6 arc
La byte moved into the register D5. Then
Start +2 the value of address regisrcr A6 is
increased by the size of the
operand.

Unchanged High I Low Data registt:r 05

45
The operation of pushing data onto, and pulling data
from the stack, using the predecrement and post-
increment addressing modes respectively, leaves the
registers and memory exactly as they were prior to
execution of the instructions with the user defined
stack pointer always pointing to the last (top) item on
the stack.

Reverse Stacks
It may at some time be necessary to create a stack that
grows towards high memory, this is achieved using
the postincrement instruction to push data onto the
stack and the predecrement instruction to pull it back
off. After the operation, the user defined stack poin-
ter always points to the next free space on the stack.

Access to the System Stacks

The User Stack Pointer can be accessed while in
supervisor mode by using the privileged instructions
MOVE USP,An and MOVE An,USP.

46
 Queues
A queue may be used to hold serial data in its correct
sequence ready for dispatching to a printer, or stor-
ing data in a keyboard buffer etc. while the processor
is employed on another task. User defined queues
may take one of two forms, open ended or ring. In
the open ended queue, two address registers are used
to access it (assuming that we are using the normal
convention of stack growth from high to low mem-
ory); one points to the last entry at the head of the
queue while the other points to the start of free space
above the queue.

The open ended queue is formed by adding data to

the head of the queue and extracting data from the
tail which causes simple queues to 'travel' in mem-
ory. The queue may travel from high to low memory
or low to high memory but it will eventually reach
the limit unless precautions are taken to keep the
queue static.

The circular buffer, sometimes called a ring queue, is

employed to keep a queue within a fixed portion of
memory. This is achieved in normal queues which
grow from high to low memory, by entering or
removing an item and then checking that neither
address register has reached the lower limit of the
buffer. If it has, the buffer length is simply added to
the contents of the register. For queues required to
grow from low to high memory using indirect ad-
dressing with postincrement, the check on the upper
47
limit is made prior to entering or removing an item
from the queue. If the address register has reached
the limit, then the buffer length is subtracted from
the address register.

Opellll ellllded queue

Queue Entry and Exit

Address AS zzzz
Registers A6 yyyy

Enter Queue (Next entry)

MOVE.B05,-(A6)

The value of A6 is decreased by the operand size and

the data moved from D5 to the new address pointed
to by the new A6.

Low memory HEAD

Nexrcntry (A6)
Last entry Byte 4 yyyy
Byte 3
Byte 2
1st entry B te I (AS)
Free +- zzzz

High memory
Data IByte
Register
TAIL 05

48
Exit Queue (First entry)

MOVE.S -(A5) ,05

The value of AS is decreased by the operand size and

the contents of the new address given by AS moved
into DS.

Queue statistics
If AS = A6 then there are zero items In the queue
(queue empty).

AS-A6 = number of bytes in the queue:

divide by 2 for words,

divide by 4 for longwords.
A6 points to the last entry.
AS points to the start of free space above the queue,
AS-s points to next item to be removed from queue,
's' being the operand size,

The queue travels towards the bottom of memory.

The circlLdar bll.llffer

Circular Buffer

Address A5 zzzz
Registers A6 yyyy

49
 Low memory

10 limit
9
8
7 Last entry
6 Byte 5 +- yyyy (A6)

Byte 4
4 Byte 3
3 Bytc2
2 Byte 1 (AS)
Free +- zzzz
Start of
'--
free space
High
abovc queuc
!\1emory
Data
05 IByte Register

ENTER QUEUE

MOVE.BD5,-(A6)

The value of A6 is decreased by the operand size and

the data moved from DS to the new address pointed
to by A6. If A6 is less than or equal to the lower limit
then the buffer length is added to A6.

EXIT QUEUE

MOVEB-(A5),D5

The value of AS is decreased by the operand size and

the contents of the new address given by AS moved
into data register DS. If AS is less than or equal to the
50
lower limit address then the buffer length is added to
AS.

Queue statistics
If A5 = A6 then the queue is either empty or the
buffer is full; a running count of the items in the list
will determine which.

If AS> A6 then AS-A6 = Number of bytes in queue,

else: buffer length -(AS-A6) = Number of bytes in
queue

Linked Lists
Linked lists are used extensively within MC68000
machine code programs to produce extendible lists of
routines or data, which may be extensions to the
operating system, User or System Heap directories
etc. The lists all have one thing in common, the
ability to have items added or removed from the list.

Linked lists provide a means of stepping sequentially

from one routine or block of data in a list to another.
Further routines or data may be linked into or
removed from the lists, the items in the list may be in
any order in memory but will be performed in the
link sequence.
51
 A pointer to the list is normally situated
Pmr 1st Link in a table of variables and points (0 the
address of the the next item in the list.
Variables Table
l The first longword is the address of the
Addr next item
Addr of routine next item in the list. The second
An Item In longword is either the address of the
a Linked List linked routine or the start of the routine
depending upon the type of list being
considered.

The first longword is zero signifying the

j
end of the list.
()
Addr of routine The second longword is either the
Last Irc.:m In address ofthc linked routine or the start
Linked List ofthc routine depending upon which
type of list is being considered.

Add hem to Linked List

Items may be added to a linked list in any position by
replacing the current contents of the previous pos-
ition's link address pointer with the newly-linked
item's link address pointer and making the first
longword of the newly-linked pointer the original
contents of the previous link address.

52
 Variables table Variables table

Pntr I st Link
Replace
yywith Next add ptr xx
xx Routine addr 1st

Where address xx
is rhe location of Next add ptr Yl'
the new pointer Routine addr xx
in the linked list

Address yy Next add ptr zz

xx Routine addr yy

Old linked New Linked List

list With added item

Delete hem lFrom lUnked List

To remove an item from a linked list it is necessary to
know an address pointer link nearer the start of the
linked list than the item required to be removed. The
pointer usually provided, but not always, is the link
start pointer located in the variables table section of
link pointers.

The previous item in the linked list has its address

pointer changed from the item to be removed to the
address of the following item in the linked list.

53
 Variables table Variables table

Pntr 1st Link Pntr 1st Link

Next add ptr xx Replace Next add ptr yy

Routine add 1st xx with yy Routine add 1st

Routine xx to be deleted
Next add ptr yy from the linked list was
Routine add xx linked from above.

Next add ptr zz Address yy Next add ptr zz

Routine add yy Routine add yy

Old Linked List New Linked List

less deleted item

54
 Processing States
The Motorola MC68000 and MC68008 processor
are always in one ofthree states:

Normal: Executing a program.

Exception: Servicing an interrupt or trap

or
Halted: Caused by a catastrophic failure.

The relationship between each of the processes is

perhaps best seen in context with the aid of the
following diagram:

Processing States
I I I
Normal -, Exception Halted

IStopped
(Special
I
Interrupts
I
Caused by
Executing case) Traps and catastrophic failure.
Instructions Tracing c.g. (wo consecutive

I bus errors

1\
User
.........
Supervisor
/
Generated

/\
Internal External
Only Restart
by an external
reset

Illegal
Instructions
I
Instruction
or Operations Bus Error,
Interrupt
Error and Reset
Trap

55
The processes described in more detail are as follows:

Normal processing
This is defined as executing program instructions.
The stop instruction is a special case, stopping the
processor until a high-priority interrupt or external
reset restarts the processor.

The processor has two privilege states, User state and

Supervisor state.

User State
This is set when bit 13 (S-bit) of the status register is
set to zero, trace mode off and the user stack pointer
(USP) selected for the system stack (A 7). In the user
state certain privileged instructions are not accessible
(see following table) and cause a trap to privilege
violation exception processing.

Pri'vileged
Instructions Implications

AJ'.:OlroSR Instructions which modify the

EORI toSR status register arc privileged
ORI ro SR to ensure that the user docs not
MOVFca,SR enter the supervisor state
RTE except in a controlled manner.

MOVE An,USP These :lrc privileged as an aid

MOVEUSP,An to debugging operating systems

RESET Supervisor only functions

STOP

56
 Supervisor State
This sets the S-bit of the status register to '1' and
selects the supervisor stack pointer (SSP) for the
system stack (A 7). All instructions are available to the
programmer with traps to exception processing
caused by those items listed in the following table.

Typical Explal1arioll

Address Error Accessing system stack on an odd address

Illegal Instruction Using a non-existing operation code word
Divide By Zero Dividing by zero
CHK Instruction Outside upper limit
TRAPV Instruction Overflow condition

Changes of Operating State

User to Supervisor: Exception processing is the only
way to change from the user to the supervisor
operating state under software control. The change
may be effected by using one of the Traps and made
condititional on a limit or overflow. Hardware inter-
rupts provide a means of changing the operating state
via exception processing from external sources.

Supervisor to User: This is accomplished by modify-

ing the status register using one of the privileged
instructions:

MOVE to SR Fetch operand in supervisor mode

and execute instruction, fetch next
AND I to SR instruction in user state - the instruc-
57
EORI to SR tion simply setting the S-bit of Status
Register system byte.
or
RTE (Return from exception) Fetch old status
register and program counter from supervisor stack -
which returns the system to the status existing prior
to the exception which may have been either super-
visor or user state.

Exception Processing
Exceptions are caused by: an unusual occurrence in
processing an instruction, a specific request from
software to process an exception routine (both con-
ditional and unconditional), a request from an ex-
ternal device for control of the processor, or an
external error condition.

Generally the processing of an exception takes the

form of the following steps:

A temporary copy of the Status Register word is

placed in an internal register, the trace bit is cleared
and the S-bit set ready for exception processing.

If an interrupt caused the exception, the interrupt

mask is updated.
58
The exception vector address pointer is determined
from the exception vector assignment table.

The current processor environment is saved by push-

ing the Program Counter longword and then the
temporary copy of the Status Register word onto the
supervisor stack.

The environment is reconfigured for exception pro-

cessing by loading the Program Counter with the
vector routine address.

Exception processing commences. On completion of

the exception, the processor will return via the
mandatory RTE (return from exception) instruction.
RTE recovers the original Status Register and
Program Counter from the supervisor stack. Program
execution resumes in either User or Supervisor mode
dependent upon the state of the Status Register S-
bit.

The processor may even continue processing a lower

priority interrupt ...

Multiple Exceptions
Each type of exception has a priority level assigned to
it such that if two exceptions are met simultaneously,
the processor will serve in sequence that of higher
priority (0 = high, 7 = low priority).

59
Exceptio1l Parity Exception
Instruction Level Origin Stack

Reset 0 External Special case

Bus Error
Address Error 2
External
Internal
} See Bus error
stack later
Trace 3 Internal Low memory
Interrupt 4 External
Illegal Internal Status register
Privileged 6 Internal PC high
PC low
TRAP, TRAPV 7 Program
instructions
CHK,OIVIDE growth

Exception Vectors
Vector Address Exception Vector
Number Dec Hex Assigmllellt

0 0 00 Reset. Initialize SSP

Initialize PC
2 8 08 Bus Error
3 12 OC Address Error
4 16 10 Illegal Instruction
5 20 14 Zero Divide
6 24 18 CHK Instruction
7 28 lC TRAPV Instruction
8 32 20 Privilege Violation
9 36 24 Trace
10 40 28 Line 1010 Emulator (Type 10)
II 44 2C Line I I I I Emulator (Type 15)
12-14 48 30 (Unassigned, Reserved)
IS 60 3C Uninitialized Interrupt Vector
16-23 64 40 (Unassigned, Reserved)
24 96 60 Spurious Interrupt
25-31 100 64 Level I to 7 Interrupt
32-47 128 80 TRAP Instruction Vectors
48-63 192 CO (Unassigned, Reserved)
64-255 256 100 User Interrupt Vectors

60
 External Exceptions
The external exceptions can be detailed as follows:

Reset
Reset the system by initializing the supervisor stack
pointer (SSP) and the program counter (PC), acc-
ording to the first two longword contents of the
vector assignment table, and commence execution at
the PC address, normally system startup. This is the
only exception to the method of processing except-
ions.

The system status register byte is initialized to:

Supervisor Stack Pointer
Trace Off
Interrupt Mask 7

The reset input should not be confused with the reset

instruction which normally asserts the reset line to
reset external devices.

]Interrupts
Interrupts are requests from peripherals for pro-
cessor time; they wait for completion of the current
instruction before being evaluated for priority level.
Interrupts are then actioned according to the level of
priority supplied by the peripheral on the interrupt
control line, in the range of levels 1 to 7. Zero
61
indicates that there is no interrupt and 7 is a non
maskable interrupt. The MC68008 has a restricted
range of interrupt levels: 2, 5 and the non maskable
interrupt 7.
Again be careful not to confuse interrupt request
priority levels with exception priorities.

If the priority is greater than an existing interrupt

process then exception processing starts by saving
the status register, the S-bit is set, the T -bit is
cleared and the interrupt mask set to the level of the
new interrupt request, normal exception processing
then occurs.

If the priority is less or equal then the request is held

until completion of the current interrupt.

lUninitialized Interrupts provide a means whereby

a support chip will provide an identifiable vector
which is not supplied by the exception request
device.

Spurious interrupts enable separation of device

response errors from bus errors to permit normal
exception processing.

Bus error
This is initiated by an external device requesting to
process an error, which may be caused by incorrect
handshaking signals, illegal memory access etc., by
raising the Berr line in system control. Processing of

62
the current instruction is aborted and information on
the current environment saved on the supervisor
stack. A full recovery is unlikely due to the nature of
the entry into the exception processing state.

The supervisor stack is used to store:

The program counter, which is modified slightly by

adding an offset of between 2 to 10 to try and return
to a defined state after the exception processing.
Status register
Current Instruction Word, operand extensions are
discarded.
Address being accessed when error was flagged.
Whether a Read (1) or a Write (0) operation In
progress.
Whether peljorming an Instruction (0) or Not per-
forming an instruction (1).
The Function Code is saved to retain a copy of the
current operating state of the MC68000.

Low memory
IR'If' I fiN I FUllccion Codt:
Current address High Stack growth
--:-:-- .
being accessed Low i
Operation Word Supervisor Bus
Status Register Word Error Stack
Program High
Counter Low

63
 Internal Exceptions
Internally generated exceptions can be detailed as
follows:

Address error
These are initiated by an attempted access of an
instruction, word or longword at an odd address.
Processing of the current instruction is aborted and
information on the current environment saved on the
supervisor stack. A full recovery is unlikely due to
the nature of the entry into the exception processing
state.

The supervisor stack is used to store data in the same

format as for a bus error.

Trace
With the trace bit set, after the completion of each
instruction an exception is forced to the trace vector
routine, which may be used to monitor a program
under development.

If an instruction is not completed because of an

interrupt or exception, then the trace exception does-
not occur. One of the first activities of the exception
process is to switch off the trace T -bit, but on return
from the exception the original status register is
64
recalled and the trace bit will be re-initialised, unless
it is cleared prior to the RTE instruction.

The trace mode can effectively be used to add

breakpoints by testing the program counter against a
table of values and outputting the required inform-
ation if the addresses match.

JlUegali instructions
Illegal instructions are defined as those instruction
words which do not conform to the bit pattern of a
legal operation word.

There are three special cases of the illegal instruction:

Dec Hex
19194 #$4AFA
19195 #$4AFB

which are designated as being reserved for Motorola

system products, and

19196 #$4AFC

which is available to the programmer to force excep-

tion processing of an illegal instruction trap.

All other illegal instructions are reserved for extens-

ions of the instruction set.

65
 Unimplemented Instructions
There are two sets of operation word whose most
significant four bits (type 10 -1010 bit pattern and
type 15 -1111 bit pattern) are not referenced as
current operation words, these codes trap to separate
exception vectors and permit efficient access to user
programmed routines.

The routines may take the form of extending the

eXIsting instruction set by adding string handling
routines or floating point arithmetic etc.

Type 15 (bit pattern 1111) is used in the MC68020

for passing co-processor instructions.

Privileged Instructions
To provide system security, certain instructions are
privileged and can only be used in supervisor mode.
Any attempt to use a privileged instruction from user
mode causes 'an exception.

Traps
The sixteen forced exception traps available through
the TRAP instruction are usable as software inter-
rupts able to call routines capable of performing
operating system functions, debugging, interrupt
simulation and error conditioning.

There are also four program traps which cause an

exception subject to a condition:

66
TRAPV Trap on overflow
CHK Trap on negative or greater than limit
DIVU Trap on divide by zero
DIVS Trap on divide by zero

Hahed State
The processor enters the Halted state if it is deemed
that the system is in an unusable state. This will
occur when a bus error aborts the execution of one of
three exception processes:

Bus error, Address error or Reset

The result of aborting one of the above exceptions is

an indeterminate state from which there cannot
possibly be a recovery.

The halted state only stops the processor; no changes

are made to any memory locations. This provides a
possibility of software diagnosis of the error using an
external processor-driven device.

Recovery from the halted state can only be achieved

by externally asserting the RESET control line.

67
 Instruction
Summary
Each Motorola MC68000 instruction is presented,
many in terms of equivalent BASIC Instructions or
assembler routines. The similes are for clarification
of the use of each instruction; there is no access to the
data or address registers (Dn or An respectively) or
the condition codes from BASIC and therefore the
examples which make use of these registers, and most
of the effective address modes (ea), cannot be taken
literally.
Instructions
The following symbols are used throughout this section
asfollows:

&& bitwise AND

bitwiseEOR
II bitwise OR

ABeD: Add Binary Coded Decimal with Extend.

Add two byte-sized binary coded decimal numbers
and the Extend bit; a dollar sign is used to indicate a
BCD number. Clear the extend bit and set the zero
bit before performing this instruction which is
limited to byte-size data register operations; multi-
byte additions are performed more easily in memory.

68
BCD addition DA T A Register Memory
Addition Multibyte
Byte only Addition

$ 7 ABCD 00,01 MOVE #4,CCR

ABCD $ 6 ABCD - (AD) . - (A 1 )
$13 ABCD -(AD) ,-(Al)
ABCD - (AD) . - (A 1 )
$27
ABCD $16
$43

Note that the z-flag is cleared if the result is non-

zero, otherwise it is unchanged. Formemory ad-
ditions, the data must be stored with the most
significant digit lower in memory and the address
pointers initially set to the byte above the low order
BCD digit in memory, as the only available address-
ing mode is predecrement.

ADD: Add two integers. One of the integers must be

the contents of a data register.

LET Dn"Dn + ea ADD ea, On

LET ea"ea + On ADD On, ea

Use ADD ea, Dn where the destination is a data

register.
Use ADDA where the destination IS an address
register.
Use ADD I or ADDQ where the source is immediate
data.
69
ADDA: Add the contents of the effective address to
the contents of the destination address register.

LET An=An + ea ADDA ea,An

ADlD][: Add a constant value to the contents of the

destination effective address.
Use ADDQ for speed and small integers.

LET ea=ea + 999 ADD! #999,ea

AlDDQ: Add a constant in the range of 1 to 8 to the

contents of the effective address.
Faster addition than ADD I.

LET ea=ea + 8 ADDQ #8,ea

AlDlDX: Add either register to register, or pre de-

cremented memory to memory, with extend.
Use of the extend bit enables multi-precision arith-
metic to be performed, the extend bit acting as a
carry between successive operations.
Data register addition
Add two 64 bit integers
DO_DI and D2_D3
Memory additions La_Hi respectively

ADDX -(Ay) ,-(Ax) * ADD.L DO,D2 Low bits

LET Ay=Ay-4 ADDX.L D1 ,D3 High bits
LET Ax=Ax-4
POKE(Ax) ,PEEK(Ax) + PEEK(Ay) + X
70
 Memory addition

MOVE #4,CCR
ADDX.L - (AO) , - (A 1 )
ADDX.L - (AO) , - (A 1) etc.

* X infers the Extend bit

Note that the z-flag is cleared if the result is non-

zero, otherwise it is unchanged, For memory ad-
ditions first clear the Extend bit and set the Zero flag.
The data must be stored with the most significant
digit lower in memory and the address pointers
initially set the operand size above the low order digit
in as the only addressing mode is predecrement.

AND: AND the source operanc'. to the destination

operand.
The source AND data is normally used either (a) as a
mask enabling a portion of the destination operand to
be examined (bits are masked by 1's in the source); or
(b) to clear bits by setting the corresponding bit in
the source to a zero.

LET ea=Dn && ea AND Dn,ea

LET Dn=src && On AND ea,Dn

If src=3, then AND src keeps bits 0 and in Dn

only, the others are set to zero.
Use AN D e a , Dn where the destination is a data
register.

71
Use ANDA where the destination is an address
register.
Use AN DI where the source is immediate data.

ANDI: ANDI the immediate data to the destination

effective address.

LET ea~data && ea ANDI.W #512.DO

Keep bit 9 of word only

AND! to CCR: AND I the data to the condition code

register.

LET CCR~26 && CCR AND! #26.CCR

Normally bits can be tested via the condition codes

without using the AND function as a mask. Here it is
used to zero a bit position where there is a zero in the
AND data; that is zero and carry (bits 0 and 2 in the
CCR) are cleared.

AND! to SR: ANDI the data to the status register

This is a privileged instruction and attempted access
while in user mode will trap to the privilege violation
exception vector.

LET SR~63743 && SR AND! #63743.SR

Set the interrupt mask level to zero and leave un-

changed the condition code and system flags.

72
ASlL: Arithmetically Shift Left the bits of the
operand.
The last MSB shifted sets the carry and extend bits;
the LSB is set to zero each shift. The overflow bit is
set if the sign is changed during the shift and is used
to flag a change of sign. The carry bit is cleared if the
shift count is zero. The instruction is used for fast
multiplication of *2 and *4; other values should use
MULS.

~---[. 4 10
LET ea"ea • 2 ASL ea (shift 1)
LET Dy"Dy • (2ADx) ASL Dx.Dy (reg modulo 64)
LET Dy"Dy • (2A5) ASL #5.Dy (shift 1 to 8)

ASR.: Arithmetically Shift Right the bits of the

operand.
The MSB sign bit is retained; the last LSB shifted is
used to set the carry and extend bits. The carry bit is
cleared if the shift count is zero. This instruction can
be used for rapid integer division by 2, 4, 8 of signed
numbers; use DIVS for other divisions.

sign bit d±==:::9:::j--[§

LET ea"INT(ea/2) ASR ea (shift 1)
LET Dy"INT(Dy/(2ADx) ASR Dx.Dy (reg modulo 64)
LET Dy"INT(Dy/(2A5) ASR #5.Dy (shift 1 to 8)

73
Bee: Branch on condition. A two's complement
displacement from the current program counter po-
sition (Instruction address + 2) + 126 to -128 for a
short branch or + 32766 to -32768 for a word branch
operation, the condition xx may be:
EQ Equal To CS Carry Set GT Greater Than
NE Not Equal CC Carry Clear LTLcssThan
MI Minus VS Overflow GE Greater Than or Equal
PL Plus VC No Overflow LE Less Than or Equal
HI Higher Than
LS Lower Than 2's Compleme1lt
or same Arithmetic

IF On • a THEN GOTO yy BEQ #14

IF On > a THEN GOTO label BGT label

BeHG: A bit is tested and its state reversed. If the

bit was zero before the test; that is clear, then the
Zero flag is set, otherwise it is cleared.

IF BITn~O

THEN set Z flag:

ELSE clear Z flag BCHG #6,ea (data mod 8)
lET BITn~1-BITn BCHG On,ea (reg mod 32)

BCLR: A bit is tested and then cleared, If the bit was

zero before test; that is clear, then the Zero flag is set,
otherwise it is cleared,

IF BITn~O

THEN set Z flag:

ELSE clear Z flag BClR #6,ea (data mod 8)
lET BITn~O BClR On,ea (reg mod 32)
74
BR.A: BRanch Always. A two's complement dis-
placement branch either of + 126 to -128 bytes by a
single word instruction or of + 32766 to -32768 bytes
by a two-word instruction from the current program
counter position (instruction address + 2).

GOTO label BRA label

GOTO 1275 BRA #8

BSET: A bit is tested and then set. If the bit was

zero before the test; that is clear, then the Zero flag is
set, otherwise it is cleared.

IF BITn"O
THEN set Z fl ag:
ELSE clear Z flag BSET #6.ea (data mod 8)
LET BITn"1 BSET Dn.ea (reg mod 32)

BSR: Branch to SubRoutine. Either a two's comple-

ment displacement of + 126 to -128 bytes by a
single-word instruction, or of + 32766 to -32768
bytes by a two-word instruction, from the current
program counter position (instruction address + 2).
Return to the next instruction via an RTS from the
subroutine.

GOSUB 1abe 1 BSR label

GOSUB 1275 BSR #8

BTST: A bit is tested. If the bit was zero; that is

clear, then the Zero flag is set, otherwise the Zero flag
is cleared.

75
IF BITn=O
THEN set Z flag: BTST #6,ea (data mod 8)
ELSE clear Z flag BTST Dn,ea (reg mod 32)

CHK: Check a data register low-order word against

the two's complement upper bound of the source
operand. If the register value is less than zero or
greater than the test value, then jump to the CHK
Trap exception vector.

IF Dn > ea OR CHK ea,Dn

Dn < 0 THEN GOSUB chk trap

Cl.R.: Clear an operand sets all or part of a specified

address or register to zero.

LET ea=O CLR ea

MOVEQ #0, Dn is quicker than CLR.L Dn.

SU BA. L An, An is quicker for memory applic-
ations.

CMP: The compare instructions are used exclusively

to set the condition code registers for a subsequent
conditional operation. The comparison is made by
subtracting the source operand from the destination
operand and setting the condition codes accordingly;
neither operand is altered by the instruction.

CMP
IF ea=Dn THEN GOTO loop BEQ loop

76
Use CMPA when the destination is an address
register.
Use CMP I when the source is immediate data.
Use CMPM for memory to memory comparisons.

CMPA: Subtract the source operand from the ad-

dress register and set the condition code flags accord-
ingly. The comparison is based on a sign-extended
source if it is a word operand. The address register is
not altered.

CMPA ea.Dn

CMPI: Subtract the immediate operand from the

effective address operand and set the condition code
flags accordingly. Neither operand is altered. Use
TST for comparing with zero as it is much quicker.

CMPI #999.ea

CMPM: Subtract the contents of the memory ad-

dress pointed to by the source address register from
the contents of the memory address pointed to by the
destination register and set the condition code flags
accordingly. Increase the value of both address regis-
ters by the size of the operand (1, 2 or 4 byte word
and longword respectively).

The main use for this instruction is comparing

strings

77
LET Dn~length string -1
loop loop CMPM (Ay)+. (Ax)+
IF PEEK(Ay)<>PEEK(Ax) BNE not_same
THEN
Ay~Ay + s:Ax~Ax + s DBRA Dn. loop
GOTO not same
ELSE same
Ay~Ay + s:Ax~Ax + s

LET Dn~Dn -1
IF Dn<>-1 THEN GOTO loop

same

not same not same

s = operand size
Dn = character count

DlBcc:Test the condition and exit loop to the next

instruction if the condition is met. If the condition is
not met, then decrement the low order 16 bits of the
count data register. If the count becomes -1, then
exit loop and carryon with the next instruction,
otherwise branch the two's complement displace-
ment of the following word -32766 to + 32768 from
the current program counter position (instruction
address + 2). The test may be one of the following:

78
EQ Equal To CS Carry Set GT Greater Than
NE Not Equal CC Carry Clear LT Less Than
MI 1\1inus VS Overflow GE Greater Than or Equal
PL Plus VC No O\'erflow LE Less Than or Equal
HI Higher Than
LS Lower Than 2's Complement
or same Arithmetic

DBEQ DO, loop BEQ pass

SUB #1, DO
(Equivalent) BPL loop
pass

DBT: Always branches and is of little use.

DBRA: Sometimes written DBF, it makes the

branch based on the data register count only and
branches when the count reaches -1. Therefore the
count should be initialised to the required count less
one. If the loop is entered via a jump or branch at the
DBcc instruction, then the count is the required
count and usefully an initial zero count will cause an
immediate exit from the loop.

DJ[VS: Sign Divide a 32-bit data register destination

operand by a 16 bit source operand and store the
integer result in the lower 16 bits of the destination
register. The remainder is stored in the upper 16 bits
of the destination and keeps the dividend sign.
Division by zero causes a jump to the Divide-by-
Zero Trap exception vector. On overflow, the result
is larger than 16 bits, the V -flag is set and the
operation terminated without affecting either
operand.
79
LET Dn=Dn / ea DIVS ea,Dn

AS Rea is a fast signed divide by two

MOVEQ #2,D2
ASR D2,Dx
is a quicker divide by four

Generally use DI VS and DI VU for division by a prime

number, otherwise think of an alternative as the
division instruction, because of its general nature, is
not quick.

DIVU: Unsigned arithmetic divide of a 32-bit data

register destination operand by a 16-bit source
operand. The integer result is stored in the lower 16
bits of the destination register and the remainder in
the upper 16 bits. Division by zero causes a jump to
the Divide-By-Zero exception vector. On overflow
the result is larger than 16 bits, the V -flag is set and
the operation terminated without affecting either
operand.

LET Dn=Dn / ea DIVU ea.Dn

EOR: EOR the data register source operand to the

contents of the destination operand. The source EOR
data is normally used to invert the state of a bit or
bits.

LET ea=Dn " ea EOR Dn.ea

If Dn = 3, then bits 0 and 1 in the effective address

80
are inverted.
Use EO RI where the source is immediate data.
There is no memory to data register operations.

EORI: EORI the immediate data to the destination

effective address.

LET ea=data " ea EORI.B #16.DO

Invert bit 4 of DO

EORI to CCR: EORI the immediate data to the

condition code register.

LET CCR=4 " CCR EORI #4.CCR

Toggle the Zero flag

EORI to SR: EORI the immediate data to the status

register. This is a privileged instruction and attem-
pted access while in user mode will cause a trap to the
privilege violation exception vector.

LET SR=8192 •• SR EORI #8192.SR

Toggle the supervisor bit

EXG: Exchange the longword contents of two regis-

ters. Referred to in many BASICs as SWAP, which
has a different meaning in the MC68000 instruction
code.

81
LET tmp=DO: DO=D1 : D1 =tmp EXG DO.D1
LET tmp=AO:AO=A1 :A1=tmp EXG AO.A1
LET tmp=DO:DO=AO:AO=tmp EXG DO.AO

EXT: Sign-extend a data register contents. A byte to

a word or a word to a longword, to permit operations
involving mixed size data to take place.

EXT Dn

llLLEGAlL: The illegal instruction causes the pro-

cessor to jump to the illegal instruction trap excep-
tion process subroutine.

GOSUB Ill_Trap ILLEGAL

JMP JSR: JMP and JSR are long forms of BRA and
BSR. The main difference is the jump instruction's
ability to access any part of memory whereas the
branch instructions are limited to a relative
± 32 Kbytes jump.

JMP: Jump to a routine in memory specified by the

effective address, either absolute or relative to the
current program counter position.

GOTO ea JMP ea

J§R: Jump to a subroutine in memory specified by

the effective address, either absolute or relative to the
current program counter position

GOSUB ea JSR ea
82
lLEA: Load Effective Address loads a calculated
effective address into an address register. The cal-
culated address can be the sum of two registers, one
must be an address register, and a displacement
which provides the addition of two registers and a
displacement without affecting either register, in a
single instruction.

LET An=Start_of_text address LEA text.An

LET An=Start_of table LEA tabl.An

LET AD=Al + D2 +64 LEA 64(Al.D2) ,AD

lLlINK: LINK enables a block of memory, part of the

stack, to be temporarily reserved for a specific pur-
pose. Typical examples might be an index table, a
text string, an array etc. The space is recovered when
the requirement has passed.

DIM A(64) LINK An.#-64

Saves a block of 64 bytes in memory. The original

value of An is preserved on the stack and will be
recovered on UNLK. The current value of An is the
start of the data space which may be most easily
accessed via indirect with displacement or indirect
with index addressing modes.

lLSlL: Logically Shift Left the bits of the operand.

The MSB sets the carry and extend bits, the LSB is
set to zero. The carry bit is cleared if the shift count
is zero.
83
 LET ea=ea * 2 LSL ea (shift 1)
LET Dy=Dy * (2.Dx) LSL Dx.Dy (reg mod 64)
LET Dy=Dy * (2,5) LSL #5.Dy (shift 1 to 8)

LSR: Logically Shift Right the bits of the operand.

The MSB is set to zero and the LSB sets the carry
and extend bits. The carry bit is cleared if the shift
count is zero.

LET ea=INT(ea/2) LSR ea (shift 1)

LET Dy=INT(Dy/(2.Dx) LSR Dx.Dy (reg mod 64)
LET Dy=INT(Dy/(2.5) LSR #5.Dy (shift 1 to 8)

MOVE: Move the byte, word or longword contents

of the source effective address to the destination
effective address.

MOVE ea.ea
LET D1=DO MOVE DO.D1
LET SP=SP-4:POKE(SP).D7 MOVE D7.-(SP)
POKE(SP) .D7:LET SP=SP+4 MOVE (SP)+.D7

Use MOVEA where the destination is an address

register.

84
MOVE from SR: Save the word contents of the
status register in the effective address register or
memory location. Be careful as this instruction is
privileged in the MC68010 and MC68020 instruc-
tion sets, programs should try not to use it in user
state.

MOVE SR.ea
MOVE.W SR,OO

MOVE to CCR: Move the contents of the source

operand word into the condition code register. Only
the low-order byte is used; the upper byte is ignored.

MOVE ea,CCR
MOVE #4.CCR

Set the Zero flag and clear all others.

MOVE to SR: Move the contents of the source

operand into the status register. This is a privileged
instruction and attempted access while in user mode
will cause a trap to the privilege violation exception
vector.

MOVE ea.SR
MOVE #1792,SR

Clear all flags, set user state, and set interrupt mask
to level seven.

85
MOVE USP: Move the contents of the user stack
pointer to or from the specified address register. This
is a privileged instruction and attempted access while
in user mode will cause a trap to the privilege
violation exception vector.

LET A3=USP MOVE USP.A3

LET USP=A3 MOVE A3,USP

MOVEA: Move the contents of the source effective

address to the destination address register. Byte-
sized operations are not permitted.

LET A3=PEEK_W(192) MOVEA.W 192,A3

LET AO=PEEK_L(4) MOVEA.L 4,AO

MOVEM: Move multiple registers to or from mem-

ory, permits the transfer of a block of specified
registers to and from memory in a predetermined
sequence by one instruction.

LET A7=A7-4:POKE_L(A7) .00 MOVEM.L #57344,-(A7)

LET A~=A7-4:POKE_L(A7) ,01
LET A7=A7-4:POKE_L(A7) ,02
MOVEM.L (A7)+.#1860

These instructions save registers DO, D 1 and D2:

MOVEM.L # 7.24(A7)
MOVEM.L #57344,-(A7)

86
These two instructions recover registers DO, D 1 and
D2:

MOVEM.L 24(A7) ,#7

MOVEM.L (A7)+,#7

** The pre decrement mode of addressing values the

registers in reverse order for the register list mask
(DO_bit 15, A7_bit 0), permitting push-on, pull-off
on a last in-first out basis,

MOVEP: Move data to or from a data register and

alternate bytes in memory, Enables the MC68000 to
interface with 8-bit peripheral devices. The data is
transferred on either the high half of the data bus
D8-DlS, even addresses, or the low halfDO-D7, odd
addresses, to memory occupying alternate bytes in
the processor's memory map. The data is transferred
in high-low order.

POKE_W(7+65536) ,On MOVEP On,d(Ay)

LET On=PEEK_W(7+65536) MOVEP 7(Ay) ,On

This is the only instruction that provides word and

longword access at odd addresses.

MOVEQ: Move sign-extended 32-bit immediate

data in the range of + 127 to -128 to a data register. A
fast means of loading small positive and negative
integers into a data register.

LET 00=0 MOVEQ #0,00

87
MULS: Multiply two signed 16-bit operands. Only
the low-order 16-bits are used from both operands
for the multiplication, the result being the 32-bit
product in the destination data register.

MULS ea.Dn

AS Lea is a fast signed multiply by two.

MUlLU: Multiply two unsigned 16-bit operands.

Only the low-order 16-bits are used from both
operands for the multiplication, the result being the
32-bit product in the destination data register.

MULU ea.Dn

NBCD: Negate Decimal with Extend subtracts the

destination byte-sized operand and the extend bit
from zero using decimal arithmetic.

NBCD ea

Extend bit clear, the ten's complement is produced.

Extend bit set, the one's complement is produced.

NEG: Negate subtracts the destination operand from

zero, producing the two's complement of a byte,
word or longword operand.

NEG ea

NEGX: Negate with extend subtracts the destination

operand and the extend bit from zero, producing the
88
two's complement of a byte, word or longword
operand.

NEGX ea

NOP: No OPeration has no effect other than to

increment the program counter by 2. Its use is
generally either for creating a space in code which
may be used later on for adding a subroutine call, for
writing text etc. or for deleting parts of code, especi-
ally test routines, without the need for recompiling.

NOP

NOT: Logically complement, producing the one's

complement of the operand.

NOT ea

OR: Or the source to the contents of the destination

data register. The source OR data is normally used to
set specific bits of an operand.

LET On~src II Dn OR ea.Dn

If s rc = 3, then OR s rc sets bits 0 and 1 in On; the

other bits are left unchanged.
Use OR ea, On where the destination is a data
register.
Use 0 RI where the source is immediate data.

ORK: ORI the immediate data to the destination

89
effective address.

OR! . W #51 2 , 00
LET ea"data II ea

Set bit 9 of word, others unchanged

OR! to CCR: ORI the data to the condition code

register.

OR! #5,CCR

OR is used to set bit positions; that is Zero and Carry.

Bits 0 and 2 in the CCR are set, the others are
unchanged.

ORI to SR: ORI the data to the status register.

LET SR"1792 I I SR OR! #1792,SR

Set the status register interrupt mask to level seven,

all other conditions unchanged. This is a privileged
instruction and attempted access from user mode will
cause a trap to the privilege violation exception
process routine.

PEA: Push effective address pushes a longword-

computed address onto the current stack. It is useful
for passing parameters to a subroutine which are
accessed via an address register indirect with dis-
placement instruction and removed from the stack
prior to return if necessary.

90
 PEA param
JSR sprag
Access parameter sprag MOVEA.L 4(SP) ,AO
Tidy stack MOVE.L (SP)+,(SP)

RTS
RESET: Reset external devices by asserting the reset
line, There is no effect on the processor other than an
increase of two in the value of the program counter.
This is a privileged instruction and attempted access
while in user mode will cause a trap to the privilege
violation exception vector.

RESET

ROL: Rotate without extend Left. The MSB is

rotated to the LSB and the carry; the other bits are
shifted up one. The carry bit is cleared for a shift
count of zero.

RDL ea (shift 7)

: RDL Dx.Dy (reg modulo 64)

RDL #5.Dy (shift 1 to 8)

ROR: ROtate without extend Right. The LSB is

rotated to the MSB and the carry; the other bits are
shifted down one. The carry bit is cleared for a shift
count of zero.
RDR ea (shift 1)
RDR Dx.Dy (reg modulo 64)
RDR #5.Dy (shift 1 to 8)

91
ROXL: ROtate with eXtend Left. The MSB is
rotated to the extend bit and the carry, the extend bit
is rotated to the LSB and the other bits are shifted up
one. The carry bit is cleared for a shift count ofzero.

~ .
~

ea (sh i ft 7)

II
ROXL
ROXL Ox.Oy (reg modulo 64)
ROXL #5.0y (shift 7 to 8)

ROXR: ROtate with eXtend Right. The LSB is

rotated to the extend bit and the carry, the extend bit
is rotated to the MSB and the other bits are shifted
down one. The carry bit is cleared for a shift count of
zero.

ROXR ea (shi(t 7)
.. ROXR Ox.Oy (reg modulo 64)
ROXR #5.0y (shift 7 to 8)

RTE: Return from Exception. The status register

and the program counter are pulled from the current
(supervisor) stack. This instruction is privileged and
attempted access while in user mode will cause a trap
to the privilege violation exception vector.

(SP)+,SR
(SP)+,PC

RTR: Return and Restore. The condition code;"and

then the program counter are pulled from the current
stack.

(SP)+,CCR
(SP)+,PC
92
RTS: Return from Subroutine. The program coun-
ter is pulled from the current stack.

(SP)+.PC

SHeD: Subtract Decimal with Extend. Subtract a

byte-sized binary coded decimal number and the
extend bit from the destination operand byte using
decimal arithmetic and store the result in the destin-
ation location.

Memory Multibyte
BCD subtraction subtraction

SBCO s 7 SBCO 527

$ 6 ..2..l&. MOVE #4.CCR
S 1 $11 SBCO 00,01

Note that the z-flag is cleared if the result is non-

zero, otherwise it is unchanged. For memory ad-
ditions the data must be stored with the most signifi-
cant digit lower in memory and the address register
pointers initially set to the byte above the low-order
BCD digit. The only memory addressing mode is
predecrement.

See: Set according to condition. The specified con-

dition is tested and the byte specified set to all ones if
true or all zeros if false. The condition may be:
EQ Equal To CS Carry Sct GT Greater Than
NE Not Equal CG Carry Clear L T Less Than
MI Minus VS Overflow GE Greater Than or Equal
PL Plus VC No Overflow LE Less Than or Equal
HI Higher Than LS Lower Than 2's Complement Arithmetic
or same
93
STOP: Load the status register and Stop. The
immediate operand is put into the status register and
the program counter advanced to the next instruction
and then stopped. Execution only resumes when a
trace, interrupt or reset exception occurs.

STOP #7

SUB: Subtract the source from the destination. One

of the integers must be the contents of a data register.

LET On~On-ea SUB ea. On

LET ea~ea-On SUB On. ea

Use SUB ea, On where the destination is a data

register.
Use SUBA where the destination IS an address
register.
Use SUBI or SUBO where the source is immediate
data.

SUBA: Subtract the contents of the effective address

from the contents ofthe destination address register.

LET An~An - ea SUBA ea,An

SUB][: Subtract a constant value from the contents of

the destination effective address.
Use SU BO for speed and small integers.

LET ea~ea - 999 SUB] #999.ea

94
SUBQ: Subtract a constant of from 1 to 8 from the
contents of the effective address. Faster subtraction
than SUB 1.

LET ea=ea - 8 SUBQ #8.ea

SUBX: Subtract either register to register, or prede-

cremented memory from memory, with extend. The
extend bit enables multi-precision arithmetic to be
performed, acting as a borrow between successive
operations.

Data register subtractions

Subtract two 64 bit integers.
DO_DI and D2_D3 Lo and
Memory subtractions Hi respectively

SUBX -(Ay) ,-(Ax)' SUB.L DD,D2 Low bits

LET Ay=Ay-4 SUBX. L Dl ,D3 High bits
LET Ax=Ax-4
PDKE(Ax) ,PEEK(Ax) - PEEK(Ay) - X

Memory addition

MOVE #4,CCR
SUBX.L - (AD) , - (A 1 )
SUBX.L -(AD),-(Al) etc.

* X infers the Extend bit

Note that the z-flag is cleared if the result is non-
zero, otherwise it is unchanged. For memory ad-
ditions first clear the Extend bit and set the Zero flag.
95
The data must be stored with the most significant
digit lower in memory and the address pointers
initially set the operand size above the low order
digit. Predecrement is the only memory addressing
mode.

SWAP: Swap register halves. This exchanges the

high-order word of a data register with the low-order
word. This instruction provides access to the low-
order byte of the high word.

On 0-15<---+On 16-31

T AS: Test and set an operand compares the operand

byte with zero and sets the condition codes accord-
ingly. If the byte is zero, the Z flag is set; if the MSB
is non-zero, then the N flag is set. The MSB of the
operand is then set.

TAS ea

TR.AP: Trap. The processor commences execution

at the relevant trap exception vector address.

TRAP #n

TRAPV: Trap on Overflow. The processor com-

mences execution at the trap on overflow exception
vector address.

TRAPV

96
TST: Test an operand. The operand is compared
with zero and the condition codes set accordingly.

TST ea

Use in preference to CMPI #0. ea

UNLK: Unlink. The stack pointer is loaded from the

specified address register; the address register is then
loaded with the longword pulled from the top of the
stack and the linked space deallocated.

UNLK An

97
 Processor
Signal 1/0
The following is a very brief description of the signal
I/O of the Motorola MC68000 and MC68008 micro-
processors.

MC68000
MC68008

Vee .. Address ~ AO AO
Gnd If bus If' to to
Clk A23 AI9

DO DO
Processor FCO All Data Ii. to to
Status FCI 'If! Bus" DIS D7
FC2

.. Asynchronous
" Control
.AI Synchronous
.. Control
Bus
tArbitration

System
Control
I Berr
Reset ~
Control

Interrupt IPLO IPLO/2

Halt Control IPLI IPLI
1...-_----' IPL2

98
 Address JEhllS
Enables the processor to address 16 Megabytes
(MC68000) or 1 Megabyte (MC68008) of memory.
The address bus provides during an interrupt the
level being serviced on address lines AO to A3 while
the remaining address lines are held high.

Data BUllS
Enables the transfer of word and byte sized data on
the MC68000, but is limited to byte sized transfers
on the MC68008. During an interrupt acknowledge,
a vector number may be placed on lines DO to D7 by
a peripheral device.

Bus Arbitration Control

Allows a peripheral device to control the processor
bus (Bus Master); any external request will be
granted on a priority basis between the competing
devices.

InterrUllpt ControX
Provides a priority level from peripherals requesting
processor control, enabling selection of multiple in-
terrupts on a priority basis. Zero implies that there is
no interrupt present and 7 may be considered as a
non-maskable interrupt. The MC68000 has seven
levels of interrupt 1 to 7 whereas the MC68008 is
limited to three levels, 2, 5 and 7.
99
 System Control
Informs the processor that bus errors have occurred
and also resets or halts the processor.

Processor Status
Each time a memory or I/O call is made the processor
provides the following information on the processor
status lines to a peripheral device: whether the
processor is accessing data or program memory
space, or servicing an interrupt; and whether the
processor is in user or supervisor mode.

The processor's separate parallel address and data

buses are used to transfer data using an asynchronous
bus structure, controlled by the processor (internal
or external) which has current bus control.

Interfacing with the 8-bit M6800 and 6500 family of

synchronous peripheral devices is catered for throu-
gh the use of memory mapped I/O and a modified
bus cycle.

The reduction from a 64-pin MC68000 package to a

48-pin MC68008 not only reduces the width of the
available address and data bus, it also reduces the
number of signal I/O's.

100
Signal I/O Variations

MC68000 MC68008 MC68008

signals signals equivalelll
----
UDS,LDS AO,DS
DS

VMA
BGACK

AO-A23 AO-AI5
DO-DI5 DO-D7

IPLO,IPL2 IPLO/2

101
APPENDICES

103
 Motorola MC68000
Instruction encoding
BIT MANIPULATION, MOVE
PERIPHERAl. and KMMEDKATE
Type 0 (Bits 15-12)

Instruction Dreg Dmod Smd Sreg Address C01ldCodes

symax 11-9 8--6 5-3 2-0 Mode XNZVC

BCHG On ~i::l On 5 -ea- dataltadd - - A - -

BCHG clata, ea 4 1 -ea- dataltadd - - A - -
BeLR Dn. Co On 6 -ca- dataltadd - - A - -
BCLR clata. Ca 4 2 -ea- dataltadd - - A - -
BSET Dn,ca On -ca- dataltadd - - A - -
SSE r Odto. ca 4 -ea- dataltadd - - A - -
BTS! Dn. eil On 4 -ca- dataddmd2 - - A - -
BiS! data.cel 4 0 -ca- dataddmd2 - - A - -

~\Ovrp Dx. d(Ay 1 Ox I x Ay

i>lOV[PC1(Ay) D., OX Ox Ay

OR I clata. ea 0 os s -ca- dataltadd - A A0 0

ORldata CCR 0 0 7 4 AAAAA
OR I datB SR 0 7 4 AAAAA

ANDl (Iota oS S -ca- dataltadd - A A 0 0

AND I clata CCR 0 4 AAAAA
,~NDI clata SR 4 AAAAA

SUB! d.;:,:a 2 os s -ca- dataltadd AAAAA

ADD 1 data os s -ca- dataltadd AAAAA

EGA I ddta oS s -ca- dataltadd - AA 0 0

EGRI data CCR 0 7 4 AAAAA
EGR I data 511 5 I 7 4 AAAAA

GtPI tlata ca 6 os s -ca- dataltadd - A AA A

105
 MOVE BYTE, WORD and
LONGWORD INSTRUCTION
(Bits 15-12)

I'1strllccioll Type Dreg Dmod SlIId Sreg Address Gond Codes

symax /5-/2 1/-9 8-6 5-3 2-0 Mode XNZ VG

MOVl H ca, - A A 0 0
source - C3- ALL*
destination -C3- dataltadd

1'10\/[ L_ (~i:l . ca - A A 0 0
source -C3- ALL
destination -ca - dataltadd

~10Vt ,l,'! eel. Cd -A A 0 0

source -C3- ALL
destination -ca- ataltadd

11 Address register direct mode is not permitted

MISCELLANEOUS
INSTRUCTIONS
Type 4 (Bits 15-12)

blstrucrion Dreg Dmod Smd Sreg Address COlld Codes

sYlltax 1/-9 8-6 5-3 2-0 Mode XNZ VG

NEGX, it 0 0 s s -ea- dataltadd AA AA A

CLR "d 0 S S -ea- dataltadd - 0 I o0
r;EG I'd 0 S S -ca- dataltadd AA AA A
t\OT ,}d 0 S S -ea- dataltadd - A A 0 0

Movr Sf1 . ea 0 -ca- dataltadd

MOV[ . CCR -ea- dataddmdl AA AA A
~101Jl cd SR -ca- dataddmdl AA A A A

106
Type 4 (Bits 15-12) continued

Instruction Dreg Dmod Smd Sreg Address Cond Codes

sylllax 11-9 8--6 5-3 2-0 Mode XNZVC

SWAP On 4 0 On - A A 0 0
EXT On 4 Olx 0 On -AAOO

NBCO ea 4 0 -ea- dataltadd AuAuA

PEA ea 4 -ea- conaddmdl

fol0VEM list,ea 4 0 1 x -ea- conaltadd

MOVEMea.list 6 o1 x -ea- conaddmd2

TST ea 5 os s -ca- dataltadd - A A 0 0

TAS ea 5 3 -ea- dataltadd - A A 0 0

ILLEGAL 5 3 7 4

TRAP data 7 00 v v v v

LINKAn.data 7 2 An
UNLK An 7 3 An
MOVE An. USP 7 4 An
NOVE USP .An 7 An

RESET 7 6 0
NOP 7 6
STOP data 7 6 2 AAAAA
RTE 7 6 3 AAAAA
RTS 7 6 5
TRAPV 7 6 6
RTR 7 6 7 AAAAA

JSR ea 7 2 -ea- conaddmdl

J~IP ea 7 3 -ea- conaddmdl

CHK ea. On On 6 -ea- dataddmdl - Au u u

LEA 08 .An An 7 -ca- conaddmdl

107
 ADD AND SUBTRACT QUICK,
SET CONDITIONALLY and
DECREMENT INSTRUCTiONS
Type 5 (Bits 15-12)

Imtrucc;Oll Dreg Dmod Smd Sreg Address Cond Codes

syntax 11-9 8-{j 5-3 2-0 Mode XNZVC

ADOQ data. ea data ass -ca- altaddmod AAAAA

SUBD da ta. ea data Iss -ca- altaddmod AAAAA

Sec ea cccc I I -ca- dataltadd

DBee On. data ecce 1 1 Dn

BRANCH CONDITIONALLY
INSTRUCTION
Type 6 (Bits 15-12)

Instruction Dreg Dmod Smd Sreg Address CondCodes

symax 11-9 8-6 5-3 2-0 Mode XNZVC

Bee data ccc displacement

BSA data a displacement
BAA data a a displacement

If displacement is 0, then displacement is in the following word

MOVE QUICK INSTRUCTION

Type 7 (Bits 15-12)

Instruction Dreg Dmod Smd Sreg Address Cond Codes

symax //-9 8-{j 5-3 2-0 Mode X N Z V C

MOVED da ta, On Dn aI data - A A aa

108
 OR, DIVIDE AND SUBTRACT
DlECIMAI. INSTRUCTIONS
TypeS (Bits 15-12)

/mlTuClioli Dreg Dmod Smd Sreg Addre,.• COlldCode,

s)mtax 11-9 8-6 5-3 2-0 Mode XNZVC

ORca.Dn Dn os s -ca- dataddmd1 -AAOO

OROn.t'd Dn Iss - ca- altmcmadd - AA00

o!VU f'<'! DIl Dn 3 -ca- dataddmd1 -AAAO

DIVSe,l,Dn Dn 7 -ca- dataddmdl -AAAO

SBCDD .. ,D', Dx 4 0 Dy AuAuA

SBeD I:"','), (':'x) Ax 4 Ay AuAuA

SUBTRACT AND SUBTRACT

EXTENDED INSTRUCTIONS
Type 9 (Bits 15-12)

Illstrucrioll Dreg Dmod Smd Sreg Address COlldCodes

syntax 11-9 8-6 5-3 2-0 Mode XNZVC

SUBA ea. An An x II -ea- ALL

SUBea.Dn Dn os s -ca- ALL AAAAA

SUBDn,cu Dn I s s -ca- altmemadd AAAAA

SUBX Dy. Dx Dx 1 s s 0 Dy AAAAA

SUBX - (lIy). (A'i Ax Iss Ay AAAAA

109
 Emulation instruction
Type 10: Normally available for the implementation
of user-written routines and entered by ensuring four
MSBs of the op word are 1010 and directing trap
service to a user routine. Other bits of Op word may
be used for parameter passing.

COMPARE AND EXCLUSIVE OR

][NS1f'RUC'FlIONS
Type 11 (#$B) (Bits 15-12)

11lS1rllCcioll Dreg Dmod Smd Sreg Address COl/dCodes

s)'max 1/-9 8-6 5-3 2-0 Mode XNZVC

CMP!-\ ea, An An x 1 1 -ca- ALL -AAAA

eMP ca. On On o s s -ea- ALL -AAAA
01Pi>1 lAy) . (A,) Ax 1 s s Ay -AAAA

EOR On. ea On 1s s -ca- dataltadd - AA0 0

AND, MUllTlIlPLY, ADD DECIMAL

AND EXCHANGE lINS1f'RUC1f'JIONS
Type 12 (#$C) (Bits 15-12)

Imtruct;ou Dreg Dmod Smd Sreg Address Cmld Codes

s)'lItax 11-9 8-6 5-3 2-0 Mode X N Z V C

AND ea. On On 0 s s -ea- dataddmdl - A A 0 0

AND On. ea On 1 s s -ea- altmemadd - A A 0 0

110
Type 12 (#$C) (Bits 15-12) cotztitzued

b,structio1/ Dreg Dmod Smd Sreg Address Com/ Codes

symax 11-9 8-6 5-3 2-0 Alode X J.V Z V C

~IULU .Un Dn - ca- dataddmdl - A A 0 0

~!U LS Un Dn - ca- dataddmdl - A A 0 0

'~BCD D\' . Dx Dx 4 0 Dy A u A u A
i.BCD \:,",1 - : ;~ ~ ) Ax I Ay A u A u A

FXGD Ox . [Jy Dx 0 Dy
lXGA .1\,/ Ax Ay
f:::XG~l 0 ... :. Dx 6 Ay

ADD AND ADD EXTENDED

INSTR.UCTIONS
Type 13 (#SO) (Bits 15-12)

ins(rllCrioll Dreg Dmod Smd Sreg Address Cond Codes

symax 11-9 8-6 5-3 2-0 1\[0£11.' X iY V C

AOD,\ Cd ,\11 An x I I -ca - ALl.

- - --------~
------------
On 0 S s -ca- ALL A A A A A
i\OO On Dn s s - ca- altmcmadd A A A A A

:·ODX D. [1. Dx s s 0 Dy A A A A A
,\ODX (1\;;). (Ax) Ax s s Ay AAAAA

111
 SHIFf AND ROTATE
INSTRUCT][ONS
Type 14 (#SE) (Bits 15-12)

Instruction Dreg Dmod Smd Sreg Address COlld Codes

syntax 11-9 8-6 5-3 2-0 A10de XNZVC

ASL Ox · Dy Ox s s 4 Oy AAAAA
ASL datil .Oy ent s S 0 Oy A A A A A
A,$L ea 0 -ca- altmcmadd A A A A A

ASR 0 x. Dy Ox os s Oy AAAAA
ASR delti.l. Dy ent oS S 0 Oy AAAAA
ASR ea 0 3 - ca- altmcmadd A A A A A

LSL Ox · Dy Ox s s Oy A A A 0 A
LSL dat.:. .Dy ent S S Oy AAA o A
LSL ca -ca- alrmcmadd AAAOA

LSR Ox · Dy Ox os s Oy AAAOA
lSRdat21. Dy em os s Oy AAAOA
LSR ea -ca- altmcmadd AAAOA

ROL Ox · Dy Ox s s Oy - A A 0 A
ROL data . Dy ent s s OJ' -AAOA
ROL ca -ca- altmcmadd -AAOA

ROR Ox · Dy Ox os s Oy -AAOA
RDR data. Dy ent os s Oy -AAOA
RDR ca - ca- altmcmadd -AAOA

ROXlOx . Dy Dx s s 6 Oy AAAOA
ROXL data . Dy ent s s 2 OJ' AAAOA
ROXl COl 2 - ca- altmcmadd AAAOA

ROXR Dx . Dy Ox s s 6 Oy AAAOA
ROXR data . Dy em s s Oy AAAOA
ROXR ea 2 - ca- altmcmadd AAAOA

112
 Emulation. Instruction
Type i5: Available for the implementation of user
written routines and entered by ensuring 4 MSBs of
the Op Word are illi (15), directing the trap service
to the user routine. Other bits of Op Word may be
used for parameter passing.

CONDITIONAL TESTS
CC i.Hllemouic Condition

o T TRUE
F FALSE
HI HIGH
LS LOW or SAME

4 CC CARRY CLEAR
CS CARRY SET
6 I'\E NOT EQUAL
7 EQ EQUAL

8 VC OVERFLOW CLEAR
9 VS OVERFLOW' SET
IO PL PLUS
II MI ,"lINUS

12 GE GREATER or EQUAL
13 LT LESS THAN
14 GT GREATER THAN
15 LE LESS or EQUAL

There is no Branch TRUE BT or Branch FALSE BF

x Size ConditioN codes
o = Word 0 0 = Byte u = Undefined 0 = Cleared
I = Longword 0 1 = Word A = Affected 1 = Set
1 0 = Longword - = Unaffected
ca = Effccth'c address
CCR = Condition code register c c c c = 4-bit Condition code
SR = Status register v \' \' V = 4-bjr Vcc(Or code
113
 Extension Word Coding

Address Mode Index instructions

Operation Word

I reg I I I
y 0 displacement

15 14 12 11 10 8 o
Bit
15 0 = Data register
1 = Address register
14-12 Register number
11 0 = .W Index
1 = .L Index
7-{) Displacement Low Memory

Operation Word Instruction word

Source Operand in memory
Destination Operand

MOVEM: The Register List always follows the Op

Word, transfer in sequence of set bits from 0 (first) to
15 (last).

Genera/list

I A7 A6 A5 A4 A3 A2 A1 AO D7 D6 D5 D4 D3 D2 D1 DO

15 o
DO D1 D2 D3 D4 D5 D6 D7 AO A1 A2 A3 A4 A5 A6 A7
Predccremcnt list ollly
114
 Address modes

ENCODING
The range of addressing modes are coded consistent-
ly throughout the MC68000 instruction set and may
be summarized as follows:

Addressing Syntax Mode Reg Ext.

mode No. No. words

Data register direct On 0 n 0

Address register direct An n 0

Address register indin::ct (An) n 0

Address n:gistl'r indirect (An)+ n 0

with postincrcmcnt
Address register indirect -(An) 4 n 0
with prcdccrcmcnr

Address register indirect deAn) n

with displacement
Address register indirect d(An.Ri) 6 n
with index

Absolute short ABS.S $xxxx 0

Absolute long ABS.L $xxxxxx I

Program counter with d(PC)

displacement
Program counter with d(i'C.Ri)
index

Immediate Imm #Sxxx 7 4 lor 2

115
n = Register number 0 to 7
Ext. Word =Number of extension words following the op word due to this
address mode (source and destination ext. words are
cumulative)
Mode No. = Dmod and Smod in instruction code tables
Reg No. = Dreg and Sreg in instruction code tables

116
 AlLlLOWABLE ADDRESS
MODE TYPES
All Data All Dat Dal COil Con Con
AI! Jv!em All Add Add Add Add All Add
Add Add Mod Mdl Md2 Mdl Add Md2

Source
DI!SI Dest'n Des! Srce Desl Dest Src

On x x x x
An x
(An) x x x x x x
(An)+ x x x
-(An) x x x x x
deAn) x x x x x x
d(An.Ri) x x x x x x
ABS sh x x x x x
ABSlg x x x x x x
d(PC) x x x
d(PC.Ri) x x x x
Imm x

ADn ADD ADDT SHeD ADDQ .-\;..;0 BTST 1MI' .\lOVE.\t .\\O\'E.\1

.\nn:\ A~D ASDI NEG SU1Q CHK JSR <eg

eM!' OR BCHG NECiX DlVS LEA

C,\\PA seB BCLR NOT DIVU PEA reg
.\\lWE BSE'[ URI
.\\oVEA
ASL elR .\IOVE

Sl:n :\SR C.\iPI Sec: weeR

sellA ROXL EOR .\\O'·E
IWXR EORI SUB! wSR
ROL MO'"E TAS
ROR TST MULS
LSL ,\tOVE .\lULU
LSR fr5R OR

All = Altcfahk .\tod '" ,\Iode .\1..11 ~~ "todd addrcs~inp: mude type'
.\h:m '" ,\kmllr~ Oat = Data Md2 '" .\10de2 dcfinillom used by
Add" Addro.:\, Con = Control .\tolOf(llu (0 describe
:lllowabk modes

117
 ADDRESS MODE
Assembly language and BASIC equivalents

Address mode Source Destinatioll

Data register Dn MOVE. L 02 .00 MOVE. L #999 ,DO

direct LET 00-02 LET 00-999

Address
register An ,lOVE LAO, DO fIOVEA. L #999 .AO
direct LET DO-AD LET AO·999

Address
register (An) MOVE L (AD) , DO MOVE L#999, (AD)
indirect LET OO'PEEK L(AO) POKEJ (AD) ,999

Address
register (An) + MOVE L I AD)' ,DO MOVE,L#999, lAO)'
indirect with LET OO-PEEKLIAO) POKE"L I AD) ,999
posrincrcmenr LET AD-AD' 4 LET AD-AD' 4

Address
register -(An) MOVE. L lAD) ,DO MOVE,L#999,-IAO)
indirect with LET AO-AO - 4 LET AD-AD - 4
prcdecrcmcnt LET OO-PEEK .. L lAO) POKE"L lAO) ,999

Address
register d(An) MOVE L9IAO),00 MOVE, L#999, 9IAO)
indirect with LET 00-PEEK_LI9' AD) POKE"LIAO'9) ,999
displacement

Address
register d(An,Ri)
MOVE L 91AO 02) ,DO MOVE. L #999,9 I AD, DO)
indirect with LET DO-PEEK..\. I 9 ·AO· 02) POKE"L lAO' 9· DO) • 999
index

Absolute short Sxxxx MOVE L 1024,00 fIOVE, L #999,1024

ABS.S LET 00'PEEK"Lll024) POKE"L I 1 024) ,999

118
Address lIIode Source Destillation

Absolute long $xxxxxx

MOVE. L 163840.00 MOVE. L #999.163840
ABS.L LET OO-PEEK_L( 163840) POKE_L(163840) .999

Prog counter d(PC) MOVE. L 9 (PC) . DO

with LET 00-9 + conts of Not legal
displacement Program Counter

Prog counter d(PC.Ri )

with MOVE.L9(PC.02) .00
index LET 00-9.02 + contof Not legal
Program Counter

Immediate #$xxx MOVE. L #65536.00 Not legal

Imm LET 00-65536

Register DO is used The source is defined

for the destination as immediate data
Notes as an example; any value 999; any other
other valid effective valid effective
address may be used. address may be used.

All equivalents have been defined as having longword operands, byte and
word-sized operands may also be used.

119
 MC68000 Instruction
Execution Times
The timings given are the execution times of each
instruction in terms of external clock periods, all
instructions other than MOVE must include any
additional time required in calculating the effective
address for both source and destination operands as
applicable. Note that the MC68008 processor times
are somewhat longer when dealing with words and
longwords, absolute addresses or 16-bit displace-
ments.
MOVE Instructions

d(An
.B.W.L On An (An) (An) + -(An) deAn) .Ri) Abs.S Abs.L

Dn 4/4 4/4 8/12 8/12 8/14 12/1614/1812/1616/20

An 4;4 4/4 8/12 8/12 8/14 12/1614/1812;1616/20
(An) 8/12 8/12 12/2012/20 12/20 16/24 18/26 16/2420/28
(An)+ 8/12 8/12 12/2012/20 12/20 16/24 18/26 16/2420/28
-(An) 10/1410/1414/2214/2214/2218/2620/2818/2622/30
deAn) 12(16 12/16 16/24 16/24 16/2420/2822/3020/2824/32
d(An.Ri) 14/18 14/18 18/26 18/26 18/2622/3024/3222/3026/34
Abs.S 12/16 12/16 16/24 16/24 16/2420/2822/3020/2824/32
Abs.L 16/2016/2020/2820/2820/2824/3226/3424/3228/36
d(PC) 12/1612/16 16/24 16/24 16/2420/2822/3020/2824/32
d(PC.Ri) 14/18 14/18 18/26 18/26 18/2622/3024/3222/3026/34
Imm 8/12 8/12 12/20 12/20 12/20 16/24 18/26 16/2420/28
Time to Calculate Effective Address

d(An d(PC
(An) (An) + -(An) deAn) .Ri) Abs.S Abs.L d(PC) .RO Imm

.B.W;.L 4/8 4,8 6/10 8,12 10/14 8:12 12,.16 8,'12 10'14 4,8

The time taken to calculate the effective address must be added to

instructions that affect a memory address.

120
Standard instructions

.B.W/.L ea,An ea,Dn Dn,menz

ADD 8/6(8) 4/6(8) 8/12

AND 4/6(8) 8/12
CMP 6/6 4/6 (8) time if effective
address is direct
DIVS 158 max
DIVU 140 max
EOR 4/8 8/12 Add effective
MULS 70 max address times from
MULU 70 max above for
OR 4/6(8) 8/12 memory addresses.
SUB 8/6(8) 4/6(8) 8/12

Immediate instructions

.B.W/.L #,DII #,An #,mem

ADDI 8/16 12/20

ADDQ 4/8 8/8 8/12 MOVEQ longword only
ANDI 8/16 12/20 NBCD and T AS Byte only
CMPI 8/14 8/14 8/12
EORI 8/16 12/20 Sec False/ True
MOVEQ 4
ORI 8/16 12/20 Add effective address
SUBI 8/16 12/20 times from above for
SUBQ 4/8 8/8 8/12 memory addresses.

CLR
NBCD
NEG
NEGX
NOT
Sec
TAS
4/6
6
4/6
416
4/6
4/6
4
4/6
6
4/6
4.'6
4/6
4/6
4
8/12
8
8/12
8/12
8/12
8/8
10
},;~" operand
instruction

TST 4/4 4/4 4/4

121
Shift/Rotate instructions

.B.W/.L Dn An mem

ASR,ASL 6/8 6/8 8 Memory is Byte only

LSR,LSL 6/8 6/8 8 Register add 2
ROR,ROL 6/8 6/8 8 x shift count
ROXR,ROXL 6/8 6/8

lmt'n (An) (An)+ -(An) d(An) d(An.Ri) Abs.S Abs.L d(PC) d(PC.Ri)

JMP 10 14 10 12 10 14
jSR 16 18 22 18 20 18 22
LEA 8 12 8 12 8 12
PEA 12 16 20 16 20 16 20

MOVEM
12 12 16 18 16 20 16 18
M>R T ~ 4

MOVEM
12 14 12 16
R>M T ~ 5

MOVEM add T x number of registers for wurd:;,

MOVEM add 2 x T x number of registers for longwords.

Register Memory
Bit imtrucrions LOllgword Byte
.E/.L only Dilly

BCHG 8/12 8/12

BCLR 10/14 8/12
BSET 8/12 8/12
BTST 6/10 4/8

122
Exception periods

Address Error 50
Bus Error 50
Interrupt 44
Illegal Instruction 34
Privilege Violation 34
Trace 34

Instruction .B. W/.L OpDn,Dn OpM,M

ADDX 4/8 18/30

CMPM 12/20
SUBX 4/8 18/30
ABCD 6 18
SBCD 6 18

• ABCD and SBCDByte only

Instruction Disp Taken Not Taken

Bcc .B/.W 10/10 8/12

BRA .B/.W 10/10
BSR .B/.W 18/18
DBcc T/F 10 12/14
CHK 40 max 8
TRAP 34
TRAPV 34 4

Instruction Size Reg--Mem

MOVEP .W/.L 16!24

Add effective address times from above for memory addresses.

123
Instruction Reg Mem Instruction Reg

ANDltoCCR 20 MOVE from USP 4

ANDltoSR 20 NOP 4
EORltoCCR 20 ORltoCCR 20
EORltoSR 20 ORIto SR 20
EXG 6 RESET 132
EXT 4 RTE 20
LINK 18 RTR 20
MOVEtoCCR 12 12 RTS 16
MOVE to SR 12 12 STOP 4
MOVE fr SR 6 8 SWAP 4
MOVEtoUSP 4 UNLK 12

Add effective address times from above for memory addresses.

124
 M C68000 Series
Differences Summary

Parameter 68008 68000 68010 68020

Data Bus bits 8 16 16 32

Address Bus bits 20 24 24 32

Address Range Mbytes 1 16 16 4294

Address Modes 14 14 14 62

Data Types 5 7
Instruction Set 56 56 58 76

Control Registers 3

System Stacks 2 2 2 3

Status Reg (active bits) 10 10 10 12

Cache Memory Bytes 6 256

Interrupt Levels 7 7 7

Pins per package 48 64 64 114

125
 Hex to Decimal Table
Hex Dec Hex Dec Hex Dec

100000 1048576 10000 65536 1000 4096

200000 2097152 20000 131072 2000 8192
300000 3145728 30000 196608 3000 12288
400000 4194304 40000 262144 4000 16384
500000 5242880 50000 327680 5000 20480
600000 6291456 60000 393216 6000 24576
700000 7340032 70000 458752 7000 28672
800000 8388608 80000 524288 8000 32768
900000 9437184 90000 589824 9000 36864
AOOOOO 10485760 AOOOO 655360 AOOO 40960
BOOOOO 11534336 BOOOO 720896 BOOO 45056
COOOOO 12582912 COOOO 786432 COOO 49152
DOOOOO 13631488 DOOOO 851968 DOOO 53248
EOOOOO 14680064 EOOOO 917504 EOOO 57334
FOOOOO 15728640 FOOOO 983040 FOOO 61440

FFFFFF 16777215 FFFFF 1048575 FFFF 65535

100 256 10 16 1
200 512 20 32 2 2
300 768 30 48 3
400 1024 40 64 4 4
500 1280 50 80 5
600 1536 60 96 6 6
700 1792 70 112 7 7
800 2048 80 128 8 8
900 2304 90 144 9 9
AOO 2560 AO 160 A 10
BOO 2816 BO 176 B 11
COO 3072 CO 192 C 12
DOO 3328 DO 208 D 13
EOO 3584 EO 224 E 14
FOO 3840 FO 240 F 15

FFF 4095 FF 255 F 15

126
 Instruction Extensions,
MC68010 Processor
Additional Registers
Vector Base Register

31 o
VBR IL...-_______~
The Vector Base Register is used with an offset to
provide the exception vector address. Initially the
VBR is set to zero, but may be loaded or read with
the MOVEC instruction. The vector offset times 4 is
added to the VBR for the required vector address,
the VBR pointing to the base of the table.

MOVE.L #$8000,DO
MOVEC DO,VBR

Alternate Function Code Register

2 0
SFC Source Function Code Register
DFC Destination Function Code Register fIE
The Alternate Function Code Registers are 3-bit
registers used with the MC68010 instructions
MOVEC and MOVES. MOVEC sets the function

127
code registers enabling the MOVES instruction to
read or write to locations in the supervisor program,
user program or user data areas.
Additional MC68010 Instructions Encoding

Instructiori Type Dreg Dmod Smod Sreg Add,.ess

Syntax 15-12 Jl-9 8-6 5-3 2-0 mode

'MOVES Rx-ea 0 7 Oss -ca- altmemadd

ext word XRx Y +- 0 -+
MOVECCR,ea 4 I -ca- dataltadd
'MOVESR,ea 4 0 3 -ca- dataltadd
RTD 4 6 4
'MOVEC CR,Rx 4 7 2 Dn,An
'MOVECRx,CR
ext word
4
XRx ....
7 7
CR .....
3 only

x = 0 data register CR = OOOH SFC CR =80IHVBR

X = I ,.ddress register = OOIHDFC =802HCAAR#
Y = 1 ca to register = 002HCACR# =803HMSP#
Y = 0 register to ca = 800HUSP =804H ISP#

* Privileged # MC68020

The above instructions do nor affect Condition Codes.

RTl!): Return and deallocate is a two word instruc-

tion that replaces the following code with RTD #12

MOVE.L (A7)+.An
LEA 12(A7).A7
JMP (An)

Changes to Code:

MOVE SR,ea: This is privileged in both MC68010

and MC68020 code.
128
RTE: return from exception. There are now two
versions of this instruction:

Short, as MC68000 code but additionally with

the vector offset.
Long, 29 words of information on the processor
status prior to the interrupt.

CLRj Scc; MOVE SR,ea; MOVE CCR,ea 32-bit

arithmetic and Logic data operations are performed
faster in MC68010 code.

129
 Instruction Extensions
MC68020 Processor
Additional Registers

31 210

Master Stack Pointer MSP

Variable Base Register VBR
Source Function Register SFC I
Destination Function Reg DFC I
Cache Control Register CACR IqCE FE
Cache Address Register CAAR Cache Function addrJ Index -

S M Status register
0 0
0
User Stack Pointer
User Stack Pointer
15 o
I 0 Interrupt (System) SP .xNzvcl
Master Stack Pointer T T active bies.
o 0 Trace off:
C ~ Clear Cache o Trace on: Branch, jump
CE ~ Clear Entry and return only
F = Freeze Code o Trace on: Same as MC68000
E ~ Enable Cache Reserved:

130
Effective Address Calculations for the indirect modes

An/PC + bd + Rx .2 x sk + od

Bast' Bast' Illdc:x Index Scale Index

Register displ. Register Size: Factor offsel

AO-A7 0 00-07 .W 1 0
or or 16 or or or 2 or 16
PC or 32 AO-A7 .L or4 or 32
or bits or or 8 bits
nothing nothing

Indirect Reg. Index Register

An Address Register data size

PC Program Counter sk scaling factor
Rx Address or Data Index Registcr
od Indcx offsct
bd Base Address displacement ± 2 Gigabytes,
o to 2 Gigabytes (-+- vc only)
New Instructions:

Bitfield*: extract BFEXT

insert BFINS
Find First One BFFFO
test BFTST
clear BFCLR
change BFCHG
Breakpoint BKPT #n
Compare and Swap CAS
Check Reg against Bounds CHK2
Compare Reg with Bounds CMP2
Trap on Condition Trap cc
Pack BCD PACK
Unpack BCD UNPK
Call Module CALLM
Return from Module RTM
* up to 32 bits

131
 'User' Programming Model
31 16 15 8 7 0
00
01
02
03 Data
04 Regs
05
06
07

AO
A1
A2
A3 Addr
A4 Regs
A5
A6
A7 User
Stack Pointer
PC

CCR Status
User byte Reg

If user applications cnd-programs are restricted to the above model, then

the programs will work on any of the MC68000 series devices.

The only variation between the devices in user state is that the MC68000
and MC68008 can read [he Status Register system byte, whereas the
MC68010 and the MC68020 can not.

132
 'Supervisor' Programming Model
MC68008
31 16 15 8 7 0
1
. . . . ._----'I____~I A7
Not strictly true but this
way it gives a consistent I - - - --
-I
approach to programm- _ T -S- - I I I _ _ _ _ _ _ SR
illg the series oj Status register
MC68000 devices_
MC68000

A7
SSP

System byte IT-S--III -------J SR

------
Status register

Supervisor Stack Pointer MC68010

A7

System byte [T-S--III ~~-_~-_-_-_-J SR

Vector Base Status register
Register '--_ _ _ _ _ _ _ _ _ _ _ _1 VBR

Source Junction code

DestinationJunction code IIII SFC
_DFC
133
 MC68020
31 16 15 8 7 o
Interrupt Stack I A7
Master Stack I A7
Status Register ITTSM- I I 1_-:: ~ ~: ] SR
System byte
Vector Base Register

~____________~IVBR

Source Junction code

DestinationJunction code EEE SFC
DFC

Cache Control
Register
~____________~ICACR
Cache Address
Register ~______________~ICAAR

The supervisor state is usually used for Operating

Systems, Interrupt handling, Resource Management
and System Control.

134
 Virtual Facilities

Virtual Machine
The MC68010 completely secures the supervisor
resources from the user, permitting an operating
system to be run at user level, and due to the
privilege violation traps, think it is running at super-
visory level. Thus one governing operating system
can execute at supervisor level and control the man-
agement of many other operating systems executing
at user level, each operating as though in supervisor
state. Privilege traps go automatically to the govern-
ing operating system where the exceptions are
checked and conditionally executed before control is
returned to the originating system, thus providing a
virtual machine.

SUPERVISOR Governing Operating System

User Programs Applications Languages

135
 Virtual Memory
Much of the address space of the MC68010 and
MC68020 processors will not be occupied by physic-
al memory and any call to this non-existant memory
will result in a bus error. The bus error exception
routine is able to hold the memory access until the
relevant data is fetched from an alternative memory
source, usually a disk, and placed in physical memory
whereupon the memory address is adjusted and the
access continued.

Address Space
The MC68010 address bus is 32-bits wide internally
with 24 of the address lines being brought off-chip in
4 different address spaces, each having a 16Mbyte
address range designated User/Supervisor and Prog-
ram/Data. The MOVES instruction (Move alternate
space) allows the executing operating system to move
data to or from an address space other than the
supervisor data space, controlled by the Alternate
Function Code registers.

FC2 FC! FCO ASSIGNMENT

0 0 0 reserved
0 0 User data space
0 0 User program space
0 ! User definition
0 0 reserved
0 Supervisor data space
0 Supervisor program space
CPU space

136
 Cache Memory (MC68010)
The MC68010 has the ability to execute a short piece
of code rapidly, (one instruction word and a DBcc
instruction) by retaining the code internally, not
requiring to go off-chip to fetch each instruction
word from memory in sequence. The facility provid-
es very fast block moves and string comparisons.

LEA data,AO
LEA space,A1
MOVE.W length,DO
loop MOVE .W (AO) + , (A 1 ) +
DBRA DO.loop } 6 byte
cache

Allowable Instructions

Imtr Src D':Sl. lustr Src Dest. Il1st,. Src Dest.

MOVE (Ay) (Ax) ADD (Ay) Dx ADDA (Ay) Ax

(Ay)+ (Ax)+ AND (Ay)+ Dx CMPA -(Ay) Ax
-(Ay) -(Ax) CMP -(Ay) Dx SUBA (Ay) + Ax
Ry OR ASL (Ay) #1
CLR (Ay) SUB ASR (Ay) + #1
NEG (Ay)+ ADD Dy (Ax) LSL -(Ay) #1
NEGX -(Ay) ! AND Dy (Ax) LSR
NOT I EOR Dy -(Ax) ROL
TST
NBCD
IOR
SUB
ROR
ROXL
ABCD -{Ay) -(Ax) CMP (Ay)+ (Ax) ROXR
ADDX
SBCD
SUBX

Although pin compatible, it is possible that replacing

an MC68000 with an MC68010 will not provide

137
increased performance as operating system timing
loops may be constructed using the DBRA instruct-
ion.

Cache Memory (MC68020)

As Code is fetched from memory it is put into the
256-byte cache memory, if a program re-executes a
recently called piece of code, it is not fetched from
memory but recalled from cache, so saving the off-
chip access time. Data accesses are not cached ensur-
ing that the latest data is always used.

138
Absolute Bcc (Branch on
addressing 24 condition) 74
ABCD 68 BCHG 74
Access to system BCLR 74
stacks 46 BRA (Branch
Add Binary Coded always) 75
Decimal 68 BSET 75
Add item to linked BSR (Branch to
list 52 subroutine) 75
ADD A 70 BTST 75
ADDI 70 Bus - arbitration
ADDQ 70 control 99
Address - bus 99 - error 62
- error 64
Address mode - Carry 20
assembler & BASIC Changes of operating
equivalents 118 state 57
- allowable 117 CHK 76
- encoding 115 Circular buffer 49
Address spaces 136 CLR 76
Addressing modes 24, CMP 76
26 CMPA 77
ADDX 70 CMPI 77
ANDI 72 CMPM 77
AND I to CCR 72 Condition codes 19, 20
ANDI to SR 72 - exceptions 21
ASL (Arithmetic shift
left) 73 Data bus 99
ASR (Arithmetic shift Data registers 16
right) 73 Data register direct
Assembler and BASIC addressing 26
equivalents 118 DBF 79

141
DBRA 79 JMP 82
Delete from linked JSR 82
list 53 Jump to subroutine 82
DIVS 79
DIVU 80 LEA 83
LINK 83
Encoding address Linked list - add
modes 115 item 52
EOR 80 - delete item 53
EORI 81 Logically -
EORI to CCR 81 complement 89
EORI to SR 81 - shift left 83
Exception state 55 - shift right 84
Execution times 120 LSL 83
EXG 81 LSR 84
EXT 82
Extend 21 MOVE 84
External exceptions 61 MOVE USP 87
MOVE from SR 85
ILLEGAL 82 MOVE to CCR 85
Immediate- MOVE to SR 85
addressing 24 MOVEA 87
- data 40 MOVEM 87
Immediate quick 40 MOVEP 86
Implied addressing 25 MOVEQ 86
Instruction - execution MULS 88
times 120 MULU 88
-summary 68
Internal exceptions 64 NBCD 88
Interrupts 61 NEG 88
- control 99 Negate 88
-level mask 21 - decimal 88

142
Negative 21 Register direct
NEGX 88 addressing 24, 26
NOP 89 Register set 16
Normal- RESET 91
processing 56 Reset 61
- state 55 Return-and
NOT 89 restore 92
- from exception 92
Open ended queues 48 - from subroutine 93
OR 89 Reverse stacks 46
ORI 89 ROL 91
ORI to CCR 90 ROR 91
ORI to SR 90 Rotate - with extend
Overflow 20 left 92
- with extend right 92
PEA 90 - without extend
Privileged left 91
instructions 66 - without extend
Processing states 55 right 91
Processor 98 ROXL 92
- status 100 ROXR 92
Program code in RTE 92
memory 25 RTR 92
Program counter 18 RTS 93
Program counter
relative addressing 25 SBCD 93
Push effective Scc 93
address 90 Sign-extend 82
Signal I/O 98
Queues - circular Spurious interrupts 62
buffer 49 Stack pointer 18
- open ended 48

143
Stacks - access to TAS 96
system 46 Test an operand 97
-reverse 46 Trace 22,64
- user defined 45 TRAP 96
Status r:egister 19 Traps 66
- system byte 19 - on overflow 96
- user byte 19 TRAPV 96
STOP 94 TST 97
SUB 94
SUBA 94 Unimplemented
SUBI 94 instructions 66
SUBQ 95 U nini tialized
Subtract decimal with interrupts 62
extend 93 UNLK 97
SUBX 95 User defined stacks 45
Supervisor 22 User state 56
Supervisor state 57
SWAP 96
System control 100

144