2020 5th International Conference on Devices, Circuits and Systems (ICDCS)

Low Power Design of 4-bit Simultaneous Counter

using Digital Switching Circuits for Low Range
Counting Applications
K.Gavaskar D.Malathi R.Dhivya
Electronics and Communication Electronics and Communication Electronics and Communication
Engineering Engineering Engineering
Kongu Engineering College Kongu Engineering College Kongu Engineering College
Erode, India Erode, India Erode, India
2020 5th International Conference on Devices, Circuits and Systems (ICDCS) 978-1-7281-6368-0/20/$31.00 ©2020 IEEE 10.1109/ICDCS48716.2020.243607

gavas.20@gmail.com malathid2001@gmail.com dhivyaraju25@gmail.com

R.Dimple Dayana I.Dharun

Electronics and Communication Electronics and Communication
Engineering Engineering
Kongu Engineering College Kongu Engineering College
Erode, India Erode, India
dyanaponmozhi@gmail.com dharunilango427@gmail.com

Abstract— To minimize the consumption of power, chip area consecutive Flip-Flop. Power efficient with high speed
and to enhance the battery life and performance of the system, asynchronous ripple scaling circuit uses innovative single
the low power VLSI circuit is designed. Scaling design or edge triggered D Flip-Flop that reduces propagation delay,
counter is used as a key element for increasing or decreasing
but it is not suitable for higher operating frequency. Low
the values of an operator depending on its previous state.
power scaling circuit based on priority encoding [21] it
During the counting process frequency and time can be
measured. The major problem in scaling circuit is the power compresses multiple binary inputs and produces the output
consumption due to the power dissipation in the clock during from the compressed input. Quasi-synchronous based design
standby mode. One-third of the total power is consumed by [22] optimizes the power dissipation. Toggle scaling circuit
the clock signal in a counter. In this paper, power [8] based on lesser transition quasi clock. Although these
consumption is reduced by minimizing the number of methods which gives the designs in an efficient way but
switching activities. The power consumption in counter they are restricted by large layout. Bi-stable storage
further reduced by reducing the power consumption in flip- elements are used in low power scaling design [11]. This
flops. This can be achieved by combining True Single Phase
method has a problem of occupying large space. 1D cellular
Clock Logic (TSPCL) with Self-controllable Voltage Level
(SVL) technique. TSPCL performs the Flip-Flop operation at
automation is used in high speed binary scaling circuit [1]
high speed with low power. SVL technique suppresses the whose operation is producing a number sequence that
power due to leakage current and also uses less number of matches the binary number system. It is not suitable for
transistors thus the system complexity also gets reduced. The wide range counters. A scaling circuit depends on adiabatic
proposed design consumes 27% less power than the existing based logic [4] and complementary pass transistor logic is
design. The proposed methodology reveals promising avenues designed. But the adiabatic logic is so complex to design.
for low power modern electronics items. True Single Phase Clock based counter [6], new OR logic is
used to implement the counting logic. By reducing the
complex and confusing path between the Flip-Flops, the
Keywords: Flip-flop, Low power, Scaling circuit, SVL, TSPCL.
counters operating frequency can be increased. This
I. INTRODUCTION phenomenon is followed in the TSPC based counter design.
Section II deals with the existing system of the Flip-Flop
A Flip-Flop itself a circuit that gives either zero or one as a
and counter. Section III claims the proposed method of T
stable state of the Flip-Flop. It is widely used for storing the
Flip-Flop using TSPCL with combined SVL technique and
information. In sequential logic, Flip-Flop is used as a basic
the scaling circuit using the proposed T Flip-Flop. The
storage element. Scaling circuit is an electronic device that
results and analysis of the proposed work are given in the
stores the number of times that the process or event has
section IV. Section V gives the conclusion.
occurred in relation with the clock signal. It is used for
counting the number of pulses coming at the input line in a II. EXISTING SYSTEM OF FLIP-FLOP AND
specific time period. The design which consumes lesser COUNTER
power with maximum reliability is almost important
A. Flip-Flop
especially when it uses clock [15]. Thus, the power of the
circuit is minimized by decreasing the dissipation of power
The Flip-Flop is designed using the method of True
in the clock. In Complementary Metal-Oxide
Single Phase Clock. The main objective of using TSPCL
Semiconductor VLSI design, [19] the basic classification of
is to perform the operation of the required Flip-Flop that
counters is synchronous and asynchronous counter and this
consumes minimum power and also operates with
classification depends on clock triggering. In simultaneous
maximum speed
counter common clock is used for all the blocks of Flip-
Flop, but in asynchronous counters the output of the
previous Flip-Flop can be given as a clock input to the

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 2020 5th International Conference on Devices, Circuits and Systems (ICDCS)

systems. In CMOS technology leakage power is primary

significance. To reduce power dissipation and to increase
the battery lifetime, the supply voltage should be reduced
when the circuit is in off state. Modified SVL technique is
applied to CMOS D Flip-Flop circuit, which suppresses
the signals and reduces power dissipation because of
leakage currents. The consumption of dynamic power is
also reduced as minimum number of transistors is used in
the modified design.
Fig. 1.D Flip-Flop Design using TSPCL.

Fig. 1 gives the design of D Flip-Flop with TSPCL.

Consider when D is 0 and CLK is low, the transistor P1 and
P2 is active which in turn activates the transistor N2 of the
next stage. Here P3 of this stage is active and gives 1 which
is inverted and gives 0. Similarly the given input of D gets
inverted in every stage and it produces the output same as the
input.

Fig. 2. Upper SVL Design. Fig. 4.Design of D Flip-Flop with Modified SVL.

P1 is ON, N2 is ON, P2, P3 are OFF, N1 and N2 are

The upper SVL consists of two NMOS connected in series
inactive. In order to perform the normal D Flip-Flop
with a parallel PMOS. The gate of the two NMOS
operation, it is connected to supply and GND. When a is
connected to the supply and the input clock bar is given to
PMOS. When the clk is 1, clkb becomes 0 and PMOS gets inactive, P1, N1, N3 are active and P2, N2 are inactive so
ON. Thus the PMOS starts conducting and the supply that out becomes inactive. When a is 1, which makes P1,
voltage 1 can pass through it. When the clk is 0, clkb N3to inactive state while makes N1, N2 and P2 active
becomes 1 then the two NMOS starts conducting and are state, that is out becomes one. P1, N3 are in OFF state i.e.
connected to the ground. By connecting the NMOS in series open circuits. N1, N2 are active but as the supply voltage
the leakage power can be reduced while the circuit is in off it gives Vdd-Vth because they acts as a pull-up network.
condition. Fig. 2 gives the design of Upper SVL. When the NMOS transistors re connected in series it
reduces the static power. P2, P3 are active but they gives
finite positive voltage as a replacement of GND because
they acts as a pull down network. As the NMOS
transistors are used in series it reduces supply voltage and
also reduces leakage current during standby mode. The
reduction of leakage power is very much concerned as it is
proportional to the current and supply voltage. This design
also has an advantage of increasing the operational speed
of the circuit and also reduces the consumption of
Fig. 3.Lower SVL Design. dynamic power in a smaller rate. Fig. 4 gives the design of
D Flip-Flop with modified SVL.
The lower SVL consists of two PMOS connected in series
B. Counter Design
with a parallel NMOS. The gate of the two PMOS
connected to the ground and the gate of the NMOS is
A simultaneous counter is designed which is power
connected to the input clock. When the clk becomes 1 and
NMOS gets OFF. Thus the PMOS starts conducting and efficient due to clock gating [16]. This logic allows the
they are connected to the ground. When the clk becomes 0 clock switching only when the Flip-Flops are in active
the two NMOS starts conducting and the supply voltage 1 state. This technique overcomes the problem of
can pass through it. When PMOS are connected in series it complexity in the circuit.
makes the circuit to reverse bias that causes the standby
mode leakage current to be reduced. Fig. 3 gives the
design of Lower SVL. A recital CMOS D Flip-Flop circuit
[10] which is comprehensively used in analog and digital

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 2020 5th International Conference on Devices, Circuits and Systems (ICDCS)

leakage current during standby mode. TSPCL consists of

four stages of inverter. The input gets inverted in each stage
and the final output of the TSPCL is same as that of the
input. The operation of the TSPCL functions according to
the clock signal.

Fig. 5.Block Diagram of 4-Bit Existing Binary Up Counter.

This design is applicable for wide range of bits. The Flip-

Flop receives the clock signal from the clock network.
This network consists of repeaters in series and eliminates Fig. 7.Proposed Counter Design using modified Flip-Flop.
clock skew. The circuit has a benefit of minimum power
consumption in the clock network by introducing a A cascade T Flip-Flop structure is used in this system.
combinational logic that mastery the clock based on the The reason for using T Flip-Flop is it concerns for the
Flip-Flop activity. So, by avoiding the unwanted activity changing activity of next state. It eliminates the clock
of clock at the inactive Flip-Flop, the power could be transition when the input of T Flip-Flop is zero. When the
optimized. Fig. 5 gives the design of 4-Bit Existing Binary clock is zero it does not affect the output of the circuit and
Up Counter. in turn maintains the previous state output whereas the
output gets toggled when the clock is one. So, it is evident
that the clock acts as a control signal for the counter. The
III. RESEARCH METHOD OF FLIP-FLOP AND block diagram of proposed counter is shown in Fig. 7.
COUNTER DESIGN

The proposed design uses the positive edge triggered IV. RESULTS AND DISCUSSION
Flip-Flop. In comparison with the conventional Flip-Flop
this TSPCL combined with SVL technique consumes less All the designs are simulated using 250nm CMOS
power. technology library in Tanner EDA TOOL at various
supply level voltages.

A. Simulation Results of Flip-Flop and Counter

The simulation results of the proposed T Flip-Flop design

using TSPCL and SVL technique is shown in Fig. 8.

Fig. 6.Design of Proposed T Flip-Flop with Combined SVL.

Fig. 6 represents the design of projected T Flip-Flop

design with combined SVL. P1 is ON, N2 is ON, P2, P3 are
OFF, N1 and N2 are inactive. In order to perform the
normal D Flip-Flop operation, it is connected to supply and
GND. When a is inactive, P1, N1, N3 are active and P2, N2
are inactive so that out becomes inactive. When a is 1,
which makes P1, N3to inactive state while makes N1, N2
and P2 active state, that is out becomes one. P1, N3 are in Fig. 8 Waveform of T Flip-Flop with Combined SVL.
OFF state i.e. open circuits. N1, N2 are active but as the
supply voltage it gives Vdd-Vth because they acts as a pull-up The input is represented as b and the output is represented
network. When the NMOS transistors re connected in series as Q and CLK as the clock input. During the first positive
it reduces the static power. P2, P3 are active but they gives edge of clock, the input is 0 the output is 0 and maintains the
finite positive voltage as a replacement of GND because same output till the next positive edge. In the second rising
they acts as a pull down network. As the NMOS transistors edge, the given bit is 1 so the result toggled from 0 to 1 and
are used in series it reduces supply voltage and also reduces the output maintains for the falling edge. During the clock’s

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 2020 5th International Conference on Devices, Circuits and Systems (ICDCS)

third rising edge, the input is 1 so the output gets toggled compares the power dissipation results of existing and
from 1 to 0 and the output maintains for the clock’s falling proposed counter for the supply voltages ranges from 2.5V
edge. In the clock signal’s next rising edge, input is 1 so the to 5.0V.
output gets toggled from 0 to 1 and the output maintains for
the falling edge. During the next consecutive rising edge, Table – II: Power Consumption Result of 4 bit up-counter
the input is 1 so the output gets toggled from 1 to 0 and the Design at Different Supply Voltages
output maintains for the negative edge of the clock.
The simulation results of the counter using proposed T AVERAGE POWER CONSUMPTION IN
Flip-Flop is shown in Fig. 9. COUNTER WATTS
DESIGNS
2.5V 3V 3.5V 4V 4.5V 5V

Existing
3.27 3.98 4.65 5.34 6.23 6.82
counter
Proposed
2.92 3.33 3.91 4.45 4.68
counter 2.18

From the Table – II it is shown that the dissipation of

power in proposed counter design is decreased by 33% for
2.5V, 26% for 3V, 28% for 3.5V, 26% for 4V, 28% for
4.5V, 31% for 5V comparing to the existing Flip-Flop.
V. CONCLUSION
Fig. 9.Waveform of Proposed Counter. The consumption of power in the counter is minimized by
using the proposed T Flip-Flop with clock gating technique.
It is 4 bit up-counter which counts from zero to sixteen The T Flip-Flop is proposed by combining TSPCL and SVL
during the clock signal’s positive edge. In the figure 4.2, qa technique. The proposed T Flip-Flop uses only 0.34
represents the first bit, qb represents the second bit, qc microwatt power which is 30% less than the existing T Flip-
represents the third bit and qd represents the fourth bit. In Flop design. The proposed counter design consumes 27%
the simulation result waveform, it counts from zero to four. less power compared to the existing counter design. The
projected T Flip-Flop and counter is designed and simulated
B. Power Comparison Results of Flip-Flop and Counter using the Tanner Tool which employs 250nm CMOS
technology. The proposed counter reduces power
The power dissipation of various Flip-Flop designs and consumption and chip area which maximizes the battery life
counters are compared for different supply voltages. The and performance of the system. Thus, it is witnessed that the
power dissipation result for Flip-Flop design using TSPCL combination of TSPCL, Upper and Lower SVL can be used
and SVL technique is given in the Table - I. to design the low power consuming Flip-Flop used in the
construction of counters. The design is proposed only for 4
Table - I: Power Consumption Result of Flip-Flop Design at bit up-counter, the work can also be extended for the design
Different Supply Voltages of low power consumed wide bit counters. This project
gives only the power comparison result of Flip-Flop and
counter design, area analysis and delay analysis of Flip-Flop
AVERAGE POWER CONSUMPTION IN
FLIP- and counter design at different Supply Voltage can also be
WATTS
FLOP done. Comparing to existing counter, the projected counter
DESIGN design utilizes 27% less power. The future work is to further
2.5V 3V 3.5V 4V 4.5V 5V minimize the power consumption of counter comparing to
the proposed power of counter design.
T Flip-
Flop with
TSPCL
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