INTEGRATED CIRCUITS

DATA SHEET

TDA9321H
I2C-bus controlled TV input
processor
Preliminary specification 2000 Sep 25
Supersedes data of 1998 Dec 16
File under Integrated Circuits, IC02
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

FEATURES
• Multistandard Vision IF (VIF) circuit with Phase-Locked
Loop (PLL) demodulator
• Sound IF (SIF) amplifier with separate input for single
reference Quasi Split Sound (QSS) mode and separate
Automatic Gain Control (AGC) circuit
• AM demodulator without extra reference circuit GENERAL DESCRIPTION
• Switchable group delay correction circuit which can be
The TDA9321H (see Fig.1) is an input processor for
used to compensate the group delay pre-correction of
‘High-end’ television receivers. It contains the following
the B/G TV standard in multistandard TV receivers
functions:
• Several (I2C-bus controlled) switch outputs which can
• Multistandard IF amplifier with PLL demodulator
be used to switch external circuits such as sound traps,
etc. • QSS-IF amplifier and AM sound demodulator
• Flexible source selection circuit with 2 external • CVBS and Y/C switch with various inputs and outputs
CVBS inputs, 2 Luminance (Y) and Chrominance (C) • Multistandard colour decoder which can also decode the
(or additional CVBS) inputs and 2 independently PALplus helper signal
switchable outputs
• Integrated baseband delay line (64 µs)
• Comb filter interface with CVBS output and Y/C input • Sync processor which generates the horizontal and
• Integrated chrominance trap circuit vertical drive pulses for the feature box
• Integrated luminance delay line with adjustable delay (100 Hz applications) or display processor
time (50 Hz applications).
• Integrated chrominance band-pass filter with switchable The supply voltage for the TDA9321H is 8 V.
centre frequency
• Multistandard colour decoder with 4 separate pins for
crystal connection and automatic search system
• PALplus helper demodulator
• Possible blanking of the helper signals for PALplus and
EDTV-2
• Internal baseband delay line
• Two linear RGB inputs with fast blanking; the
RGB signals are converted to YUV signals before they
are supplied to the outputs; one of the RGB inputs can
also be used as YUV input
• Horizontal synchronization circuit with switchable time
constant for the PLL and Macrovision/subtitle gating
• Horizontal synchronization pulse output or clamping
pulse input/output
• Vertical count-down circuit
• Vertical synchronization pulse output
• Two-level sandcastle pulse output
• I2C-bus control of various functions
• Low dissipation.

2000 Sep 25 2
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

ORDERING INFORMATION

TYPE PACKAGE
NUMBER NAME DESCRIPTION VERSION
TDA9321H QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm); SOT319-2
body 14 × 20 × 2.8 mm

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

Supply
VP supply voltage (pins VP1 and VP2) 7.2 8.0 8.8 V
IP supply current (pins VP1 and VP2) − 120 − mA
Input signals
Vi(VIF)(rms) VIF amplifier sensitivity (RMS value) − 35 − µV
Vi(SIF)(rms) SIF amplifier sensitivity (RMS value) − 100 − µV
Vi(CVBS/Y)(p-p) CVBS or Y input signal (peak-to-peak value) − 1.0 − V
Vi(C)(p-p) chrominance input signal (burst amplitude) (peak-to-peak value) − 0.3 − V
Vi(RGB)(p-p) RGB input signal (peak-to-peak value) − 0.7 − V
Output signals
Vo(VIFO)(p-p) demodulated CVBS output signal (peak-to-peak value) − 2.5 − V
Vo(CVBSPIP)(p-p) CVBS output signal for Picture-In-Picture (peak-to-peak value) − 1.0 − V
Vo(CVBSTXT)(p-p) CVBS output signal for teletext (peak-to-peak value) − 2.0 − V
Io(TAGC) tuner AGC output current 0 − 5 mA
Vo(QSS)(rms) QSS output signal (RMS value) − 100 − mV
Vo(AM)(rms) demodulated AM sound output signal (RMS value) − 600 − mV
Vo(V)(p-p) −V output signal (peak-to-peak value) − 1.05 − V
Vo(U)(p-p) −U output signal (peak-to-peak value) − 1.33 − V
Vo(Y)(b-w) Y output signal (black-to-white value) − 1.0 − V
Vo(hor) horizontal pulse output − 5 − V
Vo(ver) vertical pulse output − 5 − V
Vo(sc)(p-p) subcarrier output signal (peak-to-peak value) − 200 − mV

2000 Sep 25 3
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2000 Sep 25

BLOCK DIAGRAM

Philips Semiconductors
handbook, full pagewidth

I2C-bus controlled TV input processor

VIF1 VIF2 DECVIF VIFPLL SIF1 SIF2 DECSIF QSS/AM VP1 VP2 DECDIG DECBG PH1LF HA/CLP SCO VA SCL SDA RI1 GI1 BI1 RGB1
2 3 4 6 63 64 1 5 11 45 33 35 58 60 59 61 46 47 36 37 38 39

VIFVCO1 7 41 RI2
VIF AMPLIFIER 42 GI2
PULSE VERTICAL I2C-BUS
VIFVCO2 AND PLL SIF AMPLIFIER SUPPLY
8 GENERATOR DIVIDER TRANSCEIVER RGB MATRIX 43 BI2
DEMODULATOR AGC
TAGC 62 AGC/AFC 40 RGB2

AFC TOP Y-delay Y U V

49 YO
TDA9321H VCO AND VERTICAL
SOUND VIFO 10 VIDEO AMPLIFIER QSS MIXER Y Y/U/V 50 UO
HORIZONTAL SYNC Y-DELAY
TRAP MUTE AM DEMODULATOR SWITCH 51 VO
PLL SEPARATOR
IDENT
mute
Y U V
GDI 12
GROUP DELAY SYNC
GDO 13 CORRECTION VIDEO SYNC Y-SWITCH BASEBAND
IN-LOCK
IDENTIFICATION SEPARATOR AND TRAPS DELAY LINE
DETECTOR
switch control
4

Y/CVBS
helper
CVBSint 14 R-Y B-Y
AV1 15
AUTOMATIC
CVBS1 16 CLOCHE FILTER fsc SECAM PAL(NTSC)/
CHROMINANCE
FILTER TUNING DECODER SECAM SWITCH
AV2 17 CONTROL
CVBS2 18 53 DECSEC
SW0 19 hue
VIDEO SWITCHES
CVBS/Y3 20 AND
C3 21 CONTROL

SW1 22 PAL/NTSC
Y/C BANDPASS SYSTEM PAL/NTSC
CVBS/Y4 23 PLL
DETECTOR FILTER IDENTIFICATION DEMODULATOR
HUE CONTROL
C4 24
AS 48

34 32 26 25 27 28 29 9 31 44 30 54 55 56 57 52
CVBSTXT CVBSPIP CVBSCF SYS1 SYS2 YCF CCF GND1 GND2 GND3 REFO LFBP MGR473

XTALA

XTALB

XTALC

XTALD

Preliminary specification
subcarrier
COMB FILTER

TDA9321H
Fig.1 Block diagram.
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

PINNING

SYMBOL PIN DESCRIPTION SYMBOL PIN DESCRIPTION

DECSIF 1 SIF AGC decoupling DECDIG 33 digital supply decoupling
VIF1 2 VIF input 1 CVBSTXT 34 CVBS output for teletext
VIF2 3 VIF input 2 DECBG 35 band gap decoupling
DECVIF 4 VIF AGC decoupling RI1 36 red input 1
QSS/AM 5 combined QSS and AM sound output GI1 37 green input 1
VIFPLL 6 VIF PLL filter BI1 38 blue input 1
VIFVCO1 7 VIF VCO tuned circuit 1 RGB1 39 RGB insertion input 1
VIFVCO2 8 VIF VCO tuned circuit 2 RGB2 40 RGB insertion input 2
GND1 9 main supply ground RI2 41 red input 2
VIFO 10 VIF output GI2 42 green input 2
VP1 11 positive supply 1 (+8 V) BI2 43 blue input 2
GDI 12 group delay correction input GND3 44 ground 3
GDO 13 group delay correction output VP2 45 positive supply 2 (+8 V)
CVBSint 14 internal CVBS input SCL 46 serial clock input (I2C-bus)
AV1 15 AV input 1 SDA 47 serial data input/output (I2C-bus)
CVBS1 16 CVBS input 1 AS 48 address select input (I2C-bus)
AV2 17 AV input 2 YO 49 luminance output
CVBS2 18 CVBS input 2 UO 50 U-signal output
SW0 19 switch output bit 0 (I2C-bus) VO 51 V-signal output
CVBS/Y3 20 CVBS or luminance input 3 LFBP 52 loop filter burst phase detector
C3 21 chrominance input 3 DECSEC 53 SECAM PLL decoupling
SW1 22 switch output bit 1 (I2C-bus) XTALA 54 crystal A (4.433619 MHz)
CVBS/Y4 23 CVBS or luminance input 4 XTALB 55 crystal B (3.582056 MHz)
C4 24 chrominance input 4 XTALC 56 crystal C (3.575611 MHz)
SYS1 25 system output 1 for comb filter XTALD 57 crystal D (3.579545 MHz)
CVBSCF 26 CVBS output for comb filter PH1LF 58 phase 1 loop filter
SYS2 27 system output 2 for comb filter SCO 59 sandcastle pulse output
YCF 28 luminance input from comb filter HA/CLP 60 horizontal pulse output or clamp pulse
CCF 29 chrominance input from comb filter input/output
REFO 30 reference output (subcarrier) VA 61 vertical pulse output
GND2 31 digital supply ground TAGC 62 tuner AGC output
CVBSPIP 32 CVBS output for Picture-In-Picture SIF1 63 SIF input 1
SIF2 64 SIF input 2

2000 Sep 25 5
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

53 DECSEC
handbook, full pagewidth

60 HA/CLP

57 XTALD

56 XTALC

55 XTALB

54 XTALA
58 PH1LF
62 TAGC

52 LFBP
59 SCO
64 SIF2

63 SIF1

61 VA

DECSIF 1 51 VO

VIF1 2 50 UO

VIF2 3 49 YO

DECVIF 4 48 AS

QSS/AM 5 47 SDA

VIFPLL 6 46 SCL

VIFVCO1 7 45 VP2

VIFVCO2 8 44 GND3

GND1 9 43 BI2

VIFO 10 TDA9321H 42 GI2

VP1 11 41 RI2

GDI 12 40 RGB2

GDO 13 39 RGB1

CVBSint 14 38 BI1

AV1 15 37 GI1

CVBS1 16 36 RI1

AV2 17 35 DECBG

CVBS2 18 34 CVBSTXT

SW0 19 33 DECDIG
CVBS/Y3 20

C3 21

SW1 22

CVBS/Y4 23

C4 24

SYS1 25

CVBSCF 26

SYS2 27

YCF 28

CCF 29

REFO 30

GND2 31

CVBSPIP 32

MGR474

Fig.2 Pin configuration.

2000 Sep 25 6
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

FUNCTIONAL DESCRIPTION The input of the ident circuit is connected to pin 14

(see Fig.3). This has the advantage that the ident circuit
Vision IF amplifier
can also be activated when a scrambled signal is received
The VIF amplifier contains three AC-coupled control (descrambler connected between the IF video output
stages with a total gain control range higher than 66 dB. (pins 10 and 14). A second advantage is that the ident
The sensitivity of the circuit is comparable with that of circuit can be used when the VIF amplifier is not used (e.g.
modern IF-ICs. with built-in satellite tuners). The video ident circuit can
also be used to identify the selected CBVS or Y/C signal.
The video signal is demodulated by a PLL carrier
The switching between the two modes can be realized with
regenerator, which contains a frequency detector and
bit VIM.
a phase detector. During acquisition, the frequency
detector tunes the VCO to the correct frequency. The initial The TDA9321H contains a group delay correction circuit
adjustment of the oscillator is realized via the I2C-bus. The which can be switched between the BG and a flat group
switching between SECAM L and L’ can also be realized delay response characteristic. This has the advantage that
via the I2C-bus. After lock-in, the phase detector controls no compromise has to be made in multistandard receivers
the VCO so that a stable phase relationship between for the choice of the SAW filter. Both the input and output
the VCO and the input signal is achieved. The VCO of the group delay correction circuit are externally
operates at twice the IF frequency. The reference signal available, so that the sound trap can be connected
for the demodulator is obtained by means of a frequency between the IF video output and the group delay
divider circuit. To get good performance for phase correction input. The output signal of the correction circuit
modulated carrier signals, the control speed of the PLL can can be supplied to the video processing circuit and to the
be increased by bit FFI. external SCART plug.
The AFC output is obtained by using the VCO control The IC has several (I2C-bus controlled) output ports which
voltage of the PLL and can be read via the I2C-bus. For can be used to switch sound traps or other external
fast search tuning systems, the window of the AFC can be components.
increased with a factor 3. The setting is realized with
When the VIF amplifier is not used, the complete
bit AFW.
VIF amplifier can be switched off with bit IFO via the
The AGC detector operates on top sync and top white I2C-bus.
level. The demodulation polarity is switched via the
I2C-bus. The AGC detector time constant capacitor is Sound circuit
connected externally: mainly because of the flexibility of
The SIF amplifier is similar to the VIF amplifier and has
the application. The time constant of the AGC system
a gain control range of approximately 66 dB. The
during positive modulation is rather long, to avoid visible
AGC circuit is related to the SIF carrier levels (average
variations of the signal amplitude. To improve the speed of
level of AM or FM carriers) and ensures a constant signal
the AGC system, a circuit is included that detects whether
amplitude of the AM demodulator and the QSS mixer.
the AGC detector is activated every frame period. When
no action is detected during three field periods, the speed The single reference QSS mixer is realized by a multiplier.
of the system is increased. For signals without peak white This multiplier converts the SIF signal to the intercarrier
information, the system automatically switches to a gated frequency by mixing it with the regenerated picture carrier
black level AGC. Because a black level clamp pulse is from the VCO. The mixer output signal is supplied to the
required for this mode of operation, the circuit only output via a high-pass filter to attenuate the residual video
switches to black level AGC in the internal mode. signals. With this system, a high performance hi-fi stereo
sound processing can be achieved.
The circuit contains a video identification (ident) circuit
which is independent of the synchronization circuit. The AM sound demodulator is realized by a multiplier. The
Therefore, search tuning is possible when the display modulated SIF signal is multiplied in phase with the limited
section of the receiver is used as a monitor. However, this SIF signal. The demodulator output signal is supplied to
ident circuit cannot be made as sensitive as the slower the output via a low-pass filter to attenuate the carrier
sync ident circuit (bit SL) and we recommend the use of harmonics.
both ident outputs to obtain a reliable search system. The
ident output is supplied to the tuning system via the
I2C-bus.

2000 Sep 25 7
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

Video switches The luminance output signal which is derived from the
incoming CVBS or Y/C signal can be varied in amplitude
The circuit has three CVBS inputs (one internal and two
by means of a separate gain setting control via the I2C-bus
external inputs) and two Y/C inputs. The Y/C inputs can
control bits GAI1 and GAI0. The gain variation which can
also be used as additional CVBS inputs. The switch
be realized with these bits is −1 to +2 dB.
configuration is given in Fig.3. The various sources are
selected via the I2C-bus.
Colour decoder
The circuit can be set in a mode in which it automatically
The colour decoder can decode PAL, NTSC and SECAM
detects whether a CVBS or a Y/C signal is supplied to the
signals. The PAL/NTSC decoder contains an
Y/C inputs. In this mode, the TV standard is first identified
alignment-free crystal oscillator with four separate crystal
on the added Y/CVBS and the C input signal. Then, both
pins, a killer circuit and two colour difference
chrominance input signal amplitudes are checked once
demodulators. The 90° phase shift for the reference signal
and the input signal with the highest burst signal amplitude
is made internally.
is selected. The result of the detection can be read via the
I2C-bus. Because it is possible to connect four different crystals to
the colour decoder, all colour standards can be decoded
The IC has two inputs (AV1 and AV2), which can be used
without external switching circuits. Which crystals are
to read the status levels of pin 8 of the SCART plug. The
connected to the decoder must be indicated via the
information is available in the output status byte 02 in
I2C-bus. The crystal connection pins that are not used
bits D0 to D3.
must be left open circuit.
The three outputs of the video switch (CVBSTXT,
The horizontal oscillator is calibrated by means of the
CVBSPIP and COMBCVBS) can be independently
crystal frequency of the colour PLL. For a reliable
switched to the various input signals. The names are just
calibration, it is very important that crystal indication
arbitrary and it is for instance possible to use the
bits XA to XD are not corrupted. For this reason, the
COMBCVBS signal to drive the comb filter and the teletext
crystal bits can be read in the output bytes so that the
decoder in parallel and to supply the CVBSTXT signal to
software can check the I2C-bus transmission.
the SCART plug (via an emitter follower).
The ICs contain an Automatic Colour Limiting (ACL)
For comb filter interfacing, the circuit has the COMBCVBS
circuit, which can be switched via the I2C-bus and which
output, a third Y/C input, a reference signal output (fsc) and
prevents oversaturation occurring when signals with a high
two control pins which switch the comb filter to the
chrominance-to-burst ratio are received. The ACL circuit is
standard of the incoming signal (as detected by the ident
designed such that it only reduces the chrominance signal
circuit of the colour decoder). When the comb filter is
and not the burst signal. This has the advantage that the
enabled by bit ECMB and a signal is recognized which can
colour sensitivity is not affected by this function. The
be combed, the Y/C signals coming from the comb filter
ACL function is mainly intended for NTSC signals but it
are automatically selected if the original source is a CVBS
can also be used for PAL signals. For SECAM signals, the
signal, indicated via the CMB-bit in output status
ACL function should be switched off.
byte 02 (D5). For signals which cannot be combed (like
SECAM or Black-to-White signals) and for Y/C input The SECAM decoder contains an auto-calibrating
signals, the Y/C signals coming from the comb filter are not PLL demodulator which has two references: the 4.43 MHz
selected. sub-carrier frequency (which is obtained from the crystal
oscillator which is used to tune the PLL to the desired
Chrominance and luminance processing free-running frequency) and the bandgap reference (to
obtain the correct absolute value of the output signal). The
The circuits contain a chrominance bandpass, a SECAM
VCO of the PLL is calibrated during each vertical blanking
cloche filter and a chrominance trap circuit. The filters are
period, when the IC is in search or SECAM mode.
realized by means of gyrator circuits and they are
automatically calibrated by comparing the tuning The circuit can also decode the PALplus helper signal and
frequency with the crystal frequency of the decoder. The can insert the various reference signals, set-ups and
luminance delay line is also realized by means of gyrator timing signals which are required for the PALplus decoder
circuits. The centre frequency of the chrominance ICs.
bandpass filter is switchable via the I2C-bus so that the
The baseband delay line (TDA4665 function) is integrated.
performance can be optimized for ‘front-end’ signals and
external CVBS signals.

2000 Sep 25 8
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2000 Sep 25

Philips Semiconductors
handbook, full pagewidth

I2C-bus controlled TV input processor

VIM

VIDEO
ident
IDENTIFICATION
TDA9321H

to luminance/sync
processing

to chrominance
processing

+
9

14 16 18 20 21 23 24 28 29 26 34 32

CVBSint CVBS1 CVBS2 CVBS/Y3 C3 CVBS/Y4 C4 YCF CCF CVBSCF CVBSPIP

CVBSTXT

MGR475

Preliminary specification
TDA9321H
Fig.3 Video switches and interfacing of video ident.
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

RGB switch and matrix If required, the IC can select the time constant, depending
on the noise content of the incoming video signal.
The IC has two RGB inputs with fast switching. The
switching of the various sources is controlled via the The free-running frequency of the oscillator is determined
I2C-bus and the condition of the switch inputs can be read by a digital control circuit, which is locked to the reference
from the I2C-bus status bytes. If the RGB signals are not signal of the colour decoder. When the IC is switched on,
synchronous with the selected decoder input signal, an the HA/CLP is suppressed and the oscillator is calibrated
external clamp pulse has to be supplied to the HA/CLP as soon as all sub-address bytes have been sent. When
input. The IC must be set in this mode via the I2C-bus. In the frequency of the oscillator is correct, the HA/CLP signal
this case, the VA pulse is suppressed by switching the is switched on again.
VA output to a high impedance OFF state.
When the coincidence detector indicates an out-of-lock
When an external RGB signal is mixed into the internal situation, the calibration procedure is repeated.
YUV signal, it is necessary to switch-off the PALplus
The VA pulse is obtained via a vertical countdown circuit.
demodulation. To detect the presence of a fast blanking,
This circuit has various windows, depending on the
a circuit is added which forces the MACP and HD bits to
incoming signal (50 or 60 Hz standard or no standard).
zero if a blanking pulse is detected in two consecutive
The countdown circuit can be forced to various modes by
lines. This system is chosen to prevent switching off at
means of the I2C-bus. To obtain short switching times of
every spike that is detected on the fast blanking input.
the countdown circuit during a channel change, the divider
The IC can use input RGB1 as YUV input. This function can be forced in the search window by means of bit NCIN.
can be enabled by bit YUV in subaddress 0A (D3). When
switched to the YUV input, the input signals must have the
same amplitude and polarity as the YUV output signals. I2C-BUS SPECIFICATION
The Y signal has to be supplied to the G1 input, the The slave addresses of the ICs are given in Table 1. The
U signal to the B1 input and the V signal to the R1 input. circuit operates up to clock frequencies of 400 kHz.

Synchronization circuit Table 1 Slave addresses

The sync separator is preceded by a controlled amplifier A6 A5 A4 A3 A2 A1 A0 R/W
that adjusts the sync pulse amplitude to a fixed level.
1 0 0 0 1 A1 1 1/0
These pulses are fed to the slicing stage, which operates
at 50% of the amplitude. The separated sync pulses are
fed to the phase detector and to the coincidence detector. Bit A1 is controlled via pin 48 (AS). When the pin is
This detector detects whether the line oscillator is connected to ground, it is a logic 0; when connected to the
synchronized and can also be used for transmitter positive supply line, it is a logic 1. When this pin is left
identification. This circuit can be made less sensitive by open, it is connected to ground via an internal resistor.
means of bit STM. This mode can be used during search
tuning to avoid the tuning system from stopping at very Start-up procedure
weak input signals. The PLL has a very high static
Read the status bytes until POR = logic 0 and send all
steepness so that the phase of the picture is independent
subaddress bytes. Check the bus transmission by reading
of the line frequency.
output status bits SXA to SXD. This ensures good
Two conditions are possible for the horizontal output operation of the calibration system of the horizontal
pulse: oscillator. The horizontal output signal is switched on when
• An HA pulse which has a phase and width that are the oscillator is calibrated.
identical to the incoming horizontal sync pulse Read the status bytes each time before the data in the IC
• A Clamp Pulse (CLP) which has a phase and width that is refreshed. If POR = logic 1, the procedure mentioned
are identical to the clamp pulse in the sandcastle pulse. above must be carried out to restart the IC. When this
procedure is not followed, the horizontal frequency may be
Signal HA/CLP is generated by an oscillator that runs at
incorrect after power-up or after a power dip.
a frequency of 440 × fH. Its frequency is divided by 440 to
lock the first loop to the incoming signal. The time constant The 00 to 0E subaddresses are valid. The
of the loop can be forced by the I2C-bus (fast or slow). FE and FF subaddresses are reserved for test purposes.
The auto-increment mode is available for subaddresses.

2000 Sep 25 10
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

Inputs and outputs

Table 2 Input status bits

SUBADDRESS DATA BYTE

FUNCTION
(HEX) D7 D6 D5 D4 D3 D2 D1 D0
Colour decoder 0 00 CM3 CM2 CM1 CM0 XD XC XB XA
Colour decoder 1 01 MACP HOB HBC HD FCO ACL CB BPS
Luminance 02 0 0 GAI1 GAI0 YD3 YD2 YD1 YD0
Hue control 03 0 0 A5 A4 A3 A2 A1 A0
Spare 04 0 0 0 0 0 0 0 0
Synchronization 0 05 FORF FORS FOA FOB 0 VIM POC VID
Synchronization 1 06 0 0 0 0 BSY HO EMG NCIN
Spare 07 0 0 0 0 0 0 0 0
Video switches 0 08 0 0 0 ECMB DEC3 DEC2 DEC1 DEC0
Video switches 1 09 0 PIP2 PIP1 PIP0 0 TXT2 TXT1 TXT0
RGB switch 0A 0 0 0 0 YUV ECL IE2 IE1
Output switches 0B 0 0 0 0 0 0 OS1 OS0
Vision IF 0C FFI IFO GD MOD AFW IFS STM VSW
Tuner takeover 0D 0 0 A5 A4 A3 A2 A1 A0
Adjustment IF-PLL 0E L’FA A6 A5 A4 A3 A2 A1 A0

INPUT CONTROL BITS Table 4 Crystal indication

Table 3 Colour decoder mode XA to XD CONDITION
CM3 CM2 CM1 CM0 DECODER MODE XTAL 0 crystal not present
0 0 0 0 PAL/NTSC/SECAM A 1 crystal present; note 1
0 0 0 1 PAL/NTSC A Note
0 0 1 0 PAL A 1. When a comb filter is used, the various crystals must
0 0 1 1 NTSC A be connected to the IC as indicated in the pinning
0 1 0 0 SECAM A diagram. This is required because the ident system
switches automatically to the comb filter when a signal
0 1 0 1 PAL/NTSC B
is identified which can be combed (correct
0 1 1 0 PAL B combination of colour standard and crystal frequency).
0 1 1 1 NTSC B For applications without comb filter only the crystal on
1 0 0 0 PAL/NTSC/SECAM A/B/C/D pin XTALA is important (4.43 MHz); to pins XTALB to
XTALD an arbitrary 3.5 MHz crystal can be connected.
1 0 0 1 PAL/NTSC C
1 0 1 0 PAL C
1 0 1 1 NTSC C
1 1 0 0 PAL/NTSC A/B/C/D
1 1 0 1 PAL/NTSC D
1 1 1 0 PAL D
1 1 1 1 NTSC D

2000 Sep 25 11
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

Table 5 Motion Adaptive Colour Plus (MACP) Table 10 Chrominance band-pass centre frequency
MACP MODE CB CENTRE FREQUENCY
0 internal 4.43 MHz trap used 0 fc
1 external MACP chrominance filtering used; 1 1.1 × fc
4.43 MHz trap bypassed and black set-up
200 mV; note 1 Table 11 Bypass of chrominance baseband delay line
Note BPS DELAY LINE MODE
1. The black set-up will only be present in a norm sync 0 active
condition. 1 bypassed

Table 6 Helper output blanking (PALplus/EDTV-2)

Table 12 Gain luminance channel
HOB HBC SNR BLANKING
GAI1 GAI0 GAIN SETTING
0 X(1) X(1) off
0 0 −1 dB
1 0 X(1) on
0 1 0 dB
1 1 0 off
1 0 +1 dB
1 1 1 on
1 1 +2 dB
Note
Table 13 Y-delay adjustment; notes 1 and 2
1. X = don’t care.
YD0 to YD3 Y-DELAY
Table 7 PALplus helper demodulation active
YD3 YD3 × 160 ns
HD CONDITIONS YD2 YD2 × 160 ns
0 off YD1 YD1 × 80 ns
1 on; PALplus mode with helper set-up 400 mV YD0 YD0 × 40 ns
and black set-up 200 mV; note 1
Notes
Note 1. For an equal delay of the luminance and chrominance
1. Black and helper set-up will only be present in a norm signal the delay must be set at a value of 280 ns
sync condition. (YD3 to YD0 = 1011). This is only valid for a CVBS
signal without group delay distortions.
Table 8 Forced colour on 2. The total Y-delay is the addition of:
FCO MODE YD3 + YD2 + YD1 + YD0.

0 not active Table 14 Forced field frequency

1 active
FORF FORS FIELD FREQUENCY
Table 9 Automatic colour limiting 0 0 auto (60 Hz when line not
synchronized)
ACL COLOUR LIMITING
0 1 forced 60 Hz; note 1
0 not active
1 0 keep last detected field frequency
1 active
1 1 auto (50 Hz when line not
synchronized)

Note
1. When switched to this mode the divider will directly
switch to forced 60 Hz only.

2000 Sep 25 12
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

Table 15 Phase 1 (ϕ1) time constant; see also Table 57 Table 19 Blanked sync on pin YO

FOA FOB MODE BSY CONDITIONS

0 0 normal 0 unblanked sync; note 1
0 1 slow 1 blanked sync
1 0 slow or fast Note
1 1 fast
1. Except for PALplus with black set-up.

Table 16 Video ident mode Table 20 Condition of horizontal output

VIM MODE HO CONDITIONS
0 ident coupled to internal CVBS (pin 14) 0 clamp pulse available on pin HA/CLP
1 ident coupled to selected CVBS 1 horizontal pulse available on pin HA/CLP

Table 17 Synchronization mode Table 21 Enable ‘Macrovision/subtitle’ gating

POC MODE EMG MODE
0 active 0 disable gating
1 not active 1 enable gating

Table 18 Video ident mode Table 22 Vertical divider mode

VID VIDEO IDENT MODE NCIN VERTICAL DIVIDER MODE
0 ϕ1 loop switched-on and off 0 normal operation
1 not active 1 switched to search window

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I2C-bus controlled TV input processor TDA9321H

Table 23 Video switch control

ECMB(1) DEC3 DEC2 DEC1 DEC0 SELECTED SIGNAL SIGNAL TO COMB
0 0 0 0 X(2) CVBSint CVBSint
0 0 0 1 0 CVBS1 CVBS1
0 0 0 1 1 CVBS2 CVBS2
0 0 1 0 0 CVBS3 CVBS3
0 0 1 0 1 Y3/C3 Y3 + C3
0 0 1 1 0 CVBS4 CVBS4
0 0 1 1 1 Y4/C4 Y4 + C4
0 1 1 0 0 AUTO Y3/C3; note 3 CVBS3 or Y3 + C3
0 1 1 1 0 AUTO Y4/C4; note 3 CVBS4 or Y4 + C4
1 0 0 0 X(2) YCF/CCF CVBSint
1 0 0 1 0 YCF/CCF CVBS1
1 0 0 1 1 YCF/CCF CVBS2
1 0 1 0 0 YCF/CCF CVBS3
1 0 1 1 0 YCF/CCF CVBS4
1 1 1 0 0 AUTO COMB3; note 4 CVBS3 or Y3 + C3
1 1 1 1 0 AUTO COMB4; note 4 CVBS4 or Y4 + C4

Notes
1. When bit ECMB = 1 the subcarrier frequency is present on pin 30. The YCF and CCF signals coming from the comb
filter are only switched on when a signal is received that can be combed.
2. X = don’t care.
3. AUTO YC means the decoder switches between CVBS and Y/C depending on the presence of the burst signal on
these signals.
4. AUTO COMB means the decoder switches to Y/C mode if the burst is present on the C input and to the comb filter
output if the burst is present on the CVBS signal.

Table 24 Video switch outputs Table 25 Enable YUV input (on RGB1 input)
TXT2 TXT1 TXT0 OUTPUT SIGNAL TXT YUV MODE
PIP2 PIP1 PIP0 OUTPUT SIGNAL PIP 0 RGB1 input active
0 0 − CVBSint 1 YUV input active
0 1 0 CVBS1
0 1 1 CVBS2 Table 26 External RGB clamp mode
1 0 0 CVBS3 ECL MODE
1 0 1 Y3 + C3 0 off; internal clamp pulse used
1 1 0 CVBS4 1 on; external clamp pulse has to be supplied to
1 1 1 Y4 + C4 pin HA/CLP

2000 Sep 25 14
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

Table 27 Enable fast blanking RGB1 Table 33 Modulation standard

IE1 FAST BLANKING MOD MODULATION
0 not active 0 negative
1 active 1 positive

Table 28 Enable fast blanking RGB2 Table 34 AFC window

IE2 FAST BLANKING AFW AFC WINDOW
0 not active 0 normal
1 active 1 enlarged

Table 29 Output switches OS0 and OS1 Table 35 IF sensitivity

OS0; IFS IF SENSITIVITY
CONDITIONS
OS1 0 normal
0 output = LOW 1 reduced
1 output = HIGH
Table 36 Search tuning mode
Table 30 Fast filter IF-PLL
STM MODE
FFI CONDITIONS 0 normal operation
0 normal time constant 1 reduced sensitivity of video ident circuit
1 fast time constant
Table 37 Video mute
Table 31 IF circuit not active
VSW STATE
IFO MODE 0 normal operation
0 normal operation of IF amplifier 1 VIF signal switched off
1 IF amplifier switched off
Table 38 PLL demodulator frequency shift
Table 32 Group delay correction
L’FA MODE
GD GROUP DELAY CHARACTERISTIC 0 normal IF frequency
0 flat 1 frequency shift for L’ standard
1 according to BG standard

Table 39 Output status bits

SUBADDRESS DATA BYTE

FUNCTION
(HEX) D7 D6 D5 D4 D3 D2 D1 D0
Output status bytes 00 POR X(1) X(1) X(1) SNR FSI SL IVW
01 CD3 CD2 CD1 CD0 SXD SXC SXB SXA
02 IN1 IN2 CMB YC S2A S2B S1A S1B
03 ID3 ID2 ID1 ID0 IFI PL AFA AFB

Note
1. X = don’t care.

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Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

OUTPUT CONTROL BITS Table 43 Phase 1 (ϕ1) lock indication

Table 40 Power-on reset SL INDICATION
POR MODE 0 not locked
0 normal 1 locked
1 power-down
Table 44 Condition vertical divider
Table 41 Signal-to-noise ratio of sync signal IVW STANDARD VIDEO SIGNAL
SNR SIGNAL-TO-NOISE RATIO 0 no standard video signal
0 S/N > 20 dB 1 standard video signal in ‘narrow window’ or
standard TV norm (525 or 625 lines)
1 S/N < 20 dB

Table 45 Crystal indication (SXA to SXD)

Table 42 Field frequency indication
SXA to
FSI FREQUENCY CONDITIONS
SXD
0 50 Hz
0 no crystal connected
1 60 Hz
1 crystal connected

Table 46 Colour decoder mode

CD3 CD2 CD1 CD0 STANDARD XTAL
0 0 0 0 no colour standard identified A/B/C/D
0 0 0 1 NTSC A
0 0 1 0 PAL A
0 0 1 1 NTSC B
0 1 0 0 PAL B
0 1 0 1 NTSC C
0 1 1 0 PAL C
0 1 1 1 NTSC D
1 0 0 0 PAL D
1 0 0 1 SECAM A
1 0 1 0 illegal forced mode; note 1 −

Note
1. This mode is generated when trying (e.g. via software control) to force the decoder to a standard with a crystal which
is not connected to the IC.

2000 Sep 25 16
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

Table 47 Indication RGB1/RGB2 insertion Table 51 Output video identification

IN1; IFI VIDEO SIGNAL
RGB INSERTION
IN2 0 no video signal identified
0 no insertion 1 video signal identified
1 full insertion
Table 52 In-lock indication IF-PLL
Table 48 Condition YCF/CCF inputs from comb filter
PL CONDITIONS
CMB CONDITION YCF/CCF INPUTS 0 PLL not locked
0 not selected 1 PLL locked
1 selected
Table 53 AFC output
Table 49 Input signal condition; note 1
AFA AFB CONDITIONS
YC CONDITIONS 0 0 outside window; too low
0 CVBS signal available 0 1 outside window; too high
1 Y/C signal available 1 0 in window; below reference
Note 1 1 in window; above reference
1. During the search mode for the colour system, bit YC
Table 54 IC version indication
will indicate logic 1.
ID3 ID2 ID1 ID0 IC TYPE
Table 50 Condition of AV1 and AV2 inputs
0 0 0 1 TDA9321HN1
S1A; S1B; 1 0 0 1 TDA9321HN2
CONDITIONS
S2A S2B
0 0 no external source
0 1 external source with 4 : 3 input
signal
1 0 external source with 16 : 9 input
signal

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Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VP supply voltage on pins VP1 and VP2 − 9.0 V
Tstg storage temperature −25 +150 °C
Tamb operating ambient temperature 0 70 °C
Tsld soldering temperature for 5 s − 260 °C
Tj junction temperature − 150 °C
Ves electrostatic handling on all pins notes 1 and 2 −3000 +3000 V
notes 1 and 3 −300 +300 V

Notes
1. All pins are protected against ESD by means of internal clamping diodes.
2. Human Body Model (HBM): R = 1.5 kΩ; C = 100 pF.
3. Machine Model (MM): R = 0 Ω; C = 200 pF.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-a) thermal resistance from junction to ambient in free air 50 K/W

QUALITY SPECIFICATION
Quality specification in accordance with “SNW-FQ-611E”.

Latch-up performance
At an ambient temperature of 70 °C all pins meet the following specification:
• Positive stress test: Itrigger ≥ 100 mA or Vpin ≥ 1.5 × VP(max)
• Negative stress test: Itrigger ≤ −100 mA or Vpin ≤ −0.5 × VP(max).

2000 Sep 25 18
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

CHARACTERISTICS
VP = 8 V; Tamb = 25 °C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply (pins VP1 and VP2); note 1
VP supply voltage (pins VP1 and VP2) 7.2 8.0 8.8 V
IP supply current (pins VP1 and VP2) − 120 140 mA
Ptot total power dissipation − 960 − mW
Vision IF circuit
VISION IF AMPLIFIER INPUTS (PINS VIF1 AND VIF2)
Vi(rms) input sensitivity (RMS value) note 2
fi(VIF) = 38.90 MHz − 35 200 µV
fi(VIF) = 45.75 MHz − 35 200 µV
fi(VIF) = 58.75 MHz − 40 200 µV
Vi(max)(rms) maximum input signal (RMS value) 150 200 − mV
Ri(dif) differential input resistance note 3 − 2 − kΩ
Ci(dif) differential input capacitance note 3 − 3 − pF
∆Gv voltage gain control range 64 75 80 dB
PLL DEMODULATOR (PLL FILTER ON PIN VIFPLL); note 4
fPLL PLL frequency range 32 − 60 MHz
fcr(PLL) PLL catching range 2.0 2.7 3.3 MHz
tacq(PLL) PLL acquisition time − − 20 ms
∆fVCO/∆T VCO frequency dependency with notes 5 and 6 − 300 − kHz/K
temperature
ftune(VCO) VCO tuning frequency range via I2C-bus 3.0 3.7 4.2 MHz
∆fDAC frequency variation per step of the 23 29 33 kHz
DAC (A0 to A6)
fshift frequency shift with bit L’FA − 5.5 − MHz
VIDEO AMPLIFIER OUTPUT (PIN VIFO); note 7
Vo(z) zero signal output level note 8
negative modulation 4.6 4.7 4.8 V
positive modulation 1.9 2.0 2.1 V
Vo(ts) top-sync level negative modulation 1.9 2.0 2.1 V
Vo(w) white level positive modulation 4.4 4.5 4.6 V
∆Vo difference in amplitude between − 0 15 %
negative and positive modulation
Zo(v) video output impedance − 50 − Ω
Ibias(int) internal bias current of NPN 1.0 − − mA
emitter follower output transistor
Isource(max) maximum source current − − 5 mA
Bv(−3dB) −3 dB bandwidth of demodulated 6 8 10 MHz
output signal
Gdif differential gain note 9 − − 1.5 %

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Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

ϕdif differential phase notes 6 and 9 − − 2.5 deg
NLvid video non-linearity note 10 − 3 5 %
Vclamp white spot clamping level − 6.0 − V
Nclamp noise inverter clamping level note 11 − 1.5 − V
Nins noise inverter insertion level note 11 − 2.7 − V
(identical to black level)
dblue intermodulation at ‘blue’ notes 6 and 12
f = 0.92 or 1.1 MHz 60 66 − dB
f = 2.66 or 3.3 MHz 60 66 − dB
dyellow intermodulation at ‘yellow’ notes 6 and 12
f = 0.92 or 1.1 MHz 56 62 − dB
f = 2.66 or 3.3 MHz 60 66 − dB
S/NW weighted signal-to-noise ratio notes 6 and 13 56 60 65 dB
S/NUW unweighted signal-to-noise ratio notes 6 and 13 49 53 − dB
∆Vrc residual carrier signal note 6 − 5.5 − mV
∆Vrc(2H) 2nd harmonic of residual carrier note 6 − 2.5 − mV
signal
PSRR power supply ripple rejection at the output − 40 − dB
VIF AND TUNER AGC; note 14
Timing of VIF-AGC with a 2.2 µF capacitor (pin DECVIF)
MVI modulated video interference 60% AM for 1 to 100 mV; − − 10 %
0 to 200 Hz; system B/G
tres response time VIF input signal amplitude − 2 − ms
increase of 52 dB; positive
and negative modulation
VIF input signal amplitude
decrease of 52 dB
negative modulation − 50 − ms
positive modulation − 100 − ms
IL leakage current of the capacitor on negative modulation − − 10 µA
pin 4 positive modulation − − 200 nA
∆Vo(v) change in video output signal capacitor on pin 4 is 0.5 µF − − 2 %
amplitude over 1 vertical period for
peak white AGC at positive
modulation
Tuner takeover point adjustment (via I2C-bus)
Vstrt(min)(rms) minimum start level (RMS value) − 0.4 0.8 mV
Vstrt(max)(rms) maximum start level (RMS value) 100 150 − mV
∆Vmax maximum variation with Tamb = 0 to 70 °C − 6 8 dB
temperature

2000 Sep 25 20
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Tuner control output (pin TAGC)
Vo(max) maximum output voltage maximum tuner gain; note 3 − − 9 V
Vo(sat) output saturation voltage minimum tuner gain; − − 300 mV
Io = 2 mA
Io(max) maximum output current swing 5 − − mA
IL leakage current for RF AGC − − 1 µA
∆Vi input signal variation for complete tuner control 0.5 2 4 dB
AFC OUTPUT (VIA I2C-BUS); note 15
RESAFC AFC resolution − 2 − bits
∆fw window sensitivity normal window mode 55 65 90 kHz
enlarged window mode 175 195 270 kHz
VIDEO IDENTIFICATION OUTPUT (VIA I2C-BUS)
td delay time for identification after the − − 10 ms
AGC has stabilized on a new
transmitter
Sound IF circuit
SOUND IF AMPLIFIER (PINS SIF1 AND SIF2)
Vi(rms) input sensitivity (RMS value) FM mode (−3 dB) − 100 140 µV
AM mode (−3 dB) − 200 300 µV
Vi(max)(rms) maximum input signal (RMS value) FM mode 50 70 − mV
AM mode 80 140 − mV
Ri(dif) differential input resistance note 3 − 2 − kΩ
Ci(dif) differential input capacitance note 3 − 3 − pF
∆Gv voltage gain control range 64 − − dB
αct(SIF-VIF) crosstalk between inputs SIF 50 − − dB
and VIF
QSS AND AM SOUND OUTPUT (PIN QSS/AM)
General
Ro output resistance − − 250 Ω
VO DC output voltage − 3.3 − V
Ibias(int) internal bias current of emitter 0.7 1.0 − mA
follower
Isink(max) maximum AC and DC sink current − 0.7 − mA
Isource(max) maximum AC and DC source − 2.0 − mA
current

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Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

QSS output signal
Vo(rms) output signal amplitude SC1 on; SC2 off 70 90 110 mV
(RMS value)
B−3dB −3 dB bandwidth 7.5 9 − MHz
∆Vr(SC)(rms) residual IF sound carrier − 2 − mV
(RMS value)
S/NW weighted signal-to-noise ratio ratio of PC/SC1 at VIF input
(SC1/SC2) of 40 dB or higher; note 16
black picture 53/48 58/55 − dB
white picture 52/47 55/53 − dB
6 kHz sine wave 44/42 48/46 − dB
(black-to-white modulation)
250 kHz sine wave 44/25 48/30 − dB
(black-to-white modulation)
SC subharmonics 45/44 51/50 − dB
(f = 2.75 MHz ±3 kHz)
SC subharmonics 46/45 52/51 − dB
(f = 2.87 MHz ±3 kHz)
AM output signal
Vo(rms) output signal amplitude 54% modulation 500 600 700 mV
(RMS value)
THD total harmonic distortion − 0.5 1.0 %
B−3dB −3 dB bandwidth 100 125 − kHz
S/NW weighted signal-to-noise ratio 47 53 − dB
Video switches and comb filter interface
VIDEO SWITCHES FOR CVBS, Y AND C SIGNALS
Signal on pins CVBSint, CVBS1, CVBS2, CVBS/Y3 and CVBS/Y4
Vi(n)(p-p) input voltage (peak-to-peak value) note 17 − 1.0 1.43 V
Ii(n) input current − 4 − µA
Zsource(max) maximum source impedance − − 1.0 kΩ
αsup(n) suppression of non-selected fi = 0 to 5 MHz; note 6 50 − − dB
signals
Signal on pins C3 and C4
Vi(n)(p-p) input voltage (peak-to-peak value) notes 3 and 18 − 0.3 1.0 V
Zi(n) input impedance − 50 − kΩ

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Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Signal on pin CVBSTXT
Vo(p-p) output signal amplitude 1.6 2.0 2.4 V
(peak-to-peak value)
Vbl black level − 2.6 − V
∆Vbl/∆T black level dependency with − 4 − mV/K
temperature
Zo output impedance − − 250 Ω
Signal on pin CVBSPIP
Vo(p-p) output signal amplitude 0.8 1.0 1.2 V
(peak-to-peak value)
Vbl black level − 3.6 − V
∆Vbl/∆T black level dependency with − 9 − mV/K
temperature
Zo output impedance − − 250 Ω
COMB FILTER INTERFACE; note 19
Signal on pin CVBSCF
Vo(p-p) output signal amplitude 0.8 1.0 1.2 V
(peak-to-peak value)
Zo output impedance − − 250 Ω
Vbl black level − 3.6 − V
∆Vbl/∆T black level dependency with − 9 − mV/K
temperature
Signal on pin YCF
Vi(p-p) input voltage (peak-to-peak value) − 1.0 1.43 V
Ii input current − 4 − µA
Signal on pin CCF
Vi input voltage burst amplitude − 0.3 1.0 V
Zi input impedance − 50 − kΩ
Reference signal output (pin REFO); note 20
Vo(p-p) output signal amplitude CL = 15 pF 0.2 0.25 0.3 V
(peak-to-peak value)
VO(en) DC output level to enable 4.0 4.2 4.6 V
comb filter
VO(dis) DC output level to disable comb − 0.1 1.4 V
filter
Switching levels of SYS1 and SYS2 outputs (pins SYS1 and SYS2); note 21
VOH HIGH-level output voltage 4.0 5.0 5.5 V
VOL LOW-level output voltage − 0.1 0.4 V
Io(sink) output sink current 2 − − mA
Io(source) output source current 2 − − mA

2000 Sep 25 23
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DETECTION OF STATUS LEVELS OF SCART PLUG PIN 8; note 22
Vdet(int-ext) detection voltage between internal 2.0 2.2 2.4 V
and external (16 : 9) source
Vdet(ext-ext) detection voltage between external 5.3 5.5 5.7 V
(16 : 9) and external (4 : 3) source
Ri input resistance 60 100 − kΩ
Chrominance and luminance filters and delay lines
CHROMINANCE TRAP CIRCUIT; note 23
ftrap trap frequency fosc ±1% MHz
during SECAM reception 4.3 ±1.5% MHz
B−3dB −3 dB bandwidth fSC = 3.58 MHz 2.6 2.8 3.0 MHz
fSC = 4.43 MHz 3.2 3.4 3.6 MHz
during SECAM reception 2.9 3.1 3.3 MHz
CSR colour subcarrier rejection 26 − − dB
CHROMINANCE BAND-PASS CIRCUIT
fc centre frequency bit CB = 0 − fosc − MHz
bit CB = 1 − 1.1fosc − MHz
Qbp band-pass quality factor − 3 −
CLOCHE FILTER
fc centre frequency 4.26 4.29 4.31 MHz
B bandwidth 241 268 295 kHz
Y-DELAY LINE
td delay time bits YD3 to YD0 = 1011;
note 6
crystal A 490 520 550 ns
crystal B, C or D 530 560 590 ns
td(tr) tuning range delay time with respect to 520/560 ns; −280 − +160 ns
12 settings; see Table 13
B bandwidth note 6 8 − − MHz
GROUP DELAY CORRECTION (PINS GDI AND GDO); note 24
Vi(GDI)(p-p) input signal amplitude on pin GDI − 2.0 − V
(peak-to-peak value)
Ii(GDI) input current on pin GDI − 0.1 1.0 µA
Vo(GDO)(p-p) output signal amplitude on 1.8 2.0 2.2 V
pin GDO (peak-to-peak value)
Vo(GDO) output top-sync level on pin GDO − 2.4 − V
∆Vo(GDO)/∆T top-sync level on pin GDO − 5 − mV/K
variation with temperature
Zo(GDO) output impedance on pin GDO − − 250 Ω

2000 Sep 25 24
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Colour demodulation part
CHROMINANCE AMPLIFIER
CRACC ACC control range note 25 26 − − dB
∆Vo(CRACC) change in amplitude of the output − − 2 dB
signals over CRACC
THck(on) threshold colour killer ON colour killer from OFF to ON −40 − −35 dB
hysck(off) hysteresis colour killer OFF note 6
strong signal; S/N ≥ 40 dB − 3 − dB
noisy input signals − 1 − dB
ACL CIRCUIT; note 26
C/CACL ACL chrominance burst ratio when the ACL starts to − 3.0 −
operate
REFERENCE PART
Phase-locked loop; note 27
fcr catching range ±360 ±600 − Hz
∆ϕ phase shift for a ±400 Hz deviation of the − − 2 deg
oscillator frequency; note 6
Oscillator
TCfosc temperature coefficient of oscillator note 6 − − 1 Hz/K
frequency
∆fosc oscillator frequency variation with VP = 8 V ±10%; note 6 − − 25 Hz
respect to the supply voltage
Rneg(min) minimum negative resistance − − 1.0 kΩ
CL(max) maximum load capacitance − − 15 pF
HUE CONTROL; note 28
CRhue hue control range 63 steps; see Fig.4 ±35 ±40 − deg
∆hue/∆VP hue dependency with respect to VP ±10%; note 6 − 0 − deg
the supply voltage
∆hue/∆T hue dependency with temperature Tamb = 0 to 70 °C; note 6 − 0 − deg
DEMODULATORS
General
∆V/∆V spread of signal amplitude ratio note 6 −1 − +1 dB
between standards

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Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

PAL/NTSC demodulator
G(B-Y)(R-Y) gain between both demodulators 1.60 1.78 1.96
(B − Y) and (R − Y)
B−3dB(dem) −3 dB bandwidth of demodulators note 29 − 650 − kHz
∆Vo(rc)(p-p) residual carrier output f = fosc; (R − Y) output − − 5 mV
(peak-to-peak value) f = fosc; (B − Y) output − − 5 mV
f = 2fosc; (R − Y) output − − 5 mV
f = 2fosc; (B − Y) output − − 5 mV
RRH/2(p-p) H/2 ripple rejection (peak-to-peak at (R − Y) output − − 25 mV
value)
∆Vo/∆T output voltage variation with note 6 − 0.1 − %/K
temperature
∆Vo/∆VP output voltage variation with note 6 − − 0.3 dB/V
respect to the supply voltage
ϕe phase error in the demodulated note 6 − − ±5 deg
signals
SECAM demodulator
fblos black level offset frequency − − 7 kHz
∆fblos/∆T black level offset frequency − − 60 Hz/K
variation with temperature
fp pole frequency of de-emphasis 77 85 93 kHz
fp/fz ratio pole and zero frequency − 3 −
NL non-linearity − − 3 %
Vcal calibration voltage 3 4 5 V
Baseband delay line
∆Vo variation of output signal for adjacent time samples at −0.1 − 0.1 dB
constant input signals
∆Vr(clk)(p-p) residual clock signal (peak-to-peak − − 5 mV
value)
td delay delayed signal 63.94 64.0 64.06 µs
non-delayed signal 40 60 80 ns
∆Vo difference in output amplitude when delay line is bypassed − − 5 %
or not (with bit BPS)

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Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

PALplus helper demodulator
Vo(helper)(p-p) helper output voltage 610 686 770 mV
(peak-to-peak value)
Vsu(helper) helper set-up amplitude only helper lines 22 and 23 380 400 420 mV
td(g) group delay within pass band − − 10 ns
ϕe(dem) demodulation phase error including H/2 phase error − − 5 deg
αsup suppression for modulated helper in −36 − − dB
demodulated 0 to 1 MHz
signal
∆Vr residual signal at 4.43 MHz signal −36 − − dB
THD total harmonic distortion in ACC −36 − − dB
to(helper-Y) helper output timing to Y output − − 10 ns
Voffset offset voltage for demodulated mid grey to − − 5 mV
inserted mid grey level;
mid grey line 23 to line 22
tW(su)(helper) helper set-up pulse width − 52.8 − µs
td delay between mid sync of input bits YD3 to YD0 = 1011; − 8.6 − µs
and start of helper set-up note 30
delay between start of black set-up only lines 22 and 23 − 30.8 − µs
and start of helper set-up
Bhelper(−3dB) −3 dB bandwidth of helper − 2.6 − MHz
baseband
RGB switch and YUV switch
RGB SWITCH (PINS RI1 TO BI1 AND RI2 TO BI2)
Vi(p-p) input signal amplitude − 0.7 1.0 V
(peak-to-peak value)
Zsource(max) maximum source impedance − − 1.0 kΩ
∆Vbl(int-ext) difference between black level of − − 10 mV
internal and external signals at the
outputs
Ii input current no clamping; note 3 − 0.1 1 µA
∆td delay difference between the three note 6 − 0 20 ns
channels

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Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

YUV INPUTS (WHEN ACTIVATED)
Vi(Y)(p-p) Y input signal amplitude − 1.0 − V
(peak-to-peak value)
Vi(U)(p-p) U input signal amplitude − 1.33 − V
(peak-to-peak value)
Vi(V)(p-p) V input signal amplitude − 1.05 − V
(peak-to-peak value)
Zsource(max) maximum source impedance − − 1.0 kΩ
∆Vbl(int-ext) difference between black level of − − 10 mV
internal and external signals at the
outputs
Ii input current no clamping; note 3 − 0.1 1 µA
FAST BLANKING (PINS RGB1 AND RGB2)
Vi input voltage no data insertion − − 0.4 V
data insertion 0.9 − − V
Vi(max) maximum input pulse − − 3.5 V
Ii input current − − 0.2 mA
∆td(blank-RGB) delay difference between blanking note 6 − − tbf ns
and RGB signals
αsup(int) suppression of internal YUV data insertion; 55 − − dB
signals fi = 0 to 5 MHz; note 6
αsup(ext) suppression of external RGB no data insertion; 55 − − dB
signals fi = 0 to 5 MHz; note 6
td(blank-YUV) delay between blanking input and − − tbf ns
YUV outputs
LUMINANCE OUTPUT (PIN YO); note 31
Vo(p-p) output signal amplitude black-to-white − 1.0 − V
(peak-to-peak value)
Vo output voltage during PALplus black-to-white − 0.8 − V
∆Vbl(YUV-RGB) difference in black level between − − 10 mV
YUV and RGB mode
Zo output impedance − − 250 Ω
VO output DC voltage level black level 2.8 3.0 3.2 V
BRGB(−3dB) −3 dB bandwidth of the RGB 7 − − MHz
switch circuit
S/N signal-to-noise ratio fi = 0 to 5 MHz − 52 − dB
Vsu(bl) black set-up amplitude bit MACP = 1 or bit HD = 1 190 200 210 mV
tW(su)(bl) black set-up pulse width − 52.8 − µs
td delay between mid sync at input note 30 − 8.8 − µs
and black set-up
Voffset offset voltage Ybl to re-inserted black − − 10 mV

2000 Sep 25 28
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

G(Y/CVBS-YO) gain from internal Y/CVBS to YO 1.35 1.43 1.50
bit MACP = 1 or bit HD = 1 1.08 1.14 1.20
UO AND VO SIGNAL OUTPUTS (PINS UO AND VO)
Vo(VO)(p-p) output voltage on pin VO standard EBU colour bar 0.88 1.05 1.25 V
(peak-to-peak value)
Vo(UO)(p-p) output voltage on pin UO standard EBU colour bar 1.12 1.33 1.58 V
(peak-to-peak value)
Zo output impedance − − 250 Ω
VO output DC voltage level 2.2 2.4 2.6 V
∆Vbl(YUV-RGB) difference in black level between − − 10 mV
YUV and RGB mode
COLOUR MATRIX FROM RGB TO YUV
G gain
from RI to YO 0.40 0.43 0.46
from GI to YO 0.79 0.84 0.90
from BI to YO 0.15 0.16 0.17
from RI to UO 0.40 0.43 0.46
from GI to UO 0.79 0.84 0.90
from BI to UO 1.19 1.27 1.35
from RI to VO 0.94 1.00 1.07
from GI to VO 0.79 0.84 0.90
from BI to VO 0.15 0.16 0.17
Horizontal and vertical synchronization
SYNC VIDEO INPUTS
Vsync sync pulse amplitude note 3 35 300 350 mV
SLhor slicing level for horizontal sync note 32 50 55 60 %
SLvert slicing level for vertical sync note 32 35 40 45 %
HORIZONTAL OSCILLATOR
ffr free-running frequency − 15625 − Hz
∆ffr spread on free-running frequency − − ±2 %
∆f frequency dependency with VP = 8.0 V ±10%; note 6 − 0.2 0.5 %
respect to the supply voltage
∆fmax frequency variation with Tamb = 0 to 70 °C; note 6 − − 80 Hz
temperature
FIRST CONTROL LOOP (PIN PH1LF); note 33
fhr(PLL) PLL holding range − ±0.9 ±1.2 kHz
fcr(PLL) PLL catching range note 6 ±0.6 ±0.9 − kHz
S/N signal-to-noise ratio for the video input signal at 15 17 19 dB
which the time constant is
switched
hyssw hysteresis at the switching point 2 3 4 dB

2000 Sep 25 29
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

σϕ sigma value of phase jitter in automatic mode; ±3 σ − − 5 ns
HORIZONTAL PULSE OUTPUT AND CLAMP PULSE INPUT/OUTPUT (PIN HA/CLP)
Switched to HA output (bit HO = 1)
VOH HIGH-level output voltage Io(source) = 2 mA 4.0 5.0 5.5 V
VOL LOW-level output voltage Io(sink) = 2 mA − 0.2 0.4 V
Io(sink) output sink current 2 − − mA
Io(source) output source current 2 − − mA
tW pulse width at nominal horizontal 4.6 4.7 4.8 µs
frequency
td delay between mid sync of input note 30 0.3 0.45 0.6 µs
and mid HA pulse
Switched to CLP output (bit HO = 0)
tW pulse width at nominal horizontal 3.5 3.6 3.7 µs
frequency
td1 delay between start of CLP pulse bit HD = 1 or bit MACP = 1; 5.2 5.3 5.4 µs
to start of black set-up bits YD3 to YD0 = 1011; at
nominal horizontal frequency
td2 delay between mid sync of input note 30 3.0 3.2 3.4 µs
and start CLP pulse
Switched to CLP input (bit ECL = 1)
VIL LOW-level input voltage 0 − 0.6 V
VIH HIGH-level input voltage 2.4 − 5.5 V
tW(clamp) clamping pulse width 1.8 3.5 − µs
∆V(clamp)(n) clamping offset between pins UO − − 10 mV
and VO
Zi input impedance 3 − − MΩ
VERTICAL OSCILLATOR; note 34
ffr free-running frequency 50 Hz mode − 50 − Hz
60 Hz mode − 60 − Hz
flock frequency locking range 45 − 64.5 Hz
D/D divider ratio not locked − 625/525 − lines
LR locking range 488 − 722 lines/
frame
VERTICAL PULSE OUTPUT (PIN VA)
VOH HIGH-level output voltage Io(source) = 2 mA 4.0 5.0 5.5 V
VOL LOW-level output voltage Io(sink) = 2 mA − 0.2 0.4 V
Io(sink) output sink current 2 − − mA
Io(source) output source current 2 − − mA
tW pulse width fVA = 50 Hz − 2.5 − lines
fVA = 60 Hz − 3.0 − lines

2000 Sep 25 30
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

td delay between start of vertical sync note 35 − 37.7 − µs
of input and positive edge of
vertical pulse on pin VA
Zo output impedance bit ECL = 1 3 − − MΩ
SANDCASTLE OUTPUT (PIN SCO)
General
Vz zero level voltage 0 0.5 1.0 V
Io(sink) output sink current − 0.5 − mA
Horizontal/vertical blanking
Vo output voltage level 2.2 2.5 2.8 V
Io(source) output source current − 0.7 − mA
tW(h) horizontal blanking pulse width − 10 − µs
td delay between start horizontal − 6.4 − µs
blanking and start clamping pulse
Clamping pulse
Vo output voltage level 4.2 4.5 4.8 V
Io(source) output source current − 0.7 − mA
tW pulse width − 3.6 − µs
td delay between mid sync of input note 30 3.0 3.2 3.4 µs
and start of clamping pulse
I2C-bus control
SCL AND SDA INPUTS/OUTPUTS (PINS SCL AND SDA)
Vi input voltage range 0 − 5.5 V
VIL LOW-level input voltage − − 1.5 V
VIH HIGH-level input voltage 3.5 − − V
IIL LOW-level input current VIL = 0 V − − −10 µA
IIH HIGH-level input current VIH = 5.5 V − − 10 µA
VOL(SDA) LOW-level output voltage on IOL(SDA) = 3 mA − − 0.4 V
pin SDA
SW0 AND SW1 OUTPUTS (PINS SW0 AND SW1); note 36
VOH HIGH-level output voltage 4.0 5.0 5.5 V
VOL LOW-level output voltage − 0.2 0.4 V
IO(sink) output sink current 2 − − mA
IO(source) output source current 2 − − mA
Notes to the characteristics
1. The two supply pins VP1 and VP2 must be decoupled separately but they must be connected to a single power supply
to avoid too big differences between them.
2. On set AGC.
3. This parameter is not tested during production and is just given as application information for the designer of the
television receiver.

2000 Sep 25 31
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

4. Loop filter bandwidth Blpf = 60 kHz (natural frequency fn = 15 kHz; damping factor d = 2; calculated with top sync
level as fPLL input signal level). LC-VCO circuit between pins 7 and 8: Q0 = 60; Cint = 30 pF.
5. The optimum temperature stability of the PLL can be obtained when a TOKO coil as given in Table 55 is applied.
6. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
batches which are made in the pilot production period.
7. Measured at 10 mV (RMS) top sync input signal.
8. So called projected zero point, i.e. with switched demodulator.
9. Measured in accordance with the test line given in Fig.5. For the differential phase test the peak white setting is
reduced to 87%.
The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and
smallest value relative to the subcarrier amplitude at blanking level.
The differential phase is defined as the difference in degrees between the largest and smallest phase angle.
10. This figure is valid for the complete video signal amplitude (peak white-to-black). See Fig.6.
11. The noise inverter is only active in the ‘strong signal mode’ (no noise detected in the incoming signal).
12. The input conditions and test set-up are given in Figs 8 and 9. The figures are measured with an input signal of
10 mV (RMS).
13. Measured at an input signal of 10 mV (RMS). The S/N is the ratio of black-to-white amplitude with respect to the black
level noise voltage (RMS value). B = 5 MHz. Weighted in accordance with CCIR 567.
14. The AGC response time also depends on the acquisition time of the PLL demodulator. The values given are valid
when the PLL is in lock.
15. The AFC control voltage is obtained from the control voltage of the VCO of the PLL demodulator. The tuning
information is supplied to the tuning system via the I2C-bus. Two bits are reserved for this function. The AFC value
is valid only when bit PL = 1.
16. The weighted S/N ratio is measured under the following conditions:
a) The VIF modulator must meet the following specifications:
• Incidental phase modulation for black-to-white jumps less than 0.5 degrees.
• QSS AF performance, measured with the television-demodulator AMF2 (audio output, weighted S/N ratio)
better than 60 dB (deviation 27 kHz) for 6 kHz sine wave black-to-white modulation.
• Picture-to-sound carrier ratio: PC/SC1 = 13 dB (transmitter).
b) The measurements must be carried out with the Siemens SAW filters G3962 for VIF and G9350 for SIF.
Input level for SIF at 10 mV (RMS) with 27 kHz deviation.
c) The PC/SC ratio at the VIF input is calculated as the addition of the TV transmitter ratio and the SAW filter PC/SC
ratio. This PC/SC ratio is necessary to achieve the S/NW values as indicated.
17. Signal with negative-going sync. Amplitude includes sync pulse amplitude.
18. Indicated is a signal for a colour bar with 75% saturation (chrominance to burst amplitude ratio = 2.2 : 1).
19. When a signal is identified which can be combed (correct combination of colour standard and reference crystal) the
comb filter is switched to that mode via pins 25 and 27 and then the filter is activated by switching on the reference
carrier signal and connecting the output signals of the comb filter (pins 28 and 29) to the video processing circuits.
20. The subcarrier output signal can be used as a reference signal for external comb filter ICs (e.g. SAA4961). When
bit ECMB = 0 the subcarrier signal is suppressed and the DC level is LOW. When bit ECMB = 1 the output level is
HIGH and the subcarrier signal is present.
21. The outputs SYS1 and SYS2 can be used to switch the comb filter to the different colour standards (e.g. PAL-M,
PAL-N, PAL-B/G and NTSC-M) and are controlled by the colour decoder identification circuit.
The setting of the outputs for the various standards is given in Table 56.

2000 Sep 25 32
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

22. For the detection of the status of the incoming SCART signal a voltage divider with a ratio of 2 : 3 has to be connected
between pin 8 of the SCART plug and the detection input. The impedance of the voltage divider should not be too
high-ohmic because of the input impedance of 100 kΩ.
23. When the decoder is forced to a fixed subcarrier frequency (via bits XA to XD or bit CM) the chrominance trap is
always switched on, also when no colour signal is identified. When 2 crystals are active the chrominance trap is
switched off if no colour signal is identified.
24. The typical group delay characteristic for the B/G standard is given in Fig.7.
25. At a chrominance input voltage of 660 mV (p-p) [colour bar with 75% saturation i.e. burst signal amplitude
300 mV (p-p)] the dynamic range of the ACC is +6 and −20 dB.
26. The ACL function can be activated by bit ACL. The ACL circuit reduces the gain of the chrominance amplifier for input
signals with a C/CACL which exceeds a value of 3.0.
27. All frequency variations are referenced to 3.58 or 4.43 MHz carrier frequency. All oscillator specifications are
measured with the Philips crystal series 9922 520 with a series capacitance Cs = 18 pF. The oscillator circuit is rather
insensitive to the spurious responses of the crystal. As long as the resonance resistance of the third overtone is
higher than that of the fundamental frequency the oscillator will operate at the correct frequency. The typical crystal
parameters for the crystal series are:
a) Load resonance frequencies fL: 4.433619, 3.579545, 3.582056 and 3.575611 MHz; Cs = 20 pF.
b) Motional capacitance Cmot = 20.6 fF (4.43 MHz crystal) or Cmot = 14.7 fF (3.58 MHz crystal).
c) Parallel capacitance Cp = 5.0 pF.
The minimum detuning range can only be specified if both the IC and the crystal tolerances are known and therefore
the figures regarding catching range are only valid for the specified crystal series. In this figure tolerances of the
crystal with respect to the nominal frequency, motional capacitance and ageing have been taken into account and
have been counted for gaussic addition. Whenever different typical crystal parameters are used the following
equation might be helpful for calculating the impact on the tuning capabilities:
C mot
Detuning range = ------------------------2-
1 + C -------
p
 Cs

The resulting detuning range should be corrected for temperature shift and supply voltage deviation of both the IC
and the crystal. To guarantee a catching range of ±300 Hz on 4.43 MHz the minimum motional capacitance of the
crystal must have a value 13.2 fF or higher. For a catching range of 250 Hz with the 3.58 MHz crystal the minimum
motional capacitance must have a value of 9 fF.
Note: SMD-type crystals do not fulfil these requirements.
The actual series capacitance in the application should be Cs = 18 pF to account for parasitic capacitances on-chip
and off-chip.
28. The hue control is active for NTSC on the demodulated colour difference signals and for PALplus on the demodulated
helper signal.
29. This parameter indicates the bandwidth of the complete chrominance circuit including the chrominance band-pass
filter. The bandwidth of the low-pass filter of the demodulator is approximately 1 MHz.
30. This delay is partially caused by the low-pass filter at the sync separator input.
31. The internal luminance signal (signal which is derived from the incoming CVBS or Y/C signals) has a separate gain
control setting (controlled by the I2C-bus bits GAI1 and GAI0 and with a gain variation between −1 and +2 dB) which
can be used to get an optimal input signal amplitude for the feature box.
32. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing
level and the black level (back porch). When the amplitude of the sync pulse exceeds the value of 350 mV the sync
separator will slice the sync pulse at a level of 175 mV above top sync. The maximum sync pulse amplitude is 4 V
(peak-to-peak value).

2000 Sep 25 33
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

33. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is
switched depending on the input signal condition and the condition of the I2C-bus. Therefore the circuit contains a
noise detector and the time constant is switched to the slow mode when too much noise is present in the signal. In the
fast mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to
head-switching of the VCR are corrected as soon as possible. Switching between the two modes can be automatic
or overruled by the I2C-bus.
The circuit contains a video identification circuit which is independent of the first control loop. This identification circuit
can be used to close or open the first control loop when a video signal is present or not present on the input. This
enables a stable On Screen Display (OSD) when just noise is present at the input. The coupling of the video
identification circuit with the first control loop can be revoked via the I2C-bus.
To prevent the horizontal synchronization being disturbed by anti copy signals such as Macrovision the phase
detector is gated during the vertical retrace period from line 11 to 17 (60 Hz signal) or from line 11 to 22 (50 Hz
signal) so that pulses during scan have no effect on the output voltage. The width of the gate pulse is approximately
22 µs. During weak signal conditions (noise detector active) the gating is active during the complete scan period and
the width of the gate pulse is reduced to 5.7 µs so that the effect of noise is reduced to a minimum.
The output current of the phase detector in the various conditions is shown in Table 57.
34. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit.
This divider circuit has 3 modes of operation:
a) Search mode large window.
This mode is switched on when the circuit is not synchronized or when a non-standard signal [number of lines
per frame outside the range between 311 and 314 (50 Hz mode) or between 261 and 264 (60 Hz mode)] is
received. In the search mode the divider can be triggered between line 244 and line 361 (approximately
43.3 to 64.5 Hz).
b) Standard mode narrow window.
This mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window.
When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp
generator is started at the end of the window. Consequently, the disturbance of the picture is very small.
The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are
found within the window.
c) Standard TV-norm [divider ratio 525 (60 Hz) or 625 (50 Hz)].
When the system is switched to the narrow window a check is performed to establish whether the incoming
vertical sync pulses are in accordance with the TV-norm. When 15 standard TV-norm pulses are counted the
divider system is switched to the standard divider ratio mode. In this mode the divider is always reset at the
standard value even if the vertical sync pulse is missing.
When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this
window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window.
The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of the
divider is required during channel-switching the system can be forced to the search window by means of bit NCIN in
subaddress 06.
35. The delay between the positive edge of VA and the positive edge of CLP (≈ negative edge of HA) after VA is 32.0 µs
for field 1 and 0 µs for field 2. Especially for PALplus signals the regenerated VA pulses must have a fixed and known
phase relation to the undisturbed VA pulses of the incoming video signal. This relationship must remain correct as
long as the vertical divider is in the standard mode (indirect sync mode). Therefore the coincidence window used
here must be a half line window. With a well defined phase relationship of the generated VA pulses to the generated
HA pulses a correct field identification and all the required timing signals referring to a certain line in each frame can
be generated externally in the PALplus decoder environment.
36. Pins 19 and 22 are for general purpose outputs that can be used to switch external circuits e.g. sound traps, etc.
They are controlled via the I2C-bus by bits OS0 (pin 19) and OS1 (pin 22).

2000 Sep 25 34
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

Table 55 Coil data for the VIF-PLL demodulator (approximated coil values)
fVIF fVCO L
TOKO SAMPLE NUMBER REMARKS
(MHz) (MHz) (nH)
38.9 77.8 150 P369INAS-159HM ∅ 5 mm; 5 km long; TC = 30 ±100 ppm/°C
45.75 91.5 100 P369INAS-160HM
58.75 117.5 70 P369INAS-161HM

Table 56 Switching conditions of pins SYS1 and SYS2

COLOUR STANDARD SYS1 SYS2 ACTIVE CRYSTAL
PAL-M LOW LOW C
PAL-B, G, H, D and I LOW HIGH A
NTSC-M HIGH LOW D
PAL-N HIGH HIGH B

Table 57 Output current of the phase detector in the various conditions

I2C-BUS COMMANDS IC CONDITIONS ϕ-1 CURRENT/MODE
VID POC FOA FOB IDENT COIN NOISE SCAN V-RETR GATING MODE
− 0 0 0 yes yes no 180 270 yes(1) auto
− 0 0 0 yes yes yes 30 30 yes auto
− 0 0 0 yes no − 180 270 no auto
− 0 0 1 yes yes − 30 30 yes slow
− 0 0 1 yes no − 180 270 no slow
− 0 1 0 yes yes no 180 270 yes fast
− 0 1 0 yes yes yes 30 30 yes slow
− − 1 1 − − − 180 270 yes(1) fast
0 0 − − no − − 6 6 no OSD
− 1 − − − − − − − − off

Note
1. Only during vertical retrace, pulse width 22 µs and provided that bit EMG = 1 and IVW readout bit = 1. In the other
FOA FOB conditions with gating, the pulse width is 5.7 µs and the gating is continuous.

2000 Sep 25 35
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

MLA739
handbook, full pagewidth
50

(deg)

30

10

10

30

50
0 10 20 30 40
DAC (HEX)

Fig.4 Hue control curve.

MBC212

100%
16 % 92%

30%

for negative modulation

100% = 10% rest carrier

Fig.5 Video output signal.

2000 Sep 25 36
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

handbook, full pagewidth MBC211

100
(%)
86

72

58

44

30

10 12 22 26 32 36 40 44 48 52 56 60 64
time (µs)

Fig.6 Test signal waveform.

MGR476
500
handbook, halfpage
td(g)
(ns)
400

300

200

100

0
0 1 2 3 4 5
f (MHz)

Fig.7 Group delay characteristic.

2000 Sep 25 37
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

handbook, full pagewidth −3.2 dB

−10 dB
−13.2 dB −13.2 dB

−30 dB −30 dB

SC CC PC SC CC PC
MBC213
BLUE YELLOW

SC = sound carrier, with respect to top sync level.

CC = colour carrier, with respect to top sync level.
PC = picture carrier, with respect to top sync level.
V O at 3.58 or 4.4 MHz
Value at 0.92 or 1.1 MHz = 20 log ------------------------------------------------------------ + 3.6 dB
V O at 0.92 or 1.1 MHz

V O at 3.58 or 4.4 MHz

Value at 2.66 or 3.3 MHz = 20 log ------------------------------------------------------------
V O at 2.66 or 3.3 MHz

Fig.8 Input signal conditions.

PC
38.9 MHz

SC TEST SPECTRUM
33.4 MHz Σ ATTENUATOR CIRCUIT ANALYZER

gain setting adjusted

CC for blue or yellow
34.5 MHz
MBC210

Fig.9 Test set-up intermodulation.

2000 Sep 25 38
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

TEST AND APPLICATION INFORMATION

handbook, full pagewidth RGB1 RGB2

RI1 GI1 BI1 RI2 GI2 BI2 RI1 GI1 BI1 BL1 RI2 GI2 BI2 BL2
TAGC

62 36 37 38 39 40 41 42 43 30 31 32 33 35 36 37 38
VIF1 2 YO YIN
49 28 40 RO
IF SAW
FILTER VIF2 3 50
UO UIN
27 41 GO
VO VIN
51 26 42 BO
CVBS1 16
AV1 15 43 BCL
CVBS2 18 FEATURE
TDA9321H TDA9330H 44 BLKIN
BOX
AV2 17
1 VDOA
CVBS/Y3 20 HA HD 2 VDOB
60 24
C3 21 3 EWO
VA VD
61 23
CVBS/Y4 23 8 HOUT
C4 24 13
34 32 26 28 29 HFB

MGR477
CVBSCF YCF CCF
CVBSTXT
COMB FILTER
CVBSPIP

Fig.10 Application diagram.

2000 Sep 25 39
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

PACKAGE OUTLINE
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT319-2

c
y
X

51 33 A
52 32 ZE

e
A2
E HE A
A1 (A 3)

θ
wM
pin 1 index Lp
bp L

64 20 detail X
1 19

w M ZD v M A
e bp

D B
HD v M B

0 5 10 mm
scale

DIMENSIONS (mm are the original dimensions)

A
UNIT max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y Z D (1) Z E (1) θ
o
0.25 2.90 0.50 0.25 20.1 14.1 24.2 18.2 1.0 1.2 1.2 7
mm 3.20 0.25 1 1.95 0.2 0.2 0.1
0.05 2.65 0.35 0.14 19.9 13.9 23.6 17.6 0.6 0.8 0.8 0o

Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION

97-08-01
SOT319-2 MO-112
99-12-27

2000 Sep 25 40
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

SOLDERING If wave soldering is used the following conditions must be

observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
This text gives a very brief insight to a complex technology. turbulent wave with high upward pressure followed by a
A more in-depth account of soldering ICs can be found in smooth laminar wave.
our “Data Handbook IC26; Integrated Circuit Packages”
• For packages with leads on two sides and a pitch (e):
(document order number 9398 652 90011).
– larger than or equal to 1.27 mm, the footprint
There is no soldering method that is ideal for all surface longitudinal axis is preferred to be parallel to the
mount IC packages. Wave soldering is not always suitable
transport direction of the printed-circuit board;
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow – smaller than 1.27 mm, the footprint longitudinal axis
soldering is often used. must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied • For packages with leads on four sides, the footprint must
to the printed-circuit board by screen printing, stencilling or be placed at a 45° angle to the transport direction of the
pressure-syringe dispensing before package placement. printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven. During placement and before soldering, the package must
Throughput times (preheating, soldering and cooling) vary be fixed with a droplet of adhesive. The adhesive can be
between 100 and 200 seconds depending on heating applied by screen printing, pin transfer or syringe
method. dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the Typical dwell time is 4 seconds at 250 °C.
packages should preferable be kept below 230 °C. A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards Fix the component by first soldering two
with a high component density, as solder bridging and diagonally-opposite end leads. Use a low voltage (24 V or
non-wetting can present major problems. less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
To overcome these problems the double-wave soldering 300 °C.
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

2000 Sep 25 41
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

Suitability of surface mount IC packages for wave and reflow soldering methods

SOLDERING METHOD
PACKAGE
WAVE REFLOW(1)
HLQFP, HSQFP, HSOP, SMS not suitable(2) suitable
PLCC(3), SO suitable suitable
LQFP, QFP, TQFP not recommended(3)(4) suitable
SQFP not suitable suitable
SSOP, TSSOP, VSO not recommended(5) suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

2000 Sep 25 42
Philips Semiconductors Preliminary specification

I2C-bus controlled TV input processor TDA9321H

DATA SHEET STATUS

PRODUCT
DATA SHEET STATUS DEFINITIONS (1)
STATUS
Objective specification Development This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification Production This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

Note
1. Please consult the most recently issued data sheet before initiating or completing a design.

DEFINITIONS DISCLAIMERS
Short-form specification  The data in a short-form Life support applications  These products are not
specification is extracted from a full data sheet with the designed for use in life support appliances, devices, or
same type number and title. For detailed information see systems where malfunction of these products can
the relevant data sheet or data handbook. reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
Limiting values definition  Limiting values given are in
for use in such applications do so at their own risk and
accordance with the Absolute Maximum Rating System
agree to fully indemnify Philips Semiconductors for any
(IEC 60134). Stress above one or more of the limiting
damages resulting from such application.
values may cause permanent damage to the device.
These are stress ratings only and operation of the device Right to make changes  Philips Semiconductors
at these or at any other conditions above those given in the reserves the right to make changes, without notice, in the
Characteristics sections of the specification is not implied. products, including circuits, standard cells, and/or
Exposure to limiting values for extended periods may software, described or contained herein in order to
affect device reliability. improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
Application information  Applications that are
the use of any of these products, conveys no licence or title
described herein for any of these products are for
under any patent, copyright, or mask work right to these
illustrative purposes only. Philips Semiconductors make
products, and makes no representations or warranties that
no representation or warranty that such applications will be
these products are free from patent, copyright, or mask
suitable for the specified use without further testing or
work right infringement, unless otherwise specified.
modification.

PURCHASE OF PHILIPS I2C COMPONENTS

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2000 Sep 25 43
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The Netherlands, Fax. +31 40 27 24825

© Philips Electronics N.V. 2000 SCA 70

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.

Printed in The Netherlands 753504/02/pp44 Date of release: 2000 Sep 25 Document order number: 9397 750 07032