MUTHAYAMMAL ENGINEERING COLLEGE

(An Autonomous Institution)

(Approved by AICTE, New Delhi, Accredited by NAAC & Affiliated to Anna University)

Rasipuram - 637 408, Namakkal Dist., Tamil Nadu.

Department of Electronics and Communication Engineering

23EVC24 CMOS VLSI DESIGN LABORATORY

LAB OBSERVATION

Prepared by,
1. Ms.Venkateshwari , AP/ECE
 Syllabus

1. Plot the (i) output characteristics & (ii) transfer characteristics of an n-channel and p-
channel MOSFET

2. Design and plot the static (VTC) and dynamic characteristics of a digital CMOS
inverter

3. Design and plot the output characteristics of a 3-inverter ring oscillator

4. Design and plot the dynamic characteristics of 2-input NAND, NOR, XOR and XNOR
logic gate using CMOS technology

5. Design and plot the characteristics of a Pass Transistor Logic

6. Design and plot the characteristics of a Transmission Gate

7. Design and plot the characteristics of a 4x1 digital multiplexer using pass transistor
logic

8. Design and plot the characteristics of a positive and negative latch based on
multiplexers

9. Design and plot the characteristics of a master-slave positive and negative edge triggered
registers based on multiplexers

10. Draw the layout of an n-channel and p-channel MOSFET and perform the DRC, LVS
and RC extraction
 TABLE OF CONTENTS

Exp. Date Name of the experiment Marks Signature of

No the staff
DIAGRAM

Fig. 4: Channel pinchoff for (a) nMOS and (b) pMOS transistor devices.

SYMBOL

Fig. (2): Circuit symbols for nMOS and pMOS respectively

Ex. No:1 PLOT THE (I) OUTPUT CHARACTERISTICS & (II) TRANSFER
DATE: CHARACTERSTICS OF n-CHANNEL AND p-CHANNEL
MOSFET

AIM :
To Plot the (i) output characteristics & (ii) transfer characteristics of an n-channel and p-
channel MOSFET.

THEORY:
The metal–oxide–semiconductor field-effect transistor (MOSFET) is a transistor used for
amplifying or switching electronic signals. In MOSFETs, a voltage on the oxide-insulated gate
electrode can induce a conducting channel between the two other contacts called source and
drain. The channel can be of n-type or p-type, and is accordingly called an nMOSFET or a
pMOSFET. Figure 1 shows the schematic diagram of the structure of an nMOS device before
and after channel formation.
Figure 2 shows symbols commonly used for MOSFETs where the bulk terminal is either labeled
(B) or implied (not drawn).
The characteristics of an nMOS transistor can be explained as follows. As the voltage on
the top electrode increases further, electrons are attracted to the surface. At a particular voltage
level, which we will shortly define as the threshold voltage, the electron density at the surface
exceeds the hole density. At this voltage, the surface has inverted from the p-type polarity of the
original substrate to an n-type inversion layer, or inversion region, directly underneath the top
plate as indicated in Fig. 1(b). This inversion region is an extremely shallow layer, existing as a
charge sheet directly below the gate. In the MOS capacitor, the high density of electrons in the
inversion layer is supplied by the electron–hole generation process within the depletion layer.
The positive charge on the gate is balanced by the combination of negative charge in the inversion
layer plus negative ionic acceptor charge in the depletion layer. The voltage at which the surface
inversion layer just forms plays an extremely important role in field-effect transistors and is called
the threshold voltage Vtn. The region of output characteristics where VGStn and no current flows
is called the cutt-off region. When the channel forms in the nMOS (pMOS) transistor, a positive
(negative) drain voltage with respect to the source creates a horizontal electric field moving the
electrons (holes) toward the drain forming a positive (negative) drain current coming into the
transistor. The positive current convention is used for electron and hole current, but in both cases
electrons are the actual charge carriers. If the channel horizontal electric field is of the same order
or smaller than the vertical thin oxide field, then the inversion channel remains almost uniform
along the device length. This continuous carrier profile from drain to source puts the transistor in
a bias state that is equivalently called
OUTPUT CHARACTERISTICS :

TRANSFER CHARACTERISTICS :
 either the non-saturated, linear, or ohmic bias state. The drain and source are effectively
short-circuited. This happens when VGS > VDS + Vtn for nMOS transistor and VGS < VDS
+Vtp for pMOS transistor. Drain current is linearly related to drain-source voltage over small
intervals in the linear bias state.
But if the nMOS drain voltage increases beyond the limit, so that VGS < VDS + Vtn, then
the horizontal electric field becomes stronger than the vertical field at the drain end, creating an
asymmetry of the channel carrier inversion distribution shown in Figure 4.
If the drain voltage riseswhile the gate voltage remains the same, then VGD can go below
the threshold voltage in the drain region. There can be no carrier inversion at the drain-gate oxide
region, so the inverted portion of the channel retracts from the drain, and no longer “touches” this
terminal. The pinched-off portion of the channel forms a depletion region with a high electric
field. The n-drain and p-bulk form a pn junction.When this happens the inversion channel is said
to be “pinched-off” and the device is in the saturation region. The characteristics can be loosely
modelled by the following equations.

Transfer Characteristics
The transfer characteristic relates drain current (ID) response to the input gate-source driving voltage (VGS).
Since the gate terminal is electrically isolated from the remaining terminals (drain, source, and bulk), the gate
current is essentially zero, so that gate current is not part of device characteristics. The transfer characteristic
curve can locate the gate voltage at which the transistor passes current and leaves the OFF-state. This is the device
threshold voltage (Vtn). Figure 5 shows measured input characteristics for an nMOS and pMOS transistor with a
small 0.1V potential across their drain to source terminals.
The transistors are in their non-saturated bias states. As VGS increases for the nMOS transistor in Figure 5a, the
threshold voltage is reached where drain current elevates. For VGS between 0V and 0.7V, ID is nearly zero
indicating that the equivalent resistance between the drain and source terminals is extremely high. Once VGS
reaches 0.7V, the current increases rapidly with VGS indicating that the equivalent resistance at the drain
decreases with increasing gate-source voltage. Therefore, the threshold voltage of the given nMOS transistor is
about Vtn ≈ 0.7V. The pMOS transistor input characteristic in Figure 5b is analogous to the
nMOS transistor except the ID and VGS polarities are reversed.

RESULT:
Thus the (i) output characteristics & (ii) transfer characteristics of an n-channel and p-
channel MOSFET successfully plot
CIRCUIT DIAGRAM :
EX. NO : 2 DESIGN AND PLOT THE STATIC (VTC) AND DYNAMIC
DATE : CHARACTERISTICS OF A DIGITAL CMOS INVERTER

AIM:
To design and plot the static (VTC) and dynamic characteristics of a digital CMOS
inverter

SOFTWARE USED:
Mentor graphics

THEORY :

CMOS INVERTER
The NMOS transistor and the PMOS transistor form a typical complementary MOS
(CMOS) device. When a low voltage (0 V) is applied at the input, the top transistor (P-type) is
conducting (switch closed) while the bottom transistor behaves like an open circuit. Therefore,
the supply voltage (5 V) appears at the output. Conversely, when a high voltage (5 V) is applied
at the input, the bottom transistor (N-type) is conducting (switch closed) while the top transistor
behaves like an open circuit. Hence, the output voltage is low (0 V).

PROCEDURE:
Step 1: Go to file→new→new library→select TINCY DOC→Tannel EDA→new
folder→ok250nm. click ok
Step 2: Select file name →Add library→library folder→DOC→Tanner
EDA→Tools→process→Generic device
Step 3: Same procedure to step 2 to follow up to select→Standard
→Misc→spice→plot→spice source.
Step 4: Go to cell view →new view→library”file name”and give as cell name →”CMOS
Inverter” & select a view type schematic and click on ok button.
Step 5: Select on generic 250nm devices and also select on nmos25 and pmos25
Step 6: Schematic will create and should draw on CMOS inverter and give connections.
Step 7: Click on MISC and select on GND component and Vdd components.
Step 8: Adding the ports and connecting the devices and save as schematic.
OUTPUT WAVEFORM :
 Step 9: Adding a DC voltage source & C-V source from the library and change the value
of the DC property to be 3.3V Add pulse voltage source pulse -V- source & change the property
to be 3.3V & change the delay to be OS
Step 10: Simulating the Schematic
✔ select on menu bar and select run simulation .
✔ Click ok now design context window are open and need to setup the analysis type, plots
and load in the Eldo models.
✔ In the design context from menuber select simulation →setup simulation or click on
setup simulation in the left icon plalalte.
Step 11: A set up simulation window will pop up is shown .Here I have selected the
transient analysis with the start time as ons,stop time= loons and print time step=5ns. After
specifying the values click on apply.
Step 12: To probe the waveform click on the o/p in the selection panel,then select the
input port of the schematic window as shown.
Step 13: In the setup simulation window ,click add button then the port will be added to
the wave form as shown.
Step 14: To view the simulation result by selecting the plot result from latest run icon
from the left icon palatts .This will open E2 wave for you with the o/p waveforms.

RESULT:
Thus the design and implementation of CMOS inverter is verified successfully.
CIRCUIT DIAGRAM :

OUTPUT CHARACTERISTICS :
EX. NO : 3 DESIGN AND PLOT THE OUTPUT CHARACTERISTICS

DATE : OF 3 – INVERTER RING OSCILLATOR

AIM :

To design and plot the output characteristics of 3 – inverter ring oscillator using mentor
graphics.

SOFTWARE REQUIRED :

Mentor Graphics

THEORY :

The NOT gates, or inverters, are attached in a chain; the output of the last inverter is fed
back into the first. Because a single inverter computes the logical NOT of its input, it can be
shown that the last output of a chain of an odd number of inverters is the logical NOT of the first
input. This final output is asserted a finite amount of time after the first input is asserted; the
feedback of this last output to the input causes oscillation. A real ring oscillator only requires
power to operate; above a certain threshold voltage, oscillations begin spontaneously. To increase
the frequency of oscillation, two methods may be used. Firstly, the applied voltage may be
increased; this increases both the frequency of the oscillation and the power consumed, which is
dissipated as heat.
PROCEDURE :
Step 1: Go to file→new→new library→select TINCY DOC→Tannel EDA→new
folder→ok250nm. click ok
Step 2:Select file name →Add library→library folder→DOC→Tannel
EDA→Tools→process→Generic device
Step 3:Same procedure to step 2 to follow up to select→Standard
→Misc→spice→plot→spice source.
Step 4:Go to cell view →new view→library”file name”and give as cell name →”3
Inverter Ring Oscillator” & select a view type schematic and click on ok button.
 Step 5: Select on generic 250nm devices and also select on nmos25 and pmos25
Step 6: Schematic will create and should draw on 3 – inverter ring oscillator and give
connections.
Step 7: Click on MISC and select on GND component and Vdd components.
Step 8: Adding the ports and connecting the devices and save as schematic.
Step 9: Adding a DC voltage source & C-V source from the library and change the value
of the DC property to be 3.3V Add pulse voltage source pulse -V- source & change the
property to be 3.3V & change the delay to be OS
Step 10: Simulating the Schematic
✔ select on menu bar and select run simulation .
✔ Click ok now design context window are open and need to setup the analysis type, plots
and load in the Eldo models.
✔ In the design context from menuber select simulation →setup simulation or click on
setup simulation in the left icon plalalte.
Step 11: A set up simulation window will pop up is shown .Here I have selected the
transient analysis with the start time as ons,stop time= loons and print time step=5ns. After
specifying the values click on apply.
Step 12: To probe the waveform click on the o/p in the selection panel,then select the
input port of the schematic window as shown.
Step 13: In the setup simulation window ,click add button then the port will be added to
the wave form as shown.
Step 14: To view the simulation result by selecting the plot result from latest run icon
from the left icon palatts .This will open E2 wave for you with the o/p waveforms.

RESULT :
Thus the 3 – inverter ring oscillator was designed and its output characteristics was plotted
successfully.
CIRCUIT DIAGRAM OF 2 INPUT NAND GATE :

CIRCUIT DIAGRAM OF 2 INPUT NOR GATE :

EX. NO : 4 DESIGN AND PLOT THE DYNAMIC CHARACTERISTICS
DATE : OF 2-INPUT NAND, NOR, XOR AND XNOR LOGIC GATE
USING CMOS TECHNOLOGY

AIM :
To Design and plot the dynamic characteristics of 2-input NAND, NOR, XOR and
XNOR logic gate using CMOS technology .

SOFTWARE REQUIRED :
Mentor Graphics

THEORY :
In order to design 2-input NAND, NOR, XOR and XNOR gates for equal rise and fall
time, it is necessary to first design an inverter with equal rise and fall time. This involves
compensating for the difference in electron and hole mobilities. For silicon material, the electron
mobility is about 2.5 to 3 times greater than the hole mobility. Therefore, to have equal rise tand
fall time in an inverter, we must choose the W/L ration of pMOS as 2.5 times greater than that of
the nMOS transistor. After performing this task, we need to size the transistors of each gate under
worst case conditions (of input combination) for charging and discharging resistances R c and Rd.
(In every gate circuit, the PUN provides maximum ON resistance for rise time and the PDN
provides maximum ON resistance for fall time.) For a NAND gate, the worst case charging
corresponds to an input combination where only one of the pMOS is ON and discharging takes
place only when both nMOS’ are turned ON. i.e. in the worst case, R c/Rd=1/2. Thus, in order to
equalize both currents (considering also the mobility defferences), we must have
(W/L)p=(2.5*2)(W/L)n. This can be achieved in a 180nm technology by choosing Wn=0.18 µm
and Wp=0.90 µm. Similary in case of a NOR gate, (W/L)p must be equal to (2.5*0.5)(W/L)n
which can be achieved by taking Wn=0.36µm and Wp=0.45µm. For XOR and XNOR gates, worst
case Rc/Rd ratio is equal to one. Therefore, (W/L)p must be equal to (2.5*1)(W/L)n for both gates.
CIRCUIT DIAGRAM OF 2 INPUT XOR GATE :

CIRCUIT DIAGRAM OF 2 INPUT NAND GATE :

PROCEDURE :

Step 1: Go to file→new→new library→select TINCY DOC→Tannel EDA→new

folder→ok250nm. click ok
Step 2: Select file name →Add library→library folder→DOC→Tannel
EDA→Tools→process→Generic device
Step 3: Same procedure to step 2 to follow up to select→Standard
→Misc→spice→plot→spice source.
Step 4: Go to cell view →new view→library”file name”and give as cell name →”2 input
NAND, NOR, XOR, XNOR” & select a view type schematic and click on ok button.
Step 5: Select on generic 250nm devices and also select on nmos25 and pmos25
Step 6: Schematic will create and should draw on 2 input NAND, NOR, XOR, XNOR
and give connections.
Step 7: Click on MISC and select on GND component and Vdd components.
Step 8: Adding the ports and connecting the devices and save as schematic.
Step 9: Adding a DC voltage source & C-V source from the library and change the value
of the DC property to be 3.3V Add pulse voltage source pulse -V- source & change the property
to be 3.3V & change the delay to be OS
Step 10: Simulating the Schematic
✔ select on menu bar and select run simulation .
✔ Click ok now design context window are open and need to setup the analysis type, plots
and load in the Eldo models.
✔ In the design context from menuber select simulation →setup simulation or click on
setup simulation in the left icon plalalte.
Step 11: A set up simulation window will pop up is shown .Here I have selected the
transient analysis with the start time as ons,stop time= loons and print time step=5ns. After
specifying the values click on apply.
Step 12: To probe the waveform click on the o/p in the selection panel,then select the
input port of the schematic window as shown.
Step 13: In the setup simulation window ,click add button then the port will be added to
the wave form as shown.
OUTPUT WAVEFORM : (2 Input NOR Gate)

OUTPUT WAVEFORM : (2 Input XOR Gate)

 Step 14: To view the simulation result by selecting the plot result from latest run icon
from the left icon palatts .This will open E2 wave for you with the o/p waveforms.
OUTPUT WAVEFORM : (2 Input XNOR Gate)
RESULT :
Thus the 2-input NAND, NOR, XOR and XNOR logic gate using CMOS technology was
designed and its dynamic characteristics was plotted successfully.
CIRCUIT DIAGRAM :

TRUTH TABLE :
EX. NO : 5 DESIGN AND PLOT THE CHARACTERISTICS OF A PASS
DATE : TRANSISTOR LOGIC

AIM :
To design and plot the characteristics of a pass transistor logic.

SOFTWARE REQUIRED :
Mentor Graphics

THEORY :

The Pass transistor logic is required to reduce the transistors for implementing logic by
using the primary inputs to drive gate terminals, source and drain terminals. In complementary
CMOS logic primary inputs are allowed to drive only gate terminals.

For Example the implementation of AND function using only NMOS pass transistors. In
this gate if the B input is high the left NMOS is turned ON and copies the input A to the output
F. When B is low the right NMOS pass transistor is turned ON and passes a '0' to the output F.
This satisfies the truth table of AND gate reproduced in Table below for verification.

The major advantage of pass transistor logic is that fewer transistors are required to
implement a given function. To illustrate this consider the implementation of AND gate using
complementary CMOS logic. If we compare this with the same AND gate implementation using
pass transistor logic the number of transistors required are four including the two transistor
required to invert the input B. The another advantage of pass transistor logic is the lower
capacitance because of reduced number of transistors. As discussed NMOS devices are effective
in passing strong '0' but it is poor at pulling a node to VDD. Hence when the pass transistor pulls
a node to high logic the output only changes upto VDD–VTh. This is the major disadvantage of
pass transistors.
PROCEDURE :

Step 1: Go to file→new→new library→select TINCY DOC→Tannel EDA→new

folder→ok250nm. click ok
Step 2: Select file name →Add library→library folder→DOC→Tannel
EDA→Tools→process→Generic device
Step 3: Same procedure to step 2 to follow up to select→Standard
→Misc→spice→plot→spice source.
Step 4: Go to cell view →new view→library”file name”and give as cell name →”Pass
Transistor” & select a view type schematic and click on ok button.
Step 5: Select on generic 250nm devices and also select on nmos25 and pmos25
Step 6: Schematic will create and should draw on pass transistor logic and give
connections.
Step 7: Click on MISC and select on GND component and Vdd components.
Step 8: Adding the ports and connecting the devices and save as schematic.
Step 9: Adding a DC voltage source & C-V source from the library and change the value
of the DC property to be 3.3V Add pulse voltage source pulse -V- source & change the property
to be 3.3V & change the delay to be OS
Step 10: Simulating the Schematic
✔ select on menu bar and select run simulation .
✔ Click ok now design context window are open and need to setup the analysis type, plots
and load in the Eldo models.
✔ In the design context from menuber select simulation →setup simulation or click on
setup simulation in the left icon plalalte.
Step 11: A set up simulation window will pop up is shown .Here I have selected the
transient analysis with the start time as ons,stop time= loons and print time step=5ns. After
specifying the values click on apply.
Step 12: To probe the waveform click on the o/p in the selection panel,then select the
input port of the schematic window as shown.
Step 13: In the setup simulation window , click add button then the port will be added to
the wave form as shown.
 Step 14: To view the simulation result by selecting the plot result from latest run icon
from the left icon palatts .This will open E2 wave for you with the o/p waveforms.

RESULT :
Thus the pass transistor logic circuit was designed and its characteristics was plotted
successfully.
CIRCUIT DIAGRAM :
EX. NO : 6 DESIGN AND PLOT THE CHARACTERISTICS OF A
DATE : TRANSMISSION GATE

AIM :
To design and plot the characteristic of a transmission gate .

SOFTWARE USED :
Mentor Graphics

THEORY :
Transmission gates represent another class of logic circuits, which use Transmission gates
as basic building block. A transmission gate consist of a PMOS and NMOS connected in parallel.
Gate voltage applied to these gates is complementary of each other (C and Cbar shown in figure
1). Transmission gates act as bidirectional switch between two nodes A and B controlled by signal
C. Gate of NMOS is connected to C and gate of PMOS is connected to Cbar(invert of C). When
control signal C is high i.e. VDD, both transistor are on and provides a low resistance path
between A and B. On the other hand, when C is low, both transistors are turned off and provide
high impedance path between A and B.

PROCEDURE :

Step 1: Go to file→new→new library→select TINCY DOC→Tannel EDA→new

folder→ok250nm. click ok
Step 2: Select file name →Add library→library folder→DOC→Tanner
EDA→Tools→process→Generic device
Step 3: Same procedure to step 2 to follow up to select→Standard
→Misc→spice→plot→spice source.
Step 4: Go to cell view →new view→library”file name”and give as cell name
→”Transmission Gate” & select a view type schematic and click on ok button.
Step 5: Select on generic 250nm devices and also select on nmos25 and pmos25
Step 6: Schematic will create and should draw on transmission gate and give
connections.
 Step 7: Click on MISC and select on GND component and Vdd components.
Step 8: Adding the ports and connecting the devices and save as schematic.
Step 9: Adding a DC voltage source & C-V source from the library and change the value
of the DC property to be 3.3V Add pulse voltage source pulse -V- source & change the property
to be 3.3V & change the delay to be OS
Step 10: Simulating the Schematic
✔ select on menu bar and select run simulation .
✔ Click ok now design context window are open and need to setup the analysis type, plots
and load in the Eldo models.
✔ In the design context from menuber select simulation →setup simulation or click on
setup simulation in the left icon plalalte.
Step 11: A set up simulation window will pop up is shown .Here I have selected the
transient analysis with the start time as ons,stop time= loons and print time step=5ns. After
specifying the values click on apply.
Step 12: To probe the waveform click on the o/p in the selection panel,then select the
input port of the schematic window as shown.
Step 13: In the setup simulation window , click add button then the port will be added to
the wave form as shown.
Step 14: To view the simulation result by selecting the plot result from latest run icon
from the left icon palatts .This will open E2 wave for you with the o/p waveforms.

RESULT :
Thus the design of pass transistor was designed and the characteristics was plotted
successfully.
CIRCUIT DIAGRAM :
EX. NO : 7 DESIGN AND PLOT THE CHARACTERISTICS OF A 4X1 DIGITAL
DATE : M ULTIPLEXER USING PASS TRANSISTOR LOGIC

AIM :
To Design and plot the characteristics of a 4x1 digital multiplexer using pass transistor
logic.

SOFTWARE REQUIRED :
Mentor Graphics