Si41 33G

Si412 3G/22G/13G/12G

D U A L -B A N D R F S Y N T H E S I Z E R W I T H I N T E G R A T E D V C O S
FOR GSM AND GPRS WIRELESS COMMUNICATIONS
Features
! Dual-Band RF Synthesizers ! Fast Settling Time: 140 µs

T
-B
G
" RF1: 900 MHz to 1.8 GHz ! Low Phase Noise

1 33
i4
S
" RF2: 750 MHz to 1.5 GHz ! Programmable Power Down Modes
! IF Synthesizer ! 1 µA Standby Current
" IF: 500 MHz to 1000 MHz ! 18 mA Typical Supply Current
! Integrated VCOs, Loop Filters, ! 2.7 V to 3.6 V Operation
Varactors, and Resonators ! Packages: 24-Pin TSSOP and
! Minimal External Components 28-Pin MLP Ordering Information:
Required See page 28.

Applications
Pin Assignments
! GSM, DCS1800, and PCS1900 ! GPRS Data Terminals
Cellular Telephones ! HSCSD Data Terminals Si4133G-BT
Description S C LK 1 24 SENB

S D ATA 2 23 VDDI

The Si4133G is a monolithic integrated circuit that performs both IF and GNDR 3 22 IF O U T
dual-band RF synthesis for GSM and GPRS wireless communications
R FL D 4 21 GNDI
applications. The Si4133G includes three VCOs, loop filters, reference and
R FL C 5 20 IF L B
VCO dividers, and phase detectors. Divider and power down settings are
programmable through a three-wire serial interface. GNDR 6 19 IF L A

R FL B 7 18 GNDD

Functional Block Diagram R FL A 8 17 VDDD

GNDR 9 16 GNDD

GNDR 10 15 X IN
R efe re nce
X IN ÷ 65 P hase R FL A R FO U T 11 14 PW DNB
A m p lifier
D etector R FL B
VDDR 12 13 AUXOUT
P ow er R F1
P W DN B D ow n
C ontrol ÷N R FO U T

S DA TA R FL C
Si4133G-BM
S erial P hase
SDATA

IFOUT
GNDR

SENB
SCLK

Interfa ce
GNDI

D etector
VDD I

S CL K R FL D
22-b it R F2
S EN B D ata 28 27 26 25 24 23 22
R egister ÷N
GNDR 1 21 GNDI

Test P hase R FLD 2 20 IF L B

A UX O U T IFO UT
Mux D etector
R FLC 3 19 IF L A
IF
IFL A GNDR 4 18 GNDD
÷N
IFL B
R FLB 5 17 VDDD

R FLA 6 16 GNDD

GNDR 7 15 X IN

8 9 10 11 12 13 14
RFOU T

AUX OU T
GNDR

GNDR

VDDR

PW DNB

GNDD

Patents pending

Rev. 1.1 4/01 Copyright © 2001 by Silicon Laboratories Si4133G-DS11

S i4 13 3G

2 Rev. 1.1
 Si4133G
TA B L E O F C O N T E N T S

Section Page
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Setting the VCO Center Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Self-Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
RF and IF Outputs (RFOUT and IFOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Auxiliary Output (AUXOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pin Descriptions: Si4133G-BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pin Descriptions: Si4133G-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Si4133G Derivative Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Package Outline: Si4133G-BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package Outline: Si4133G-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Rev. 1.1 3
S i4 13 3G
Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit

Ambient Temperature TA –20 25 85 °C
Supply Voltage VDD 2.7 3.0 3.6 V
Supply Voltages Difference V∆ (VDDR – VDDD), –0.3 — 0.3 V
(VDDI – VDDD)
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at 3.0 V and an operating temperature of 25°C unless otherwise stated.

Table 2. Absolute Maximum Ratings1,2

Parameter Symbol Value Unit

DC Supply Voltage VDD –0.5 to 4.0 V

Input Current3 IIN ±10 mA

Input Voltage3 VIN –0.3 to VDD+0.3 V

Storage Temperature Range TSTG –55 to 150 o
C
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. This device is a high performance RF integrated circuit with an ESD rating of < 2 kV. Handling and assembly of
this device should only be done at ESD-protected workstations.
3. For signals SCLK, SDATA, SENB, PWDNB and XIN.

4 Rev. 1.1
 Si4133G

Table 3. DC Characteristics
(VDD = 2.7 to 3.6 V, TA = –20 to 85°C

Parameter Symbol Test Condition Min Typ Max Unit

1
Typical Supply Current RF1 and IF Operating — 18 31 mA
RF1 Mode Supply Current1 — 13 17 mA
RF2 Mode Supply Current1 — 12 17 mA
IF Mode Supply Current1 — 10 14 mA
Standby Current PWDNB = 0 — 1 — µA
High Level Input Voltage2 VIH 0.7 VDD — — V
Low Level Input Voltage2 VIL — — 0.3 VDD V
High Level Input Current2 IIH VIH = 3.6 V, –10 — 10 µA
VDD = 3.6 V
Low Level Input Current2 IIL VIL = 0 V, –10 — 10 µA
VDD= 3.6 V
High Level Output Voltage3 VOH IOH = –500 µA VDD–0.4 — — V
Low Level Output Voltage3 VOL IOH = 500 µA — — 0.4 V
Notes:
1. RF1 = 1.55 GHz, RF2 = 1.2 GHz, IF = 800 MHz
2. For signals SCLK, SDATA, SENB, and PWDNB.
3. For signal AUXOUT.

Rev. 1.1 5
S i4 13 3G

Table 4. Serial Interface Timing

(VDD = 2.7 to 3.6 V, TA = –20 to 85°C)

Parameter1 Symbol Test Condition Min Typ Max Unit

SCLK Cycle Time tclk Figure 1 40 — — ns

SCLK Rise Time tr Figure 1 — — 50 ns
SCLK Fall Time tf Figure 1 — — 50 ns
SCLK High Time th Figure 1 10 — — ns
SCLK Low Time tl Figure 1 10 — — ns
SDATA Setup Time to SCLK↑2 tsu Figure 2 5 — — ns
SDATA Hold Time from SCLK↑2 thold Figure 2 0 — — ns
2
SENB↓ to SCLK↑ Delay Time ten1 Figure 2 10 — — ns
SCLK↑ to SENB↑ Delay Time2 ten2 Figure 2 12 — — ns
SENB↑ to SCLK↑ Delay Time2 ten3 Figure 2 12 — — ns
SENB Pulse Width tw Figure 2 10 — — ns
Notes:
1. All timing is referenced to the 50% level of the waveform, unless otherwise noted.
2. Timing is not referenced to 50% level of waveform. See Figure 2.

tr tf
80%
S CLK 50%
20%
th tl
t clk

Figure 1. SCLK Timing Diagram

6 Rev. 1.1
 Si4133G

ts u thold

S CLK

S DA TA D17 D16 D15 A1 A0

ten3
ten1
ten2

S E NB

tw

Figure 2. Serial Interface Timing Diagram

First bit Las t bit

c loc ked in c loc ked in

D D D D D D D D D D D D D D D D D D A A A A
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0

data addres s
field field

Figure 3. Serial Word Format

Rev. 1.1 7
S i4 13 3G

Table 5. RF and IF Synthesizer Characteristics

(VDD = 2.7 to 3.6 V, TA = –20 to 85°C)

Parameter1 Symbol Test Condition Min Typ Max Unit

XIN Input Frequency fREF — 13 — MHz
Reference Amplifier Sensitivity VREF 0.5 — VDD VPP
+0.3
Phase Detector Update Frequency fφ fφ = fREF/R 200 KHz
RF1 Center Frequency Range fCEN 947 — 1720 MHz
RF2 Center Frequency Range fCEN 789 — 1429 MHz
IF VCO Center Frequency fCEN 526 — 952 MHz
Tuning Range from fCEN Note: LEXT ±10% –5 — 5 %
RF1 VCO Pushing Open loop — 0.5 — MHz/V
RF2 VCO Pushing — 0.4 — MHz/V
IF VCO Pushing — 0.3 — MHz/V
RF1 VCO Pulling VSWR = 2:1, all — 0.4 — MHzPP
RF2 VCO Pulling phases, open loop — 0.1 — MHzPP
IF VCO Pulling — 0.1 — MHzPP
RF1 Phase Noise 1 MHz offset — –132 — dBc/Hz
3 MHz offset — –142 — dBc/Hz
RF1 Integrated Phase Error 100 Hz to 100 kHz — 0.9 — deg rms
RF2 Phase Noise 1 MHz offset — –134 — dBc/Hz
3 MHz offset — –144 — dBc/Hz
RF2 Integrated Phase Error 100 Hz to 100 kHz — 0.7 — deg rms
IF Phase Noise 100 kHz offset — –117 — dBc/Hz
IF Integrated Phase Error 100 Hz to 100 kHz — 0.4 — deg rms
RF1 Harmonic Suppression Second Harmonic — –26 — dBc
RF2 Harmonic Suppression — –26 — dBc
IF Harmonic Suppression — –26 — dBc
RFOUT Power Level ZL = 50 Ω –7 –2 1 dBm
IFOUT Power Level ZL = 50 Ω –8 –6 –1 dBm
RF1 Reference Spurs Offset = 200 kHz — –70 — dBc
Offset = 400 kHz — –75 — dBc
Offset = 600 kHz — –80 — dBc
RF2 Reference Spurs Offset = 200 kHz — –75 — dBc
Offset = 400 kHz — –80 — dBc
Offset = 600 kHz — –80 — dBc
Power Up Request to Synthesizer tpup Figures 4, 5 — 140 — µs
Ready Time, RF1, RF2, IF2
Power Down Request to Synthesizer Off tpdn Figures 4, 5 — — 100 ns
Time3
Notes:
1. RF1 = 1.55 GHz, RF2 = 1.2 GHz, IF = 550 MHz for all parameters unless otherwise noted.
2. From power up request (PWDNB↑ or SENB↑ during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF
synthesizers ready (settled to within 0.1 ppm frequency error). Typical settling time to 5 degrees phase error is 120 µs.
3. From power down request (PWDNB↓, or SENB↑ during a write of 0 to bits PDIB and PDRB in Register 2) to supply
current equal to IPWDN.

8 Rev. 1.1
 Si4133G

RF and IF s y nthes iz ers s ettled to R F and IF synthesizers s ettled to

w ithin 0.1 ppm f requenc y error. within 0.1 ppm frequency error.

t t t pup t pdn
p up p dn
IT IT

I PW D N I PW D N

S E NB PW DNB

PD IB = 1 PD IB = 0
S DA TA PD R B = 1 PD R B = 0

Figure 4. Software Power Management Timing Figure 5. Hardware Power Management Timing
Diagram Diagram

Rev. 1.1 9
S i4 13 3G

TRACE A: Ch1 FM Gate Time

A Offset 133.59375 us
800
Hz

Real
Axis is 0.1 ppm/div

160
Hz
/div

-800
Hz
Start: 0 s Stop: 299.21875 us

Figure 6. Typical Transient Response RF1 at 1.6 GHz

with 200 kHz Phase Detector Update Frequency

10 Rev. 1.1
 Si4133G

−60

−70

−80
Phase Noise (dBc/Hz)

−90

−100

−110

−120

−130

−140
2 3 4 5 6
10 10 10 10 10
Offset Frequency (Hz)

Figure 7. Typical RF1 Phase Noise at 1.6 GHz

with 200 kHz Phase Detector Update Frequency

Figure 8. Typical RF1 Spurious Response at 1.6 GHz

with 200 kHz Phase Detector Update Frequency

Rev. 1.1 11
S i4 13 3G

−60

−70

−80
Phase Noise (dBc/Hz)

−90

−100

−110

−120

−130

−140
2 3 4 5 6
10 10 10 10 10
Offset Frequency (Hz)

Figure 9. Typical RF2 Phase Noise at 1.2 GHz

with 200 kHz Phase Detector Update Frequency

Figure 10. Typical RF2 Spurious Response at 1.2 GHz

with 200 kHz Phase Detector Update Frequency

12 Rev. 1.1
 Si4133G

−70

−80

−90
Phase Noise (dBc/Hz)

−100

−110

−120

−130

−140

−150
2 3 4 5 6
10 10 10 10 10
Offset Frequency (Hz)

Figure 11. Typical IF Phase Noise at 550 MHz

with 200 kHz Phase Detector Update Frequency

Figure 12. IF Spurious Response at 550 MHz

with 200 kHz Phase Detector Update Frequency

Rev. 1.1 13
S i4 13 3G

S i41 33 G -B T
From
1 24
S ys te m S C LK SENB
V DD 0 .02 2 µ F
C on tro lle r 2 23
S D ATA VDDI
1 0 nH 5 6 0p F
3 22
GNDR IFO U T IFO U T

4 21
R FL D GNDI
P rinte d Tra c e
5 20
R FL C IFL B Ind uc tor or
C hip In du ctor
P rinte d Tra c e 6 19
GNDR IFL A
Ind uc tors
7 18
R FL B GNDD
V DD 0 .02 2 µ F
8 17
R FL A VDDD

9 16
GNDR GNDD
560 pF
10 15
GNDR X IN E x te rn al C loc k
5 6 0p F 2 nH
11 14
R FO U T R FO U T PW DNB PDWNB
0.022µ F V DD
12 13
VDDR AUXO UT AUXO UT

Figure 13. Typical Application Circuit: Si4133G-BT

VDD
F ro m
0.02 2 µ F
S ys tem 10 n H 56 0p F
C o n tro ller IF O U T

28 27 26 25 24 23 22
VDDI

GNDI
SENB

IFOUT
GNDR

SDATA

SCLK

1 21 P rin ted Trace

GNDR GNDI
In d u cto r o r
2 20 C h ip In d u cto r
RFLD IF L B

3 19
RFLC IF L A

P rin ted Trace 4 18

In d u cto rs
GNDR S i4 1 3 3 G -B M GNDD V DD

5 17
RFLB VDDD

6 16 0.02 2 µ F
RFLA GNDD
56 0p F
7 15
AUXOUT

GNDR X IN E xte rn a l C lo ck
PWDNB
RFOUT
GNDR

GNDR

GNDD
VDDR

8 9 10 11 12 13 14

V DD

0.02 2 µ F
AUXOUT

PW DNB 2n H 56 0p F

RFOUT

Figure 14. Typical Application Circuit: Si4133G-BM

14 Rev. 1.1
 Si4133G
Functional Description The Si4133G is programmed serially with 22-bit words
comprised of 18-bit data fields and 4-bit address fields.
The Si4133G is a monolithic integrated circuit that When the serial interface is enabled (i.e., when SENB is
performs IF and dual-band RF synthesis for many low) data and address bits on the SDATA pin are
wireless applications such as GSM, DCS1800, and clocked into an internal shift register on the rising edge
PCS1900. Its fast transient response also makes the of SCLK. Data in the shift register is then transferred on
Si4133G especially well suited to GPRS and HSCSD the rising edge of SENB into the internal data register
multislot applications where channel switching and addressed in the address field. The serial interface is
settling times are critical. This integrated circuit (IC), disabled when SENB is high.
with a minimum number of external components, is all Table 10 on page 20 summarizes the data register
that is necessary to implement the frequency synthesis functions and addresses. The internal shift register will
function. ignore any leading bits before the 22 required bits.
The Si4133G has three complete phase-locked loops
(PLLs) with integrated voltage-controlled oscillators Setting the VCO Center Frequencies
(VCOs). The low phase noise of the VCOs makes the The PLLs can adjust the IF and RF output frequencies
Si4133G suitable for use in demanding wireless ±5% with respect to their VCO center frequencies. Each
communications applications. Also integrated are phase center frequency is established by the value of an
detectors, loop filters, and reference dividers. The IC is external inductance connected to the respective VCO.
programmed through a three-wire serial interface. Manufacturing tolerances of ±10% for the external
One PLL is provided for IF synthesis, and two PLLs are inductances are acceptable. The Si4133G will
provided for dual-band RF synthesis. One RF VCO is compensate for inaccuracies in each inductance by
optimized to have its center frequency set between executing a self-tuning algorithm following PLL power-
947 MHz and 1720 MHz, while the second RF VCO is up or following a change in the programmed output
optimized to have its center frequency set between frequency.
789 MHz and 1429 MHz. The IF VCO is optimized to Because the total tank inductance is in the low nH
have its center frequency set between 526 MHz and range, the inductance of the package needs to be
952 MHz. Each PLL can adjust its output frequency by considered in determining the correct external
±5% relative to its VCO center frequency. inductance. The total inductance (LTOT) presented to
The center frequency of each of the three VCOs is set each VCO is the sum of the external inductance (LEXT)
by connection of an external inductance. Inaccuracies in and the package inductance (LPKG). Each VCO has a
the value of the inductance are compensated for by the nominal capacitance (CNOM) in parallel with the total
Si4133G’s proprietary self-tuning algorithm. This inductance, and the center frequency is as follows:
algorithm is initiated each time the PLL is powered-up
1
(by either the PWDNB pin or by software) and/or each fCEN = ---------------------------------------------
2π L TOT ⋅ C NOM
time a new output frequency is programmed.
The two RF PLLs share a common output pin, so only or
one PLL is active at a given time. Because the two
VCOs can be set to have widely separated center 1
fCEN = ----------------------------------------------------------------------
frequencies, the RF output can be programmed to 2π ( L PKG + L EXT ) ⋅ C NOM
service different frequency bands, thus making the
Tables 6 and 7 summarize these characteristics for
Si4133G ideal for use in dual-band cellular handsets.
each VCO.
The unique PLL architecture used in the Si4133G
produces a transient response that is superior in speed
to fractional-N architectures without suffering the high
phase noise or spurious modulation effects often
associated with those designs.
Serial Interface
A timing diagram for the serial interface is shown in
Figure 2 on page 7. Figure 3 on page 7 shows the
format of the serial word.

Rev. 1.1 15
S i4 13 3G
in addition to 2.3 nH of LPKG (Si4133G-BT), will present
Table 6. Si4133G-BT VCO Characteristics the correct total inductance to the VCO. In
manufacturing, the external inductance can vary ±10%
VCO Fcen Range Cnom Lpkg Lext Range
of its nominal value and the Si4133G will correct for the
(MHz) (pF) (nH) (nH)
variation with the self-tuning algorithm.
Min Max Min Max In most cases, particularly for the RF VCOs, the
requisite value of the external inductance is small
RF1 947 1720 4.3 2.0 0.0 4.6 enough to allow a PC board trace to be utilized. During
RF2 789 1429 4.8 2.3 0.3 6.2 initial board layout, a length of trace approximating the
desired inductance can be used. For more information,
IF 526 952 6.5 2.1 2.2 12.0 please refer to Application Note 31.
Self-Tuning Algorithm
Table 7. Si4133G-BM VCO Characteristics The self-tuning algorithm is initiated immediately
following power-up of a PLL or, if the PLL is already
VCO Fcen Range Cnom Lpkg Lext Range powered, following a change in its programmed output
(MHz) (pF) (nH) (nH) frequency. This algorithm attempts to tune the VCO so
Min Max Min Max that its free-running frequency is near the desired output
frequency. In so doing, the algorithm will compensate
RF1 947 1720 4.3 1.5 0.5 5.1 for manufacturing tolerance errors in the value of the
external inductance connected to the VCO. It will also
RF2 789 1429 4.8 1.5 1.1 7.0 reduce the frequency error for which the PLL must
correct to get the precise desired output frequency. The
IF 526 952 6.5 1.6 2.7 12.5
self-tuning algorithm will leave the VCO oscillating at a
frequency in error by somewhat less than 1% of the
desired output frequency.
After self-tuning, the PLL controls the VCO oscillation
frequency. The PLL will complete frequency locking,
eliminating any remaining frequency error. Thereafter, it
L PK G
will maintain frequency-lock, compensating for effects
2
caused by temperature and supply voltage variations.
L EXT
The Si4133G’s self-tuning algorithm will compensate for
component value errors at any temperature within the
specified temperature range. However, the ability of the
L PK G PLL to compensate for drift in component values that
2
occur after self-tuning is limited. For external
inductances with temperature coefficients around
Figure 15. External Inductance Connection ±150 ppm/oC, the PLL will be able to maintain lock for
changes in temperature of approximately ±30oC.
As a design example, suppose it is desired to Applications where the PLL is regularly powered down
synthesize frequencies in a 25 MHz band between (such as GSM) or switched between channels minimize
1120 MHz and 1145 MHz. The center frequency should or eliminate the potential effects of temperature drift
be defined as midway between the two extremes, or because the VCO is re-tuned when it is powered up or
1132.5 MHz. The PLL will be able to adjust the VCO when a new frequency is programmed. In applications
output frequency ±5% of the center frequency, or where the ambient temperature can drift substantially
±56.6 MHz of 1132.5 MHz (i.e., from approximately after self-tuning, it may be necessary to monitor the
1076 MHz to 1189 MHz, more than enough for this LDETB (lock-detect bar) signal on the AUXOUT pin to
example). The RF2 VCO has a CNOM of 4.8 pF, and a determine the locking state of the PLL. (See "Auxiliary
4.1 nH inductance (correct to two digits) in parallel with Output (AUXOUT)" on page 18 for how to select
this capacitance will yield the desired center frequency. LDETB.)
An external inductance of 1.8 nH should be connected The LDETB signal is normally low after self-tuning is
between RFLC and RFLD as shown in Figure 15. This, completed but will rise to a logic high condition when

16 Rev. 1.1
 Si4133G
either the IF or RF PLL nears the limit of its the RF and IF PLLs Tφ = 5 µS. During the first 6.5
compensation range (LDETB will also be high when update periods, the Si4133G executes the self-tuning
either PLL is executing the self-tuning algorithm). The algorithm. Thereafter the PLL controls the output
output frequency will still be locked when LDETB goes frequency. Because of the unique architecture of the
high, but the PLL will eventually lose lock if the Si4133G PLLs, the time required to settle the output
temperature continues to drift in the same direction. frequency to 0.1 ppm error is approximately 21 update
Therefore, if LDETB goes high both the IF and RF PLLs periods. Thus, the total time after power-up or a change
should promptly be re-tuned by initiating the self-tuning in programmed frequency until the synthesized
algorithm. frequency is well settled (including time for self-tuning)
is around 28 update periods or 140 µS.
Output Frequencies
The IF and RF output frequencies are set by RF and IF Outputs (RFOUT and IFOUT)
programming the N-Divider registers. Each RF PLL has The RFOUT pin is driven by an amplifier that buffers the
its own N register and can be programmed output pin from the RF VCOs, and must be coupled to
independently. All three PLL R dividers are fixed at its load through an AC coupling capacitor. The amplifier
R = 65 to yield a 200 kHz phase detector update rate receives its input from either the RF1 or RF2 VCO,
from a 13 MHz reference frequency. Programming the depending upon which N-Divider register was last
N-Divider register for either RF1 or RF2 automatically written. For example, programming the N-Divider
selects the associated output. register for RF1 automatically selects the RF1 VCO
The reference frequency on the XIN pin is divided by R output.
and this signal is the input to the PLL’s phase detector. A matching network is required to maximize power
The other input to the phase detector is the PLL’s VCO delivered into a 50 Ω load. The network consists of a 2
output frequency divided by N. The PLL works to make nH series inductance, which may be realized with a PC
these frequencies equal. That is, after an initial transient board trace, connected between the RFOUT pin and
the AC coupling capacitor. The network is made to
f OUT fREF provide an adequate match for both the RF1 and RF2
-----------
- = -----------
N 65 frequency bands, and also filters the output signal to
or reduce harmonic distortion. A 50 Ω load is not required
for proper operation of the Si4133G. Depending on
N
f OUT = ------ ⋅ f REF
transceiver requirements, the matching network may
65 not be needed. See Figure 16.
For XIN = 13 MHz this simplifies to
560 pF
fOUT = N ⋅ 200 kHz
RFOUT
2 nH
The integer N is set by programming the RF1 N-Divider
register (Register 3), the RF2 N-Divider register 50 Ω
(Register 4), and the IF N-Divider register (Register 5).
Each N divider is implemented as a conventional high
speed divider. That is, it consists of a dual-modulus
prescaler, a swallow counter, and a lower speed Figure 16. RFOUT 50 Ω Test Circuit
synchronous counter. However, the calculation of these
values is done automatically. Only the appropriate N The IFOUT pin is driven by an amplifier that buffers the
value needs to be programmed. output pin from the IF VCO. The IFOUT pin must be
coupled to its load through an AC coupling capacitor. A
PLL Loop Dynamics matching network is required to maximize power
The transient response for each PLL has been delivered into a 50 Ω load. See Figure 17.
optimized for a GSM application. VCO gain, phase
detector gain, and loop filter characteristics are not
programmable.
The settling time for each PLL is directly proportional to
its phase detector update period Tφ (Tφ equals 1/fφ). For
a GSM application with a 13 MHz reference frequency,

Rev. 1.1 17
S i4 13 3G
Reference Frequency Amplifier
560 pF
The Si4133G provides a reference frequency amplifier.
IFOUT If the driving signal has CMOS levels it can be
L MATCH connected directly to the XIN pin. Otherwise, the
50 Ω
reference frequency signal should be AC coupled to the
XIN pin through a 560 pF capacitor.
Power Down Modes
Figure 17. IFOUT 50 Ω Test Circuit Table 9 summarizes the power down functionality. The
Si4133G can be powered down by taking the PWDNB
pin low or by setting bits in the Power Down register
Table 8. LMATCH Values (Register 1). When the PWDNB pin is low, the Si4133G
will be powered down regardless of the Power Down
Frequency LMATCH register settings. When the PWDNB pin is high, power
management is under control of the Power Down
500–600 MHz 40 nH register bits.
600–800 MHz 27 nH The reference frequency amplifier, IF, and RF sections
of the Si4133G circuitry can be individually powered
800–1 GHz 18 nH down by setting the Power Down register bits PDIB and
PDRB low, respectively. The reference frequency
The IF output level is dependent upon the load. amplifier will also be powered up if either of the PDRB
Figure 18 displays the output level versus load or PDIB bits are high. Also, setting the AUTOPDB bit to
resistance for a variety of output frequencies. 1 in the Main Configuration register (Register 0) is
equivalent to setting both bits in the Power Down
450 register to 1. The serial interface remains available and
400
can be written in all power down modes.
350
LPWR=1
Auxiliary Output (AUXOUT)
LPWR=0
300
The signal appearing on AUXOUT is selected by setting
Output Voltage (mVrms)

250
the AUXSEL bits in the Main Configuration register
200 (Register 0).
150 The LDETB signal can be selected by setting the
100
AUXSEL bits to 11. As discussed previously, this signal
50
can be used to indicate that the IF or RF PLL is about to
lose lock due to excessive ambient temperature drift and
0
0 200 400 600
Ω)
800 1000 1200 should be re-tuned.
Load Resistance (Ω

Figure 18. Typical IF Output Voltage vs. Load

Resistance at 550 MHz

For resistive loads greater than 500 Ω the output level

saturates and the bias currents in the IF output amplifier
are higher than they need be. The LPWR bit in the Main
Configuration register (Register 0) can be set to 1 to
reduce the bias currents and therefore reduce the
power dissipated by the IF amplifier. For loads less than
500 Ω LPWR should be set to 0 to maximize the output
level.

18 Rev. 1.1
 Si4133G
Table 9. Power Down Configuration

PWDNB Pin AUTOPDB PDIB PDRB IF Circuitry RF Circuitry

PWDNB = 0 x x x OFF OFF

0 0 0 OFF OFF

0 0 1 OFF ON

PWDNB = 1 0 1 0 ON OFF

0 1 1 ON ON

1 x x ON ON

Rev. 1.1 19
S i4 13 3G
Control Registers

Table 10. Register Summary

Register Name Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Main 0 0 0 0 AUXSEL 0 0 0 0 0 0 LPWR 0 AUTO 0 1 0
[1:0] PDB
Configuration
1 Reserved
2 Power Down 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDIB PDRB

3 RF1 N Divider NRF1[17:0]

4 RF2 N Divider 0 NRF[16:0]
5 IF N Divider 0 0 NIF[15:0]
6 Reserved
.
.
.
15 Reserved

Note: Registers 1 and 6–15 are reserved. Writes to these registers may result in unpredictable behavior. Any register not listed
here is reserved and should not be written.

20 Rev. 1.1
 Si4133G

Register 0. Main Configuration Address Field = A[3:0] = 0000

Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Name 0 0 0 0 AUXSEL 0 0 0 0 0 0 LPWR 0 AUTO 0 1 0
PDB
[1:0]

Bit Name Function

17:14 Reserved Program to zero.
13:12 AUXSEL Auxiliary Output Pin Definition.
[1:0] 00 = Reserved.
01 = Force output low.
10 = Reserved.
11 = Lock Detect—LDETB.
11:6 Reserved Program to zero.
5 LPWR Output Power-Level Settings for IF Synthesizer Circuit.
0 = RLOAD < 500 Ω—normal power mode.
1 = RLOAD ≥ 500 Ω—low power mode.
4 Reserved Program to zero.
3 AUTOPDB Auto Power Down
0 = Software powerdown is controlled by Register 2.
1 = Equivalent to setting all bits in Register 2 = 1.
2 Reserved Program to zero.
1 Reserved Program to one.
0 Reserved Program to zero.

Rev. 1.1 21
S i4 13 3G

Register 2. Power Down Address Field (A[3:0]) = 0010

Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDIB PDRB

Bit Name Function

17:2 Reserved Program to zero.
1 PDIB Power Down IF Synthesizer.
0 = IF synthesizer powered down.
1 = IF synthesizer on.
Note: Always program to 0 for Si4113G.
0 PDRB Power Down RF Synthesizer.
0 = RF synthesizer powered down.
1 = RF synthesizer on.
Note: Always program to 0 for Si4112G.

Register 3. RF1 N Divider Address Field (A[3:0]) = 0011

Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Name NRF1[17:0]

Bit Name Function

17:0 NRF1[17:0] N Divider for RF1 Synthesizer.
Register reserved for Si4112G, Si4122G. Writes to this register may result in unpre-
dictable behavior.

22 Rev. 1.1
 Si4133G

Register 4. RF2 N Divider Address Field = A[3:0] = 0100

Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Name 0 NRF2[16:0]

Bit Name Function

17 Reserved Program to zero.
16:0 NRF2[16:0] N Divider for RF2 Synthesizer.
Register reserved for Si4112G, Si4123G. Writes to this register may result in
unpredictable behavior.

Register 5. IF N Divider Address Field (A[3:0]) = 0101

Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Name 0 0 NIF[15:0]

Bit Name Function

17:16 Reserved Program to zero.
15:0 NIF[15:0] N Divider for IF Synthesizer.
Register reserved for Si4113G. Writes to this register may result in
unpredictable behavior.

Rev. 1.1 23
S i4 13 3G
Pin Descriptions: Si4133G-BT

SCLK 1 24 SEN B

S D ATA 2 23 VDDI

GNDR 3 22 IF O U T

RFLD 4 21 GNDI

RFLC 5 20 IF L B

GNDR 6 19 IF L A

RFLB 7 18 GNDD

RFLA 8 17 VDDD

GNDR 9 16 GNDD

GNDR 10 15 X IN

RFOU T 11 14 PWDNB

VDDR 12 13 AUXOUT

Pin Number(s) Name Description

1 SCLK Serial clock input
2 SDATA Serial data input
3, 6, 9, 10 GNDR Common ground for RF analog circuitry
4, 5 RFLC, RFLD Pins for inductor connection to RF2 VCO
7, 8 RFLA, RFLB Pins for inductor connection to RF1 VCO
11 RFOUT Radio frequency (RF) output of the selected RF VCO
12 VDDR Supply voltage for the RF analog circuitry
13 AUXOUT Auxiliary output
14 PWDNB Power down input pin
15 XIN Reference frequency amplifier input
16, 18 GNDD Common ground for digital circuitry
17 VDDD Supply voltage for digital circuitry
19, 20 IFLA, IFLB Pins for inductor connection to IF VCO
21 GNDI Common ground for IF analog circuitry
22 IFOUT Intermediate frequency (IF) output of the IF VCO
23 VDDI Supply voltage for IF analog circuitry
24 SENB Enable serial port input

24 Rev. 1.1
 Si4133G

Table 11. Pin Descriptions for Si4133G Derivatives—TSSOP

Pin Number Si4133G-BT Si4123G-BT Si4122G-BT Si4113G-BT Si4112G-BT

1 SCLK SCLK SCLK SCLK SCLK

2 SDATA SDATA SDATA SDATA SDATA

3 GNDR GNDR GNDR GNDR GNDD

4 RFLD GNDR RFLD RFLD GNDD

5 RFLC GNDR RFLC RFLC GNDD

6 GNDR GNDR GNDR GNDR GNDD

7 RFLB RFLB GNDR RFLB GNDD

8 RFLA RFLA GNDR RFLA GNDD

9 GNDR GNDR GNDR GNDR GNDD

10 GNDR GNDR GNDR GNDR GNDD

11 RFOUT RFOUT RFOUT RFOUT GNDD

12 VDDR VDDR VDDR VDDR VDDD

13 AUXOUT AUXOUT AUXOUT AUXOUT AUXOUT

14 PWDNB PWDNB PWDNB PWDNB PWDNB

15 XIN XIN XIN XIN XIN

16 GNDD GNDD GNDD GNDD GNDD

17 VDDD VDDD VDDD VDDD VDDD

18 GNDD GNDD GNDD GNDD GNDD

19 IFLA IFLA IFLA GNDD IFLA

20 IFLB IFLB IFLB GNDD IFLB

21 GNDI GNDI GNDI GNDD GNDI

22 IFOUT IFOUT IFOUT GNDD IFOUT

23 VDDI VDDI VDDI VDDD VDDI

24 SENB SENB SENB SENB SENB

Rev. 1.1 25
S i4 13 3G
Pin Descriptions: Si4133G-BM

SDATA

IFO UT
GN DR

SENB
SCLK

GN DI
VDD I
28 27 26 25 24 23 22

GNDR 1 21 GNDI

R FLD 2 20 IFLB

R FLC 3 19 IFLA

GNDR 4 18 GNDD

R FLB 5 17 VDDD

R FLA 6 16 GNDD

GNDR 7 15 X IN

8 9 10 11 12 13 14
R FO U T

AUX OU T
GN DR

GN DR

VD DR

PW D NB

Pin Number(s) Name Description GN DD

1, 4, 7–9, 28 GNDR Common ground for RF analog circuitry

2, 3 RFLC, RFLD Pins for inductor connection to RF2 VCO
5,6 RFLA, RFLB Pins for inductor connection to RF1 VCO
10 RFOUT Radio frequency (RF) output of the selected RF VCO
11 VDDR Supply voltage for the RF analog circuitry
12 AUXOUT Auxiliary output
13 PWDNB Power down input pin
14, 16, 18 GNDD Common ground for digital circuitry
15 XIN Reference frequency amplifier input
17 VDDD Supply voltage for digital circuitry
19, 20 IFLA, IFLB Pins for inductor connection to IF VCO
21, 22 GNDI Common ground for IF analog circuitry
23 IFOUT Intermediate frequency (IF) output of the IF VCO
24 VDDI Supply voltage for IF analog circuitry
25 SENB Enable serial port input
26 SCLK Serial clock input
27 SDATA Serial data input

26 Rev. 1.1
 Si4133G

Table 12. Pin Descriptions for Si4133G Derivatives—MLP

Pin Number Si4133G-BM Si4123G-BM Si4122G-BM Si4113G-BM Si4112G-BM

1 GNDR GNDR GNDR GNDR GNDD

2 RFLD GNDR RFLD RFLD GNDD

3 RFLC GNDR RFLC RFLC GNDD

4 GNDR GNDR GNDR GNDR GNDD

5 RFLB RFLB GNDR RFLB GNDD

6 RFLA RFLA GNDR RFLA GNDD

7 GNDR GNDR GNDR GNDR GNDD

8 GNDR GNDR GNDR GNDR GNDD

9 GNDR GNDR GNDR GNDR GNDD

10 RFOUT RFOUT RFOUT RFOUT GNDD

11 VDDR VDDR VDDR VDDR VDDD

12 AUXOUT AUXOUT AUXOUT AUXOUT AUXOUT

13 PWDNB PWDNB PWDNB PWDNB PWDNB

14 GNDD GNDD GNDD GNDD GNDD

15 XIN XIN XIN XIN XIN

16 GNDD GNDD GNDD GNDD GNDD

17 VDDD VDDD VDDD VDDD VDDD

18 GNDD GNDD GNDD GNDD GNDD

19 IFLA IFLA IFLA GNDD IFLA

20 IFLB IFLB IFLB GNDD IFLB

21 GNDI GNDI GNDI GNDD GNDI

22 GNDI GNDI GNDI GNDD GNDI

23 IFOUT IFOUT IFOUT GNDD IFOUT

24 VDDI VDDI VDDI VDDD VDDI

25 SENB SENB SENB SENB SENB

26 SCLK SCLK SCLK SCLK SCLK

27 SDATA SDATA SDATA SDATA SDATA

28 GNDR GNDR GNDR GNDR GNDD

Rev. 1.1 27
S i4 13 3G
Ordering Guide

Ordering Part Description Operating

Number Temperature
Si4133G-BT* RF1/RF2/IF –20 to 85oC
Si4133G-BM
Si4123G-BT* RF1/IF –20 to 85oC
Si4123G-BM
Si4122G-BT* RF2/IF –20 to 85oC
Si4122G-BM
Si4113G-BT* RF1/RF2 –20 to 85oC
Si4113G-BM
Si4112G-BT* IF –20 to 85oC
Si4112G-BM
*Note: TSSOP not recommended for new designs.

Si4133G Derivative Devices

The Si4133G performs both IF and dual-band RF frequency synthesis. The Si4112G, Si4113G, Si4122G, and the
Si4123G are derivatives of this device. Table 13 outlines which synthesizers each derivative device features as
well as which pins and registers coincide with each synthesizer.

Table 13. Si4133G Derivatives

Name Synthesizer Pins Registers

Si4112G IF IFLA, IFLB NIF, RIF, PDIB, IFDIV, LPWR, AUTOPDB = 0,

PDRB = 0

Si4113G RF1, RF2 RFLA, RFLB, RFLC, RFLD NRF1, NRF2, RRF1, RRF2, PDRB, AUTOPDB = 0,
PDIB = 0

Si4122G RF2, IF RFLC, RFLD, IFLA, IFLB NRF2, RRF2, PDRB, NIF, RIF, PDIB, LPWR

Si4123G RF1, IF RFLA, RFLB, IFLA, IFLB NRF1, RRF1, PDRB, NIF, RIF, PDIB, LPWR

Si4133G RF1, RF2, IF RFLA, RFLB, RFLC, RFLD, NRF1, NRF2, RRF1, RRF2, PDRB, NIF, RIF,
IFLA, IFLB PDIB, LPWR

28 Rev. 1.1
 Si4133G
Package Outline: Si4133G-BT

θ2
E1 E

S
R1
R

θ1
L
e L1

θ3

c
A2 A

A1

Figure 19. 24-pin Thin Small Shrink Outline Package (TSSOP)

Table 14. Package Diagram Dimensions

Symbol Millimeters
Min Nom Max
A — 1.10 1.20
A1 0.05 — 0.15
A2 0.80 1.00 1.05
b 0.19 — 0.30
c 0.09 — 0.20
D 7.70 7.80 7.90
e 0.65 BSC
E 6.40 BSC
E1 4.30 4.40 4.50
L 0.45 0.60 0.75
L1 1.00 REF
R 0.09 — —
R1 0.09 — —
S 0.20 — —
θ1 0 — 8
θ2 12 REF
θ3 12 REF

Rev. 1.1 29
S i4 13 3G
Package Outline: Si4133G-BM

Figure 20. 28-Pin Micro Leadframe Package (MLP)

Table 15. Package Dimensions

Controlling Dimension: mm
Symbol Millimeters
Min Nom Max
A — 0.90 1.00
A1 0.00 0.01 0.05
b 0.18 0.23 0.30
D 5.00 BSC
D1 4.75 BSC
E 5.00 BSC
E1 4.75 BSC
N 28
Nd 7
Ne 7
e 0.50 BSC
L 0.50 0.60 0.75
θ 12°

30 Rev. 1.1
 Si4133G

NOTES:

Rev. 1.1 31
S i4 13 3G
Contact Information
Silicon Laboratories Inc.
4635 Boston Lane
Austin, Texas 78735
Tel:1+ (512) 416-8500
Fax:1+ (512) 416-9669
Toll Free:1+ (877) 444-3032
Email: productinfo@silabs.com
Internet: www.silabs.com

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32 Rev. 1.1