AND Gate:
Code:
module andd1(
input a,
input b,
output y
);
assign y = a & b;
endmodule
TESTBENCH:
module andd1_tb;
reg a, b;
wire y;
andd1 dut (
.a(a),
.b(b),
.y(y)
);
initial begin
a = 0; b = 0; #10; $display("[%t] a = %b, b = %b, y = %b", $time, a, b, y);
a = 0; b = 1; #10; $display("[%t] a = %b, b = %b, y = %b", $time, a, b, y);
a = 1; b = 0; #10; $display("[%t] a = %b, b = %b, y = %b", $time, a, b, y);
a = 1; b = 1; #10; $display("[%t] a = %b, b = %b, y = %b", $time, a, b, y);
$finish;
end
endmodule
// All basic logic gates in a single file
//DATAFLOW
module logic_gate(
input a,
input b,
output p,q,r,s,t,u,v
);
assign p = a & b;
assign q = a | b;
assign r = ~a;
assign s = a ^ b;
assign t = ~(a & b);
assign u = ~(a | b);
assign v = ~(a ^ b);
endmodule
// Testbench for all gates
module logic1_tb;
reg a, b;
wire p,q,r,s,t,u,v;
logic_gate dut (
.a(a),
.b(b),
.p(p),
.q(q),
.r(r),
.s(s),
.t(t),
.u(u),
.v(v)
);
initial begin
// Test vectors
a = 0; b = 0; #10; $display("[%t] a = %b, b = %b, p = %b, q = %b, r = %b, s = %b, t = %b, u = %b, v = %b ",
$time, a, b, p, q, r, s, t, u, v);
a = 0; b = 1; #10; $display("[%t] a = %b, b = %b, p = %b, q = %b, r = %b, s = %b, t = %b, u = %b, v = %b ",
$time, a, b, p, q, r, s, t, u, v);
a = 1; b = 0; #10; $display("[%t] a = %b, b = %b, p = %b, q = %b, r = %b, s = %b, t = %b, u = %b, v = %b ",
$time, a, b, p, q, r, s, t, u, v);
a = 1; b = 1; #10; $display("[%t] a = %b, b = %b, p = %b, q = %b, r = %b, s = %b, t = %b, u = %b, v = %b ",
$time, a, b, p, q, r, s, t, u, v);
$finish;
end
endmodule
//BEHAVIORAL
module LOGIC_BEH(
input a,
input b,
output reg p, q, r, s, t, u, v
);
always @(*) begin
p = a & b;
q = a | b;
r = ~a;
s = a ^ b;
t = ~(a & b);
u = ~(a | b);
v = ~(a ^ b);
end
endmodule
//STRUCTURAL
module logic_structural(
input a,
input b,
output p, q, r, s, t, u, v
);
and (p, a, b);
or (q, a, b);
not (r, a);
xor (s, a, b);
not (t, p);
not (u, q);
not (v, s);
endmodule
HALF ADDER
//DATAFLOW
module half_adder(
input a,
input b,
output sum,
output carry
);
assign sum = a ^ b;
assign carry = a & b;
endmodule
//BEHAVIORAL
module half_adder(
input a,
input b,
output sum,
output carry
);
always @(*) begin
case ({a, b})
2'b00: begin
sum = 0;
carry = 0;
end
2'b01: begin
sum = 1;
carry = 0;
end
2'b10: begin
sum = 1;
carry = 0;
end
2'b11: begin
sum = 0;
carry = 1;
end
endcase
end
endmodule
//STRUCTURAL
module half_adder(
input a,
input b,
output sum,
output carry
);
wire w1, w2;
xor (sum, a, b);
and (carry, a, b);
endmodule
//TESTBENCH
module half_adder_tb;
reg a, b;
wire sum, carry;
half_adder dut (
.a(a),
.b(b),
.sum(sum),
.carry(carry)
);
initial begin
// Test vectors
a = 0; b = 0; #10; $display("[%t] a = %b, b = %b, sum = %b, carry = %b", $time, a, b, sum, carry);
a = 0; b = 1; #10; $display("[%t] a = %b, b = %b, sum = %b, carry = %b", $time, a, b, sum, carry);
a = 1; b = 0; #10; $display("[%t] a = %b, b = %b, sum = %b, carry = %b", $time, a, b, sum, carry);
a = 1; b = 1; #10; $display("[%t] a = %b, b = %b, sum = %b, carry = %b", $time, a, b, sum, carry);
$finish;
end
endmodule––
FULL ADDER
//DATAFLOW
module FullAdder_Dataflow (
input A, B, Cin,
output Sum, Cout
);
assign Sum = A ^ B ^ Cin;
assign Cout = (A & B) | (B & Cin) | (A & Cin);
endmodule
testbench:
module FullAdder_Testbench;
reg A, B, Cin;
wire Sum, Cout;
FullAdder_Dataflow FA (A, B, Cin, Sum, Cout);
initial begin
// Test all input combinations
A = 0; B = 0; Cin = 0; #10;
A = 0; B = 0; Cin = 1; #10;
A = 0; B = 1; Cin = 0; #10;
A = 0; B = 1; Cin = 1; #10;
A = 1; B = 0; Cin = 0; #10;
A = 1; B = 0; Cin = 1; #10;
A = 1; B = 1; Cin = 0; #10;
A = 1; B = 1; Cin = 1; #10;
$finish;
end
endmodule
Full adder using 2 half adders:
module FullAdder_Using_HalfAdder (
input A, B, Cin,
output Sum, Cout
);
wire Sum1, Carry1, Carry2;
halfadder_struct HA1 (A,B,Sum1,Carry1);
halfadder_struct HA2 (Cin,Sum1,Sum,Carry2);
assign Cout = Carry1 | Carry2;
endmodule
TESTBENCH:
module FullAdder_Using_HalfAdder_Testbench;
reg A, B, Cin;
wire Sum, Cout;
FullAdder_Using_HalfAdder FA (
.A(A),
.B(B),
.Cin(Cin),
.Sum(Sum),
.Cout(Cout)
);
initial begin
A = 0; B = 0; Cin = 0; #10;
A = 0; B = 0; Cin = 1; #10;
A = 0; B = 1; Cin = 0; #10;
A = 0; B = 1; Cin = 1; #10;
A = 1; B = 0; Cin = 0; #10;
A = 1; B = 0; Cin = 1; #10;
A = 1; B = 1; Cin = 0; #10;
A = 1; B = 1; Cin = 1; #10;
$finish;
end
endmodule
HALF SUBTRACTOR:
//STRUCTURAL
module HalfSubtractor_Structural (input A, B, output Diff, Bout);
wire notA;
xor (Diff, A, B);
not (notA, A);
and (Bout, notA, B);
endmodule
//BEHAVIORAL
module HalfSubtractor_Behavioral (input A, B, output reg Diff, Bout);
always @(*) begin
Diff = A ^ B;
Bout = ~A & B;
end
endmodule
//DATAFLOW
module HalfSubtractor_Dataflow (input A, B, output Diff, Bout);
assign Diff = A ^ B;
assign Bout = ~A & B;
endmodule
TESTBENCH:
module HalfSubtractor_Testbench;
reg A, B;
wire Diff, Bout;
HalfSubtractor_Structural HS (A, B, Diff, Bout);
// HalfSubtractor_Behavioral HS (A, B, Diff, Bout);
// HalfSubtractor_Dataflow HS (A, B, Diff, Bout);
initial begin
A = 0; B = 0; #10;
A = 0; B = 1; #10;
A = 1; B = 0; #10;
A = 1; B = 1; #10;
$finish;
end
endmodule
FULL SUBTRACTOR:
//STRUCTURAL
module FullSubtractor_Structural (input A, B, Bin, output Diff, Bout);
wire w1, w2, w3, w4;
xor (w1, A, B);
xor (Diff, w1, Bin);
not (w2, A);
and (w3, w2, B);
and (w4, w1, Bin);
or (Bout, w3, w4);
endmodule
//BEHAVIORAL
module FullSubtractor_Behavioral (input A, B, Bin, output reg Diff, Bout);
always @(*) begin
Diff = A ^ B ^ Bin;
Bout = (~A & B) | ((~A | B) & Bin);
end
endmodule
//DATAFLOW
module FullSubtractor_Dataflow (input A, B, Bin, output Diff, Bout);
assign Diff = A ^ B ^ Bin;
assign Bout = (~A & B) | ((~A | B) & Bin);
endmodule
TESTBENCH:
module FullSubtractor_Testbench;
reg A, B, Bin;
wire Diff, Bout;
FullSubtractor_Structural FS (A, B, Bin, Diff, Bout);
// FullSubtractor_Behavioral FS (A, B, Bin, Diff, Bout);
// FullSubtractor_Dataflow FS (A, B, Bin, Diff, Bout);
initial begin
A = 0; B = 0; Bin = 0; #10;
A = 0; B = 0; Bin = 1; #10;
A = 0; B = 1; Bin = 0; #10;
A = 0; B = 1; Bin = 1; #10;
A = 1; B = 0; Bin = 0; #10;
A = 1; B = 0; Bin = 1; #10;
A = 1; B = 1; Bin = 0; #10;
A = 1; B = 1; Bin = 1; #10;
$finish;
end
endmodule
//FULL ADDER MODULE
module FullAdder (input A, B, Cin, output Sum, Cout);
wire w1, w2, w3;
xor (w1, A, B);
xor (Sum, w1, Cin);
and (w2, A, B);
and (w3, w1, Cin);
or (Cout, w2, w3);
endmodule
//STRUCTURAL
module AdderSubtractor_4bit (input [3:0] A, B, input Mode, output [3:0] S, output C);
wire x0, x1, x2, x3;
wire c1,c2,c3,c4;
xor (x0, B[0], Mode);
xor (x1, B[1], Mode);
xor (x2, B[2], Mode);
xor (x3, B[3], Mode);
FullAdder_Using_HalfAdder FA0 (A[0], x0, Mode, S[0], c1);
FullAdder_Using_HalfAdder FA1 (A[1], x1, c1, S[1], c2);
FullAdder_Using_HalfAdder FA2 (A[2], x2, c2, S[2], c3);
FullAdder_Using_HalfAdder FA3 (A[3], x3, c3, S[3], C);
Endmodule
TESTBENCH:
module AdderSubtractor_4bit_Testbench;
reg [3:0] A, B;
reg Mode;
wire [3:0] S;
wire C;
AdderSubtractor_4bit UUT (A, B, Mode, S, C);
initial begin
A = 4'b0000; B = 4'b0000; Mode = 0; #10;
A = 4'b0001; B = 4'b0001; Mode = 0; #10;
A = 4'b0011; B = 4'b0001; Mode = 0; #10;
A = 4'b0110; B = 4'b0011; Mode = 0; #10;
A = 4'b0000; B = 4'b0000; Mode = 1; #10;
A = 4'b0001; B = 4'b0001; Mode = 1; #10;
A = 4'b0110; B = 4'b0011; Mode = 1; #10;
A = 4'b1001; B = 4'b0100; Mode = 1; #10;
$finish;
end
endmodule
MULTIPLEXERS
//2X1 MUX DATAFLOW
module mux2x1_dataflow (
input wire a, b,
input wire sel,
output wire y
);
assign y = sel ? b : a;
endmodule
//2X1 MUX BEHAVIORAL
module mux2x1_behavioral (
input wire a, b,
input wire sel,
output reg y
);
always @(*) begin
if (sel)
y = b;
else
y = a;
end
endmodule
//2X1 MUX STRUCTURAL
module mux2x1_structural (
input wire a, b,
input wire sel,
output wire y
);
wire sel_n, and1_out, and2_out;
not (sel_n, sel);
and (and1_out, a, sel_n);
and (and2_out, b, sel);
or (y, and1_out, and2_out);
endmodule
//TESTBENCH
//4X1 DATAFLOW
module mux4x1_dataflow (
input wire a, b, c, d,
input wire [1:0] sel,
output wire y
);
assign y = (sel == 2'b00) ? a :
(sel == 2'b01) ? b :
(sel == 2'b10) ? c : d;
Endmodule
//TESTBENCH
module mux4x1_tb;
reg a, b, c, d;
reg [1:0] sel;
wire y;
mux4x1_dataflow dut(
.a(a),
.b(b),
.c(c),
.d(d),
.sel(sel),
.y(y)
);
initial
begin
a = 0; b = 0; c = 0; d = 0; sel == 2'b00; #10;
a = 1; b = 1; c = 0; d = 0; sel == 2'b01; #10;
a = 1; b = 1; c = 0; d = 1; sel == 2'b10; #10;
a = 0; b = 0; c = 0; d = 1; sel == 2'b11; #10;
$finish;
end
endmodule
//4X1 BEHAVIORAL
module mux4x1_behavioral (
input wire a,b,c,d,
input wire [1:0] sel,
output reg y
);
always @(*) begin
case (sel)
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
2'b11: y = d;
default: y = 1'b0;
endcase
end
endmodule
//4X1 STRUCTURAL
module mux4x1_2x1(
output Y, input A, input B, input C, input D, input Sel0, input Sel1);
wire X1, X2;
mux2x1_dataflow M1(A,B,Sel0,X1);
mux2x1_dataflow M2(C,D,Sel0,X2);
mux2x1_dataflow M3(X1,X2,Sel1,Y);
endmodule
//8X1 DATAFLOW
module mux8x1_dataflow(output y, input [7:0] d, input [2:0] s);
assign y = (s == 3'b000) ? d[0] :
(s == 3'b001) ? d[1] :
(s == 3'b010) ? d[2] :
(s == 3'b011) ? d[3] :
(s == 3'b100) ? d[4] :
(s == 3'b101) ? d[5] :
(s == 3'b110) ? d[6] :
d[7];
endmodule
//8X1 BEHAVIORAL
module mux8x1(output reg y, input [7:0] d, input [2:0] s);
always @(*) begin
case(s)
3'b000: y = d[0];
3'b001: y = d[1];
3'b010: y = d[2];
3'b011: y = d[3];
3'b100: y = d[4];
3'b101: y = d[5];
3'b110: y = d[6];
3'b111: y = d[7];
endcase
end
endmodule
//8X1 STRUCTURAL
module mux2x1(output Y, input I0, I1, S);
assign Y = S ? I1 : I0;
endmodule
module mux4x1(output Y, input [3:0] I, input [1:0] S);
wire Y0, Y1;
mux2x1 m1(Y0, I[0], I[1], S[0]);
mux2x1 m2(Y1, I[2], I[3], S[0]);
mux2x1 m3(Y, Y0, Y1, S[1]);
endmodule
module mux8x1(output Y, input [7:0] I, input [2:0] S);
wire Y0, Y1;
mux4x1 m1(Y0, I[3:0], S[1:0]);
mux4x1 m2(Y1, I[7:4], S[1:0]);
mux2x1 m3(Y, Y0, Y1, S[2]);
endmodule
//and gate
module and_using_mux(output reg Y, input A, B);
always @(*)
begin
case (A)
1'b0: Y = 1'b0;
1'b1: Y = B;
endcase
end
endmodule
//OR Gate
module or_using_mux(output reg Y, input A, B);
always @(*)
begin
case (A)
1'b1: Y = 1'b1;
1'b0: Y = B;
endcase
end
endmodule
//XOR Gate
module xor_using_mux(output reg Y, input A, B);
always @(*)
begin
case (A)
1'b1: Y = ~B;
1'b0: Y = B;
endcase
end
endmodule
//NAND Gate
module nand_using_mux(output reg Y, input A, B);
always @(*)
begin
case (A)
1'b1: Y = ~B;
1'b0: Y = 1;
endcase
end
endmodule
//NOR Gate
module nor_using_mux(output reg Y, input A, B);
always @(*)
begin
case (A)
1'b0: Y = ~B;
1'b1: Y = 0;
endcase
end
endmodule
//NOT GATE
module not_using_mux(output reg Y, input A);
always @(*)
begin
case (A)
1'b0: Y = 1; 08816234506
1'b1: Y = 0;
endcase
end
endmodule
//FULL ADDER USING 4X1 MUX (select lines are chosen as X and Y)
Full Adder Implementation using 4 to 1 Multiplexer: Designing and Circuit
module fadd_mux(
input x,
input y,
input z,
output reg s, c
);
always @(*) begin
case ({x, y})
2'b00: begin s = z; c = 0; end
2'b01: begin s = ~z; c = z; end
2'b10: begin s = ~z; c = z; end
2'b11: begin s = z; c = 1; end
default: begin s = 0; c = 0; end
endcase
end
endmodule
//TESTBENCH
module fadd_mux_tb;
reg x, y, z;
wire s, c;
fadd_mux uut (
.x(x),
.y(y),
.z(z),
.s(s),
.c(c)
);
initial begin
x = 0; y = 0; z = 0; #10;
x = 0; y = 0; z = 1; #10;
x = 0; y = 1; z = 0; #10;
x = 0; y = 1; z = 1; #10;
x = 1; y = 0; z = 0; #10;
x = 1; y = 0; z = 1; #10;
x = 1; y = 1; z = 0; #10;
x = 1; y = 1; z = 1; #10;
$finish;
end
endmodule
//FULL ADDER USING 2X1 MUX( select line is chosen as Z)
module fadd_mux2x1(
input x,
input y,
input z,
output reg s, c
);
always @(*) begin
case ({z})
2'b0: begin s = (x^y);
c = xy; end
2'b1: begin s = ~(x^y);
c = (x+y); end
default: begin s = 0; c = 0; end
endcase
end
endmodule
// TESTBENCH
module fadd_mux2x1_tb;
reg x, y, z;
wire s, c;
fadd_mux2x1 uut (
.x(x),
.y(y),
.z(z),
.s(s),
.c(c)
);
initial begin
x = 0; y = 0; z = 0; #10;
x = 0; y = 0; z = 1; #10;
x = 0; y = 1; z = 0; #10;
x = 0; y = 1; z = 1; #10;
x = 1; y = 0; z = 0; #10;
x = 1; y = 0; z = 1; #10;
x = 1; y = 1; z = 0; #10;
x = 1; y = 1; z = 1; #10;
$finish;
end
endmodule
//JK FLIP FLOP
module JK_FF (
input J, K, clk,
output reg Q, Qbar
);
always @(posedge clk) begin
case ({J, K})
2'b00: Q <= Q;
2'b01: Q <= 0;
2'b10: Q <= 1;
2'b11: Q <= ~Q;
endcase
Qbar <= ~Q;
end
endmodule
//SR FLIP FLOP
module SR_FF (
input S, R, clk,
output reg Q, Qbar
);
always @(posedge clk) begin
case ({S, R})
2'b00: Q <= Q;
2'b01: Q <= 0;
2'b10: Q <= 1;
2'b11: Q <= 1'bx;
endcase
Qbar <= ~Q
//T FLIP FLOP
module T_FF (
input T, clk,
output reg Q, Qbar
);
always @(posedge clk) begin
case (T)
1'b0: Q <= Q;
1'b1: Q <= ~Q;
endcase
Qbar <= ~Q;
end
endmodule
//D FLIP FLOP
module D_FF (
input D, clk,
output reg Q, Qbar
);
always @(posedge clk) begin
case (D)
1'b0: Q <= 0;
1'b1: Q <= 1;
endcase
Qbar <= ~Q;
end
endmodule
// 2 TO 4 DECODER (Nor)( Active-High Output)
E A B D3 D2 D1 D0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
0 X X 1 1 1 1
module Decoder_2to4_NOR(
input wire A, B, Enable,
output reg D0, D1, D2, D3
);
always @(*) begin
if (Enable) begin
if (A == 0 && B == 0)
{D3, D2, D1, D0} = ~4'b1110;
else if (A == 0 && B == 1)
{D3, D2, D1, D0} = ~4'b1101;
else if (A == 1 && B == 0)
{D3, D2, D1, D0} = ~4'b1011;
else if (A == 1 && B == 1)
{D3, D2, D1, D0} = ~4'b0111;
else
{D3, D2, D1, D0} = ~4'b1111;
end
else begin
{D3, D2, D1, D0} = 4'b1111;
end
end
endmodule
// 2 TO 4 DECODER (NAND)( Active-Low Output)
E A0 A1 D3 D2 D1 D0
1 0 0 1 1 1 0
1 0 1 1 1 0 1
1 1 0 1 0 1 1
1 1 1 0 1 1 1
0 X X 1 1 1 1
module Decoder_2to4_NAND(
input wire A, B, E,
output reg D0, D1, D2, D3
);
always @(*) begin
if (E)
begin
case ({A, B})
2'b00: {D3, D2, D1, D0} = ~4'b0001;
2'b01: {D3, D2, D1, D0} = ~4'b0010;
2'b10: {D3, D2, D1, D0} = ~4'b0100;
2'b11: {D3, D2, D1, D0} = ~4'b1000;
endcase
end
else
{D3, D2, D1, D0} = 4'b1111;
end
endmodule
//TESTBENCH
module dec_nand_tb;
reg A, B, E;
wire D0, D1, D2, D3;
dec_nand uut (
.A(A),
.B(B),
.E(E),
.D0(D0),
.D1(D1),
.D2(D2),
.D3(D3)
);
initial begin
E=1; A = 0; B = 0; #10;
E=1; A = 0; B = 1; #10;
E=1; A = 1; B = 0; #10;
E=1; A = 1; B = 1; #10;
$stop;
end
endmodule
//ENCODER
module encoder_4x2 (
input wire [3:0] D,
output reg [1:0] Y D3 D2 D1 D0 Y1 Y0
); 0 0 0 1 0 0
0 0 1 0 0 1
always @(*) begin 0 1 0 0 1 0
case (D) 1 0 0 0 0 0
4'b0001: Y = 2'b00; X X X X 0 0
4'b0010: Y = 2'b01;
4'b0100: Y = 2'b10;
4'b1000: Y = 2'b11;
default: Y = 2'b00;
endcase
end
endmodule
//TESTBENCH
module encoder_tb;
reg [3:0] D;
wire [1:0] Y;
encoder_4x2 uut (
.D(D),
.Y(Y)
);
initial begin
D = 4'b0001; #10;
D = 4'b0010; #10;
D = 4'b0100; #10;
D = 4'b1000; #10;
$stop;
end
endmodule
//4X2 PRIORITY ENCODER
D3 D2 D1 D0 Y1 Y0 V
0 0 0 1 0 0 1
0 0 1 X 0 1 1
0 1 X X 1 0 1
1 X X X 1 1 1
0 0 0 0 X X 0
module Priority_Encoder (
input wire [3:0] D,
output reg [1:0] Y,
output reg V
);
always @(*) begin
V= 1'b1;
if (D[3]) begin
Y = 2'b11;
end else if (D[2]) begin
Y = 2'b10;
end else if (D[1]) begin
Y = 2'b01;
end else if (D[0]) begin
Y = 2'b00;
end else begin
Y = 2'bXX;
V = 1'b0;
end
end
endmodule
//TESTBENCH
module Priority_Encoder_tb;
reg [3:0] D;
wire [1:0] Y;
wire V;
Priority_Encoder uut (.D(D), .Y(Y), .V(V));
initial begin
D = 4'b0000; #10;
D = 4'b0001; #10;
D = 4'b0010; #10;
D = 4'b0011; #10;
D = 4'b0100; #10;
D = 4'b0101; #10;
D = 4'b0110; #10;
D = 4'b0111; #10;
D = 4'b1000; #10;
D = 4'b1001; #10;
D = 4'b1010; #10;
D = 4'b1011; #10;
D = 4'b1100; #10;
D = 4'b1101; #10;
D = 4'b1110; #10;
D = 4'b1111; #10;
$stop;
end
endmodule
//4 bit BCD counter
module BCD_Counter (
input wire clk, rst, rst clk Q
output reg [3:0] Q ↑ ↑ 0000
); ↓ ↑ 0001
↓ ↑ 0010
always @(posedge clk or posedge rst) begin ↓ ↑ 0011
if (rst) ↓ ↑ 0100
Q <= 4'b0000; ↓ ↑ 0101
else if (Q == 4'b1001) ↓ ↑ 0110
Q <= 4'b0000; ↓ ↑ 0111
else ↓ ↑ 1000
Q <= Q + 1;
↓ ↑ 1001
end
↓ ↑ 0000
endmodule
//TESTBENCH
module BCD_Counter_tb;
reg clk, rst;
wire [3:0] Q;
BCD_Counter uut (.clk(clk), .rst(rst), .Q(Q));
always #5 clk = ~clk;
initial begin
clk = 0;
rst = 1; #10;
rst = 0;
#100;
$stop;
end
endmodule
//8-bit ALU
ALU_Sel Operation ALU_Out
000 A+B Sum
001 A-B Difference
010 A&B Bitwise AND
011 A|B Bitwise OR
100 A^B Bitwise XOR
101 ~A Bitwise NOT of A
110 A<<1 Left shift
111 A>>1 Right shift
module ALU_8bit (
input wire [7:0] A, B,
input wire [2:0] ALU_Sel,
output reg [7:0] ALU_Out,
);
always @(*) begin
case (ALU_Sel)
3'b000: ALU_Out = A + B;
3'b001: ALU_Out = A - B;
3'b010: ALU_Out = A & B;
3'b011: ALU_Out = A | B;
3'b100: ALU_Out = A ^ B;
3'b101: ALU_Out = ~A;
3'b110: ALU_Out = A << 1;
3'b111: ALU_Out = A >> 1;
default: ALU_Out = 8'b00000000;
endcase
end
endmodule
//TESTBENCH
module ALU_8bit_tb;
reg [7:0] A, B;
reg [2:0] ALU_Sel;
wire [7:0] ALU_Out;
ALU_8bit uut (.A(A), .B(B), .ALU_Sel(ALU_Sel), .ALU_Out(ALU_Out));
initial begin
A = 8'b00001111; B = 8'b00000011;
ALU_Sel = 3'b000; #10;
ALU_Sel = 3'b001; #10;
ALU_Sel = 3'b010; #10;
ALU_Sel = 3'b011; #10;
ALU_Sel = 3'b100; #10;
ALU_Sel = 3'b101; #10;
ALU_Sel = 3'b110; #10;
ALU_Sel = 3'b111; #10;
$stop;
end
endmodule
// 1011 SEQUENCE DETECTOR
module Sequence_Detector (
input wire clk, rst, in_bit,
output reg detected
);
reg [1:0] state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
always @(posedge clk or posedge rst) begin
if (rst)
state <= S0;
else
state <= next_state;
end
always @(*) begin
case (state)
S0: next_state = (in_bit) ? S1 : S0;
S1: next_state = (in_bit) ? S1 : S2;
S2: next_state = (in_bit) ? S3 : S0;
S3: next_state = (in_bit) ? S1 : S0;
default: next_state = S0;
endcase
end
always @(posedge clk) begin
detected <= (state == S3 && in_bit);
end
endmodule
//TESTBENCH
module Sequence_Detector_tb;
reg clk, rst, in_bit;
wire detected;
Sequence_Detector uut (.clk(clk), .rst(rst), .in_bit(in_bit), .detected(detected));
always #5 clk = ~clk;
initial begin
clk = 0; rst = 1; in_bit = 0; #10;
rst = 0;
in_bit = 0; #10;
in_bit = 1; #10;
in_bit = 0; #10;
in_bit = 1; #10;
in_bit = 0; #10;
in_bit = 1; #10;
in_bit = 0; #10;
in_bit = 1; #10;
in_bit = 0; #10;
in_bit = 1; #10;
in_bit = 0; #10;
in_bit = 1; #10;
$stop;
end
endmodule
// 0101 SEQUENCE DETECTOR
module Sequence_Detector (
input wire clk, rst, in_bit,
output reg detected
);
reg [1:0] state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
always @(posedge clk or posedge rst) begin
if (rst)
state <= S0;
else
state <= next_state;
end
always @(*) begin
case (state)
S0: next_state = (in_bit) ? S0 : S1;
S1: next_state = (in_bit) ? S2 : S1;
S2: next_state = (in_bit) ? S0 : S3;
S3: next_state = (in_bit) ? S2 : S1;
default: next_state = S0;
endcase
end
always @(posedge clk) begin
detected <= (state == S3 && in_bit);
end
endmodule
//TESTBENCH
module Sequence_Detector_tb;
reg clk, rst, in_bit;
wire detected;
Sequence_Detector uut (.clk(clk), .rst(rst), .in_bit(in_bit), .detected(detected));
always #5 clk = ~clk;
initial begin
clk = 0; rst = 1; in_bit = 0; #10;
rst = 0;
in_bit = 0; #10;
in_bit = 1; #10;
in_bit = 0; #10;
in_bit = 1; #10;
in_bit = 0; #10;
in_bit = 1; #10;
in_bit = 0; #10;
in_bit = 1; #10;
$stop;
end
endmodule
