MICROPROCESSORS AND MICROCONTROLLERS

Microprocessor Microcontroller

Arithmetic and logic

ALU Timer/ IO Ports
unit
Counter
Accumulator
Accumulator Interrupt
Registers

Internal Circuits
Working Registers
Internal RAM ROM
Program Counter Stack Pointer Stack Pointer Clock

Clock Circuit Interrupt circuit Program Counter

Block diagram of microprocessor Block diagram of microcontroller

Microprocessor contains ALU, General purpose Microcontroller contains the circuitry of

registers, stack pointer, program counter, clock microprocessor, and in addition it has built in
timing circuit, interrupt circuit ROM, RAM, I/O Devices, Timers/Counters etc.

It has many instructions to move data between It has few instructions to move data between
memory and CPU memory and CPU

Few bit handling instruction It has many bit handling instructions

Less number of pins are multifunctional More number of pins are multifunctional

Single memory map for data and code Separate memory map for data and code
(program) (program)

Access time for memory and IO are more Less access time for built in memory and IO.

Microprocessor based system requires It requires less additional hardwares

additional hardware

More flexible in the design point of view Less flexible since the additional circuits which is
residing inside the microcontroller is fixed for a
particular microcontroller

Large number of instructions with flexible Limited number of instructions with few
addressing modes addressing modes
RISC AND CISC CPU ARCHITECTURES
Microcontrollers with small instruction set are called reduced instruction set computer (RISC)
machines and those with complex instruction set are called complex instruction set computer
(CISC). Intel 8051 is an example of CISC machine whereas microchip PIC 18F87X is an example of
RISC machine.

RISC CISC

Instruction takes one or two cycles Instruction takes multiple cycles

Only load/store instructions are used to access In additions to load and store instructions,
memory memory access is possible with other
instructions also.

Instructions executed by hardware Instructions executed by the micro program

Fixed format instruction Variable format instructions

Few addressing modes Many addressing modes

Few instructions Complex instruction set

Most of the have multiple register banks Single register bank

Highly pipelined Less pipelined

Complexity is in the compiler Complexity in the microprogram

HARVARD & VON- NEUMANN CPU ARCHITECTURE

Von-Neumann (Princeton architecture) Harvard architecture

Program Data Data

Data
Memory Memory
CPU CPU Address Bus

Data Data Program

Memory Memory
Address Bus
Address Bus

Von-Neumann (Princeton architecture) Harvard architecture

It uses single memory space for both It has separate program memory and data
instructions and data. memory

It is not possible to fetch instruction code and Instruction code and data can be fetched
data simultaneously
Execution of instruction takes more machine Execution of instruction takes less machine
cycle cycle

Uses CISC architecture Uses RISC architecture

Instruction pre-fetching is a main feature Instruction parallelism is a main feature

Also known as control flow or control driven Also known as data flow or data driven
computers computers

Simplifies the chip design because of single Chip design is complex due to separate memory
memory space space

Eg. 8085, 8086, MC6800 Eg. General purpose microcontrollers, special

DSP chips etc.
 Salient features of 8051 microcontroller are given below.
 Eight bit CPU
 On chip clock oscillator
 4Kbytes of internal program memory (code memory) [ROM]
 128 bytes of internal data memory [RAM]
 64 Kbytes of external program memory address space.
 64 Kbytes of external data memory address space.
 32 bi directional I/O lines (can be used as four 8 bit ports or 32
individually addressable I/O lines)
 Two 16 Bit Timer/Counter :T0, T1
 Full Duplex serial data receiver/transmitter
 Four Register banks with 8 registers in each bank.
 Sixteen bit Program counter (PC) and a data pointer (DPTR)
 8 Bit Program Status Word (PSW)
 8 Bit Stack Pointer
 Five vector interrupt structure (RESET not considered as an interrupt.)
 8051 CPU consists of 8 bit ALU with associated registers like
accumulator ‘A’ , B register, PSW, SP, 16 bit program counter, stack
pointer.
 ALU can perform arithmetic and logic functions on 8 bit variables.
 8051 has 128 bytes of internal RAM which is divided into
o Working registers [00 – 1F]
o Bit addressable memory area [20 – 2F]
o General purpose memory area (Scratch pad memory) [30-7F]
Intel 8051 Architecture
It consists of a Central Processing Unit, two kinds of memory (data RAM plus program
ROM/EPROM) Input/Output ports, the mode status, and data registers and random logic needed for
a variety of peripheral functions. These elements communicate through an eight bit data bus which
runs throughout the chip referred as internal data bus. This bus is buffered to the outside world
through an I/O port when memory or I/O expansion is desired.
Central Processing Unit (CPU):

The CPU of 8051 Architecture consists of eight-bit Arithmetic and Logic unit with associated
registers like A, B, PSW, SP, the sixteen bit program counter and “Data pointer” (DPTR)
registers.

ALU:

The 8051’s ALU can perform arithmetic and logic functions on eight bit variables. The
arithmetic unit can perform addition, subtraction, multiplication and division. The logic unit can
perform logical operations such as AND, OR, and Exclusive-OR, as well as rotate, clear, and
complement. The ALU also looks after the branching ‘decisions. An important and unique
feature of the Intel 8051 Architecture and 8031 Architecture is that the ALU can also manipulate
one bit as well as eight-bit data types. Individual bits may be set, cleared, complemented, moved,
tested, and used in logic computation.

Accumulator:

It is an 8-bit register. It holds a source operand and receives the result of the arithmetic
instructions (addition, subtraction, multiplication, and division). The accumulator can be the
source or destination for logical operations and a number of special data movement instructions,
including look-up tables and external RAM expansion. Several functions apply exclusively to the
accumulator : rotate, parity computation, testing for zero, and so on.

In addition to accumulator, an 8-bit B-register is available as a general purpose register when it is

not being used for the hardware multiply/divide operation.

Program Status Word:

Many instructions implicitly or explicitly affect (or are affected by) several status flags, which
are grouped together to form the Program Status Word. Fig. 12.3 shows the bit pattern of the
program status word. It is an 8-bit word, containing the information as follows.
Other CPU Registers:

Stack Pointer :

The stack pointer register is 8 bit wide. It is incremented before data is stored during PUSH and
ALL instructions. The stack array can reside anywhere in on-chip RAM. The stack pointer is
initialized to 07H after a reset. This causes the stack to begin at location 08H.

Data Pointer (DPTR) :

The data pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its function is to
hold a 16 bit address. It may be manipulated as a 16 bit data register or as two independent 8 bit
registers. It serves as a base register in indirect jumps, lookup table instructions and external data
transfer.

Memory Structure of 8051:

Fig: 12.4 shows the basic memory structure for 8051. It can access upto 64 K program memory
and 64 K data memory. The 8051 has 4 Kbytes of internal program memory and 256 bytes of
internal data memory.
Each memory type has different addressing mechanism, different control signals, and a
differennt function. Each may be added independently, and each uses the same address and data
buses, but with different control signals.

Program Memory of 8051 :

Fig. 12.5 shows a map of Program Memory of 8051.

In 8051, when the EA pin is connected to Vcc, program fetches to addresses 0000H through OFFFH
are directed to the internal ROM and program fetches to addresses 1000H through FFFFH are
directed to external ROM/EPROM. On the other hand when EA pin is grounded, all addresses
(0000H to FFFFH) fetched by program are directed to the external ROM/EPROM. The PSEN signal is
used to activate output enable signal of the external ROM/EPROM , as shown in the Fig. 12.6.

As shown in the Fig. 12.6, the port 0 is used as a multiplexed address/data bus. It gives lower order
8-bit address in the initial T-cycle and later it is used as a data bus.The 8-bit address is latched using
external latch and ALE signal generated by Intel 8051 Architecture and 8031 Architecture. The port
2 provides the higher order 8-bit address.

Memory Organisation of 8051:

Fig. 12.9 shows a map of Data Memory Organisation of 8051

The 8051 can address upto 64 Kbytes of external data memory. The “MOVX” instruction is used
to access the external data memory. The internal data memory space for Intel 8051 Architecture
and 8031 Architecture is divided into three blocks : Lower 128 bytes, Upper 128 bytes and SFRs.
The upper addresses and SFRs occupy the same block of address space, 80H through FFH,
although they are physically separate entities. As shown in the Fig. 12.9, the upper address space
is accessible by indirect addressing only and SFRs are accessible by direct addressing only. On
the other hand, lower address space can be accessed either by direct addressing or by indirect
addressing.

Fig. 12.10 shows the circuit diagram for connecting external data memory. The multiplexed
address/data bus provided by port 0 is demultiplexed by external latch and ALE signal. Port 2
gives the higher order address bus. The RD and WR signals from 8051 selects the memory read
and memory write operation, respectively.
Special Function Register:

Unlike other microprocessors in the Intel family, 8051 uses memory mapped I/O through a set of
special function registers that are implemented in the address space immediately above the 128
bytes of RAM. Fig. 12.12 shows special function bit addresses. All access to the four I/O ports,
the CPU registers, interrupt-control registers, the timer/counter, UART, and power control are
performed through registers between 80H and FFH.
RAM:

It consists of 4 register banks and 144 general purpose bits forming boolean processor RAM.
Fig. 12.12 shows RAM bit addresses. The register bank-select bits refer to four 8 byte regions at
the bottom of memory. Certain instructions can access these registers in RAM directly with 1
byte instructions, since 3 bits of the instruction specify the desired register. The RSO and RS1
bits in PSW must be set to the appropriate bank before execution of the instruction. This method
of addressing saves one byte per instruction. The 144 general purpose bits can be used as
software flags or program variables.

Input/Output Ports:

The MCS-51 family I/O port structure is extremely versatile. The 8051 has 32 I/0 pins
configured as four eight-bit parallel ports ( P0, P1, P2, and P3 ). All four ports are bidirectional,
i.e. each pin will be configured as input or output (or both) under software control. Each port
consists of a latch, an output driver, and an input buffer.

The output drives of Ports 0 and 2 and the input buffers of Port 0, are used in access to external
memory. As mentioned earlier, Port 0 outputs the low order byte of the external memory address,
time multiplexed with the data being written or read, and Port 2 outputs the high order byte of
the external memory address when the address is 16 bits wide. Otherwise Port 2 gives the
contents of special function register P2.

All port pins of Port 3 are multi functional. They have special functions as shown in Fig. 12.13
including two external interrupts, two counter inputs, two special data lines and two timing
control strobes.

8051 Addressing Modes:

The 8051 Addressing Modes architecture supports several distinct physical address spaces.
 1. On – chip program memory
2. On – chip data memory
3. External program memory
4. External data memory
5. On-chip special function registers

The most of the instructions can operate with variables from these physical address spaces.. Now
we will see how to access variables from different physical and logical address spaces with the
help of different Addressing modes.

Register Addressing :

The 8051 can access eight “working registers” (R0—R7). Three bit code within the instruction
selects one of the eight registers from the selected register The programmer can select a register
bank by modifying bits 4 and 3 in the PSW.

Direct Byte Addressing :

Direct addressing can access any on chip variable or hardware register. i.e. on chip RAM and
special function register. The most significant bit of the address decides whether it is a location
within on chip RAM (MSB = 0) or in special function register (MSB = 1).

Register Indirect Addressing :

In this addressing mode R0 and R1 of each register bank can be used as an index or pointer
register. R0 and R1 point to the contents in the.
Immediate Addressing :

In this addressing mode source operand is a constant rather than a variable. So the constant can
be incorporated in the instruction. Sign “#” indicates it is a immediate addressing mode.

Register Specific :

Inherent in the instruction, these refer to a specific register such as accumulator or DPTR.

Index :

Only program memory can be accessed in the index addressing. Either the DPTR or PC can be
used as an index register.

Pin Diagram of 8051

The pin diagram of 8051 microcontroller looks as follows −

● Pins 1 to 8 − These pins are known as Port 1. This port doesn’t serve any other functions. It is
internally pulled up, bi-directional I/O port.

● Pin 9 − It is a RESET pin, which is used to reset the microcontroller to its initial values.

● Pins 10 to 17 − These pins are known as Port 3. This port serves some functions like interrupts,
timer input, control signals, serial communication signals RxD and TxD, etc.

● Pins 18 & 19 − These pins are used for interfacing an external crystal to get the system clock.

● Pin 20 − This pin provides the power supply to the circuit.

● Pins 21 to 28 − These pins are known as Port 2. It serves as I/O port. Higher order address bus
signals are also multiplexed using this port.

● Pin 29 − This is PSEN pin which stands for Program Store Enable. It is used to read a signal
from the external program memory.

● Pin 30 − This is EA pin which stands for External Access input. It is used to enable/disable the
external memory interfacing.
● Pin 31 − This is ALE pin which stands for Address Latch Enable. It is used to demultiplex the
address-data signal of port.

● Pins 32 to 39 − These pins are known as Port 0. It serves as I/O port. Lower order address and
data bus signals are multiplexed using this port.

● Pin 40 − This pin is used to provide power supply to the circuit.

8051 microcontrollers have 4 I/O ports each of 8-bit, which can be configured as input or output.
Hence, total 32 input/output pins allow the microcontroller to be connected with the peripheral
devices.

● Pin configuration, i.e. the pin can be configured as 1 for input and 0 for output as per the logic
state. Input/Output (I/O) pin − All the circuits within the microcontroller must be connected to
one of its pins except P0 port because it does not have pull-up resistors built-in.

Input pin − Logic 1 is applied to a bit of the P register. The output FE transistor is turned off and
the other pin remains connected to the power supply voltage over a pull-up resistor of high
resistance.

● Port 0 − The P0 (zero) port is characterized by two functions −

When the external memory is used then the lower address byte (addresses A0A7) is applied on it,
else all bits of this port are configured as input/output. When P0 port is configured as an output
then other ports consisting of pins with built-in pull-up resistor connected by its end to 5V power
supply, the pins of this port have this resistor left out.

● Input Configuration If any pin of this port is configured as an input, then it acts as if it “floats”,
i.e. the input has unlimited input resistance and in-determined potential.

● Output Configuration When the pin is configured as an output, then it acts as an “open drain”.
By applying logic 0 to a port bit, the appropriate pin will be connected to ground (0V), and
applying logic 1, the external output will keep on “floating”.

In order to apply logic 1 (5V) on this output pin, it is necessary to build an external pullup
resistor.

Port 1 P1 is a true I/O port as it doesn’t have any alternative functions as in P0, but this port can
be configured as general I/O only. It has a built-in pull-up resistor and is completely compatible
with TTL circuits.

Port 2 P2 is similar to P0 when the external memory is used. Pins of this port occupy addresses
intended for the external memory chip. This port can be used for higher address byte with
addresses A8-A15. When no memory is added then this port can be used as a general
input/output port similar to Port 1.
Port 3 In this port, functions are similar to other ports except that the logic 1 must be applied to
appropriate bit of the P3 register.

Pins Current Limitations ● When pins are configured as an output (i.e. logic 0), then the single
port pins can receive a current of 10mA.

● When these pins are configured as inputs (i.e. logic 1), then built-in pull-up resistors provide
very weak current, but can activate up to 4 TTL inputs of LS series.

● If all 8 bits of a port are active, then the total current must be limited to 15mA (port P0:
26mA).

● If all ports (32 bits) are active, then the total maximum current must be limited to 71mA.

Data transfer instructions

1. MOV < dest-byte >, < src-byte >

Function : Move byte variable

Description : The byte variable indicated by the second operand is copied into the location
specified by the first operand. The source byte is not affected. No other register or flag is
affected.

Example :

MOV A, @R0 Moves the content of memory pointed to by Ro into A

MOV A, R1 Moves the content of Register R1 to Accumulator A
MOV 20h, 30h Moves the content of memory location 30h to 20h
MOV A, #45h Moves 45h to Accumulator A

2. MOV < dest-byte >, < src-byte >

Function : Move bit data

Description : MOV < dest-bit >,< src-bit > copies the Boolean variable indicated by the second
operand into the location specified by the first operand. One of the operands must be the carry
flag; the other may be any directly addressable bit. No other register or flag is affected.

Example : MOV P1.3, C - Moves the carry bit to 3rd bit of port1

3. MOV DPTR, #data16

Function : Load Data Pointer with a 16-bit constant

Description : MOV DPTR, v#data16 loads the Data Pointer with the 16-bit constant indicated.
The 16-bit constant is loaded into the second and third bytes of the instruction. The second byte
(DPH) is the high-order byte, while the third byte (DPL) holds the lower-order byte. No flags are
affected. This is the only instruction which moves 16 bits of data at once

Example : MOV DPTR, # 4567H - loads the value 4567H into the Data Pointer. DPH holds
45H, and DPL holds 67H.

4. MOVC A,@A+ < base-reg >

Function : Move Code byte

Description : The MOVC instructions load the Accumulator with a code byte or constant from
program memory. The address of the byte fetched is the sum of the original unsigned 8-bit
Accumulator contents and the contents of a 16-bit base register, which may be either the Data
Pointer or the PC. In the latter case, the PC is incremented to the address of the following
instruction before being added with the Accumulator; otherwise the base register is not altered.
Sixteen-bit addition is performed so a carryout from the low-order eight bits may propagate
through higher-order bits. No flags are affected.

5. MOVC A,@A+PC

6. MOVX < dest-byte >, < src-byte >

Function : Move External

Description : The MOVX instructions transfer data between the Accumulator and a byte of
external data memory, which is why “X” is appended to MOV. There are two types of
instructions, differing in whether they provide an 8-bit or 16-bit indirect address to the external
data RAM.

In the first type, the contents of R0 or R1 in the current register bank provide an 8-bit address
multiplexed with data on P0. Eight bits are sufficient for external I/O expansion decoding or for
a relatively small RAM array. For somewhat larger arrays, any output port pins can be used to
output higher-order address bits. These pins are controlled by an output instruction preceding the
MOVX.

In the second type of MOVX instruction, the Data Pointer generates a 16-bit address. P2 outputs
the high-order eight address bits (the contents of DPH), while P0 multiplexes the low-order eight
bits (DPL) with data. The P2 Special Function Register retains its previous contents, while the
P2 output buffers emit the contents of DPH.
This form of MOVX is faster and more efficient when accessing very large data arrays (up to
64K bytes), since no additional instructions are needed to set up the output ports. It is possible to
use both MOVX types in some situations. A large RAM array with its high-order address lines
driven by P2 can be addressed via the Data Pointer, or with code to output high-order address
bits to P2, followed by a MOVX instruction using R0 or R1.

Example : An external 256 byte RAM using multiplexed address/data lines is connected to the
8051 Port 0. Port 3 provides control lines for the external RAM. Ports 1 and 2 are used for
normal I/O. Registers 0 and 1 contain 12H and 34H. Location 34H of the external RAM holds
the value 56H. The instruction sequence,

MOVX A,@R1

MOVX @R0, A

copies the value 56H into both the Accumulator and external RAM location 12H.

7. PUSH direct

Function : Push onto stack

Description : The Stack Pointer is incremented by one. The contents of the indicated variable is
then copied into the internal RAM location addressed by the Stack Pointer. No flags are affected.

Example: On entering an interrupt routine, the Stack Pointer contains 09H. The Data Pointer
holds the value 0123H. The following instruction sequence,

PUSH DPL

PUSH DPH

leaves the Stack Pointer set to 0BH and stores 23H and 01H in internal RAM locations 0AH and
0BH, respectively.

8. POP direct

Function: Pop from stack.

Description: The contents of the internal RAM location addressed by the Stack Pointer is read,
and the Stack Pointer is decremented by one. The value read is then transferred to the directly
addressed byte indicated. No flags are affected.

Example: The Stack Pointer originally contains the value 32H, and internal RAM locations 30H
through 32H contain the values 20H, 23H, and 01H, respectively. The following instruction
sequence,
POP DPH

POP DPL

leaves the Stack Pointer equal to the value 30H and sets the Data Pointer to 0123H.

9. Arithmetic group of instructions

ADD A,< src-byte >

Function: Add

Description : ADD adds the byte variable indicated to the Accumulator, leaving the result in the
Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from
bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an
overflow occurred. OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of
bit 7 but not bit 6; otherwise, OV is cleared. When adding signed integers, OV indicates a
negative number produced as the sum of two positive operands, or a positive sum from two
negative operands. Four source operand addressing modes are allowed: register, direct, register-
indirect, or immediate.

Example : The Accumulator holds 0C3H (1100001lB), and register 0 holds 0AAH
(10101010B). The following instruction, ADD A,R0 leaves 6DH (01101101B) in the
Accumulator with the AC flag cleared and both the carry flag and OV set to 1.

10. ADDC A, < src-byte >

Function : Add with Carry

Description : ADDC simultaneously adds the byte variable indicated, the carry flag and the
Accumulator contents, leaving the result in the Accumulator. The carry and auxiliary carry flags
are set respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When
adding unsigned integers, the carry flag indicates an overflow occurred. OV is set if there is a
carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of bit 6; otherwise OV is
cleared. When adding signed integers, OV indicates a negative number produced as the sum of
two positive operands or a positive sum from two negative operands. Four source operand
addressing modes are allowed: register, direct, register-indirect, or immediate.

Example : The Accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B)
with the carry flag set. The following instruction, ADDC A, R0 leaves 6EH (01101110B) in the
Accumulator with AC cleared and both the Carry flag and OV set to 1.

11. SUBB A,< src-byte >

Function: Subtract with borrow

Description: SUBB subtracts the indicated variable and the carry flag together from the
Accumulator, leaving the result in the Accumulator. SUBB sets the carry (borrow) flag if a
borrow is needed for bit 7 and clears C otherwise. (If C was set before executing a SUBB
instruction, this indicates that a borrow was needed for the previous step in a multiple-precision
subtraction, so the carry is subtracted from the Accumulator along with the source operand.)

AC is set if a borrow is needed for bit 3 and cleared otherwise. OV is set if a borrow is needed
into bit 6, but not into bit 7, or into bit 7, but not bit 6. When subtracting signed integers, OV
indicates a negative number produced when a negative value is subtracted from a positive value,
or a positive result when a positive number is subtracted from a negative number. The source
operand allows four addressing modes: register, direct, register-indirect, or immediate.

Example: The Accumulator holds 0C9H (11001001B), register 2 holds 54H (01010100B), and
the carry flag is set. The instruction, SUBB A,R2 will leave the value 74H (01110100B) in the
accumulator, with the carry flag and AC cleared but OV set.

12. DEC byte

Function: Decrement

Description: DEC byte decrements the variable indicated by 1. An original value of 00H
underflows to 0FFH. No flags are affected.

Example: Register 0 contains 7FH (01111111B). Internal RAM locations 7EH and 7FH contain
00H and 40H, respectively. The following instruction sequence, DEC @R0 DEC R0 DEC @R0

leaves register 0 set to 7EH and internal RAM locations 7EH and 7FH set to 0FFH and 3FH.

13. DIV AB

Function: Divide

Description: DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned
eight-bit integer in register B. The Accumulator receives the integer part of the quotient; register
B receives the integer remainder. The carry and OV flags are cleared.

Exception: if B had originally contained 00H, the values returned in the Accumulator and B-
register are undefined and the overflow flag are set. The carry flag is cleared in any case.

Example: The Accumulator contains 251 (0FBH or 11111011B) and B contains 18 (12H or
00010010B). The following instruction, DIV AB leaves 13 in the Accumulator (0DH or
00001101B) and the value 17 (11H or 00010001B) in B, since 251 = (13 x 18) + 17. Carry and
OV are both cleared.

14. INC <byte>

Function : Increment

Description : INC increments the indicated variable by 1. An original value of 0FFH overflows
to 00H. No flags are affected.

Example : Register 0 contains 7EH (011111110B). Internal RAM locations 7EH and 7FH
contain 0FFH and 40H, respectively. The following instruction sequence, INC @R0 INC R0
INC @R0 leaves register 0 set to 7FH and internal RAM locations 7EH and 7FH holding 00H
and 41H, respectively.

15. INC DPTR

Function : Increment Data Pointer

Description : INC DPTR increments the 16-bit data pointer by 1. A 16-bit increment (modulo
216) is performed, and an overflow of the low-order byte of the data pointer (DPL) from 0FFH
to 00H increments the high-order byte (DPH). No flags are affected.This is the only 16-bit
register which can be incremented.

Example: Registers DPH and DPL contain 12H and 0FEH, respectively. The following
instruction sequence,

INC DPTR

changes DPH and DPL to 13H and 01H.

16. MUL AB

Function : Multiply

Description : MUL AB multiplies the unsigned 8-bit integers in the Accumulator and register B.
The low-order byte of the 16-bit product is left in the Accumulator, and the high-order byte in B.
If the product is greater than 255 (0FFH), the overflow flag is set; otherwise it is cleared. The
carry flag is always cleared.

Example: Originally the Accumulator holds the value 80 (50H). Register B holds the value 160
(0A0H). The instruction, MUL AB will give the product 12,800 (3200H), so B is changed to
32H (00110010B) and the Accumulator is cleared. The overflow flag is set, carry is cleared.

17. DA A

Function: Decimal-adjust Accumulator for Addition

Description: DA A adjusts the eight-bit value in the Accumulator resulting from the earlier
addition of two variables (each in packed-BCD format), producing two four-bit digits. Any ADD
or ADDC instruction may have been used to perform the addition.
If Accumulator bits 3 through 0 are greater than nine or if the AC flag is one, six is added to the
Accumulator producing the proper BCD digit in the low-order nibble. This internal addition sets
the carry flag if a carry-out of the low-order four-bit field propagates through all high-order bits,
but it does not clear the carry flag otherwise. If the carry flag is now set, or if the four high-order
bits now exceed nine, these high order bits are incremented by six, producing the proper BCD
digit in the high-order nibble.

Again, this sets the carry flag if there is a carry-out of the high-order bits, but does not clear the
carry. The carry flag thus indicates if the sum of the original two BCD variables is greater than
100, allowing multiple precision decimal addition. OV is not affected.

Logical instructions

18. ANL < dest-byte >,< src-byte >

Function: Logical-AND for byte variables

Description: ANL performs the bitwise logical-AND operation between the variables indicated
and stores the results in the destination variable. No flags are affected. The two operands allow
six addressing mode combinations. When the destination is the Accumulator, the source can use
register, direct, register-indirect, or immediate addressing; when the destination is a direct
address, the source can be the Accumulator or immediate data.

Example: If the Accumulator holds 0C3H (1100001lB), and register 0 holds 55H (01010101B),
then the following instruction, ANL A,R0 leaves 41H (01000001B) in the Accumulator.

19. ORL < dest-byte > < src-byte >

Function: Logical-OR for byte variables Description: ORL performs the bitwise logical-OR
operation between the indicated variables, storing the results in the destination byte. No flags are
affected.

Example: If the Accumulator holds 0C3H (11000011B) and R0 holds 55H (01010101B) then
the following instruction, ORL A,R0 leaves the Accumulator holding the value 0D7H
(1101011lB).

20. XRL < dest-byte >,< src-byte >

Function: Logical Exclusive-OR for byte variables

Description: XRL performs the bitwise logical Exclusive-OR operation between the indicated
variables, storing the results in the destination. No flags are affected. The two operands allow six
addressing mode combinations. When the destination is the Accumulator, the source can use
register, direct, register-indirect, or immediate addressing; when the destination is a direct
address, the source can be the Accumulator or immediate data.
Example:
If the Accumulator holds 0C3H (1100001lB) and register 0 holds 0AAH (10101010B) then the
instruction, XRL A,R0 leaves the Accumulator holding the value 69H (01101001B).

21. RL A

Function : Rotate Accumulator Left

Description : The eight bits in the Accumulator are rotated one bit to the left. Bit 7 is rotated
into the bit 0 position. No flags are affected.

Example : The Accumulator holds the value 0C5H (11000101B). The following instruction, RL
A leaves the Accumulator holding the value 8BH (10001011B) with the carry unaffected.

22. RLC A

Function : Rotate Accumulator Left through the Carry flag

Description : The eight bits in the Accumulator and the carry flag are together rotated one bit to
the left. Bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0
position. No other flags are affected.

Example : The Accumulator holds the value 0C5H(11000101B), and the carry is zero. The
following instruction, RLC A leaves the Accumulator holding the value 8BH (10001010B) with
the carry set.

23. RRC A

Function: Rotate Accumulator Right through Carry flag

Description: The eight bits in the Accumulator and the carry flag are together rotated one bit to
the right. Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7
position. No other flags are affected.

Example: The Accumulator holds the value 0C5H (11000101B), the carry is zero. The
following instruction, RRC A leaves the Accumulator holding the value 62 (01100010B) with
the carry set.

24. SWAP A

Function : Swap nibbles within the Accumulator

Description: SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the
Accumulator (bits 3 through 0 and bits 7 through 4). The operation can also be thought of as a 4-
bit rotate instruction. No flags are affected.
Example: The Accumulator holds the value 0C5H (11000101B). The instruction, SWAP A
leaves the Accumulator holding the value 5CH (01011100B).

25. CPL A

Function: Complement Accumulator

Description: CPLA logically complements each bit of the Accumulator (one’s complement).
Bits which previously contained a 1 are changed to a 0 and vice-versa. No flags are affected.

Example:

The Accumulator contains 5CH (01011100B).The following instruction, CPL A leaves the
Accumulator set to 0A3H (10100011B).

Jump instructions

26. AJMP

Function: Absolute jump within 2K block

Description: AJMP unconditionally jumps to the indicated code address. The new value for the
Program Counter is calculated by replacing the least-significant-byte of the Program Counter
with the second byte of the AJMP instruction, and replacing bits 0-2 of the most-significant-byte
of the Program Counter with 3 bits that indicate the page of the byte following the AJMP
instruction. Bits 3-7 of the most-significant-byte of the Program Counter remain unchanged.
Since only 11 bits of the Program Counter are affected by AJMP, jumps may only be made to
code located within the same 2k block as the first byte that follows AJMP.

27. LGMP

Function: Long Jump

Syntax: LJMP code address.

Description: LJMP jumps unconditionally to the specified code address.