COMPUTER ARCHITECTURE
LAB3 FCIS Ainshams University
Spring2021
AGENDA
• Sequential code
Process
If statement
• Hands-on 1: D -FF
• Hands-on 2: Generic Building Block of MIPS: n-bit
Flop register
• JK- FF
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SEQUENTIAL CODE
▪ As the VHDL statements are inherently concurrent,
then sequential circuits can not be implemented
directly.
▪ It must be enclosed in sequential block which
guarantees sequential execution .
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SEQUENTIAL CODE
▪ PROCESSES, FUNCTIONS, and PROCEDURES
are the only sections of code that are executed
sequentially.
▪ Any of these blocks is still concurrent with any other
statements placed outside it.
▪ There are statements that allowed only inside
sequential code like IF and CASE statements.
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PROCESS
A PROCESS is executed every time a signal in the
sensitivity list changes
ARCHITECTURE myarch OF myentity IS
BEGIN
...
PROCESS (sensitivity list)
BEGIN
(sequential code)
END PROCESS;
...
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END myarch;
PROCESS
To construct a synchronous circuit, monitoring a signal is
necessary (for example clk)
A common way of detecting a signal change is by means of
the EVENT attribute
IF (clk'EVENT AND clk='1')... -- EVENT attribute
IF (NOT clk'STABLE AND clk='1')…-- STABLE attribute 6
THE IF STATEMENT
IF/ELSE
Creates priority-encoded logic.
ARCHITECTURE myarch OF myentity IS
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst = ‘1’) THEN
...
ELSIF (clk'EVENT AND clk = ‘1’) THEN
...
ELSE
...
END IF;
END PROCESS;
END myarch; 7
D-FLIPFLOP (WITH ASYNCHRONOUS RESET)
Check the usage of if statement and PROCESS to
write D Flip Flop
RST D Clk Q
1 X X 0
0 1 Trig 1
0 0 Trig 0
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HANDS-ON 1: D-FF(WITH ASYNCHRONOUS RESET)
ENTITY DFF IS ARCHITECTURE Behavioral OF DFF IS
PORT ( clk: IN STD_LOGIC; BEGIN
D: IN STD_LOGIC; PROCESS (clk, rst)
rst: IN STD_LOGIC;
BEGIN
Q: OUT STD_LOGIC);
IF (rst = '1') THEN
END DFF;
Q <= '0' ;
ELSIF (clk'EVENT and clk = '1') THEN
Q <= D ;
END IF;
END PROCESS;
END Behavioral;
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TESTING THE DFF
Generate the Test Bench
Check the code, you will see this:
constant clk_period : time := 1us;
This line defines the period of the clock used in simulation
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THE CLK PROCESS
This process gives the clock its square wave form.
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
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THE STIMULUS PROCESS
Use this process to test the flip flop
stim_proc: process
begin
-- hold reset state till before rising edge.
wait for clk_period/2 - 100ns;
d <= ‘1';
wait for clk_period*5;
rst <= ‘1';
wait;
end process; 12
THE INITIAL WAIT
wait for clk_period/2 - 100ns
If the stimulus changes at the same time of the clock,
then the flip flop has no time to read the value and
store it.
So, the 100ns shift is to give time for the signal to
stabilize before the rising edge of the clock.
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SIMULATION TIME
The clock period is 1 us, and we need about 10
clocks to simulate enough test cases.
If we run the simulation, it will only run for 1 us.
To change it, right-click on “Simulate Behavioral
Model”, click on “Process Properties”, and enter
10 us in the “Simulated Run Time” field.
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SIMULATION TIME
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D-FLIPFLOP(WITH SYNCHRONOUS RESET)
Notice the difference when Reset becomes
synchronous
rst D Clk Q
1 X Trig* 0
0 1 Trig 1
0 0 Trig 0
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D-FLIPFLOP(WITH SYNCHRONOUS RESET)
ENTITY DFF IS ARCHITECTURE Behavioral OF DFF IS
PORT ( clk: IN STD_LOGIC; BEGIN
D: IN STD_LOGIC; PROCESS (clk)
rst: IN STD_LOGIC; BEGIN
Q: OUT STD_LOGIC); IF (clk'EVENT and clk = '1’) THEN
END DFF; IF (rst = '1’) THEN
Q <= '0' ;
ELSE
Q <= D ;
END IF;
END IF;
END PROCESS;
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END Behavioral;
FLOP REGISTER
▪An N-bit register is a bank of N flip-flops that share a
common CLK input, so that all bits of the register are
updated at the same time.
▪Registers are the key building block of most sequential
circuits.
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HANDS-ON 2: FLOP REGISTER
(WITH ASYNCHRONOUS RESET)
d q
n bits flopr n bits
clk
reset
• Dynamic assignment statement:
q <= (others => '0’);
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HANDS-ON 2: FLOP REGISTER
(WITH ASYNCHRONOUS RESET)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
entity flopr is
generic (n : NATURAL := 32);
port(clk, reset: in STD_LOGIC;
d: in STD_LOGIC_VECTOR(n-1 downto 0);
q: out STD_LOGIC_VECTOR(n-1 downto 0));
end; 20
HANDS-ON 2: FLOP REGISTER
(WITH ASYNCHRONOUS RESET)
architecture behavioral of flopr is
begin
process(clk, reset)
begin
if reset='1' then q <= (others => '0’);
Elsif rising_edge(clk) then
q <= d;
end if;
end process;
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end;
JK-FF(WITH ASYNCHRONOUS RESET)
rst J K Clk Q Q’
1 X X X 0 1
Trig No Change
0 0 0
Trig
0 0 1 0 1
Trig
0 1 0 1 0
Trig
0 1 1 Toggle
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JK-FF(WITH ASYNCHRONOUS RESET)
ENTITY JK_FF IS
PORT ( clk: IN STD_LOGIC;
J, K: IN STD_LOGIC;
rst: IN STD_LOGIC;
Q, Qbar: OUT STD_LOGIC);
END JK_FF;
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JK-FF(WITH ASYNCHRONOUS RESET)
ARCHITECTURE JK_FFArch OF JK_FF IS
SIGNAL state: STD_LOGIC;
SIGNAL input: STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
input <= J & K; IF (rst='1') THEN
PROCESS (clk, rst) state <= '0';
BEGIN ELSIF (clk'EVENT AND clk = '1') THEN
IF (rst='1') THEN
state <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
CASE (input) IS
CASE (input) IS
WHEN "11" => state <= NOT state; WHEN "11" => state <= NOT
WHEN "10" => state <= '1';
WHEN "01" => state <= '0';
WHEN OTHERS => null;
state;
END IF;
END CASE;
WHEN "10" => state <= '1';
END PROCESS; WHEN "01" => state <= '0';
Q <= state; WHEN OTHERS => null;
Qbar <= NOT state;
END JK_FFArch ; END CASE;
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END IF;
Thanks
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