Allen and Holberg - CMOS Analog Circuit Design Page VII.

0-1

SECTION 7 - COMPARATORS
Allen and Holberg - CMOS Analog Circuit Design Page VII.0-1

VII. COMPARATORS
Contents

VI.1 Comparators Models and Performance

VI.2 Development of a CMOS Comparator
VI.3 Design of a Two-Stage CMOS Comparator
VI.4 Other Types of Comparators
VI.5 Improvement in Comparator Performance
A. Hysteresis
B. Autozeroing
VI.6 High Speed Comparators

Organization

Chapter 10
Chapter 11
D/A and A/D
Analog Systems
Converters
SYSTEMS

Chapter 7 Chapter 8 Chapter 9

CMOS Simple CMOS High Performance
Comparators OTA's OTA's

COMPLEX

CIRCUITS
Chapter 5 Chapter 6
CMOS CMOS Amplifiers
Subcircuits
SIMPLE

Chapter 2 Chapter 3
CMOS Device Chapter 4 Device
CMOS
Modeling Characterization
Technology

DEVICES
Allen and Holberg - CMOS Analog Circuit Design Page VII.1-1

VII.1 - CHARACTERIZATION OF
COMPARATORS

What is a Comparator?

A comparator is a circuit which compares two analog signals and

outputs a binary signal based on the comparsion. (It can be an op amp
without frequency compensation.)

Characterization of Comparators

We shall characterize the comparator by the following aspects:

• Resolving capability
• Speed or propagation time delay
• Maximum signal swing limits
• Input offset voltage
• Other Considerations
Noise
Power
Etc.
Allen and Holberg - CMOS Analog Circuit Design Page VII.1-2

VOLTAGE COMPARATORS

Definition of a Comparator

VA +
VOUT
VB -

Noninverting
VOUT
VOH

 V O H when VA ≥ VB

VOUT =  VA - VB
 V OL when V A < V B
VOL

Inverting
VOUT

 V O L when VA ≥ VB VOH

VOUT = 
 V OH when V A ≤ V B VA - VB

VOL
Allen and Holberg - CMOS Analog Circuit Design Page VII.1-3

COMPARATOR PERFORMANCE

1. Speed or propagation time delay.

The amount of time between the time when VA - V B = 0 and the
output is 50% between initial and final value.

2. Resolving capability.
The input change necessary to cause the output to make a transition
between its two stable states.

3. Input common mode range.

The input voltage range over which the comparator can detect
V A = VB .

4. Output voltage swing (typically binary).

5. Input offset voltage.

The value of V OUT reflected back to the input when VA is physically
connected to V B.
Allen and Holberg - CMOS Analog Circuit Design Page VII.1-4

APPROACHES TO THE DESIGN OF VOLTAGE

COMPARATORS

Open Loop

Use of a high-gain differential amplifier.

V OH - V O L
Gain =
resolution of the comparator

Regenerative

Use of positive feedback to detect small differences between two

voltages, VA and VB. I.e., sense amplifiers in digital memories.

Open Loop - Regenerative

Use of low gain, high speed comparator cascaded with a latch.

Results in comparators with very low propagation time delay.

Charge Balancing

Differential charging of a capacitor. Compatible with switched

capacitor circuit techniques.

Type Offset Voltage Resolution Speed (8 bit)

(Power supply)
Open-loop 1-10 mV 300µV (±5V) 10 MHz
Regenerative 0.1 mV 50µV (±5V) 50 MHz
Charge
Balancing 0.1 mV 5mV (5V) 30 MHz
Allen and Holberg - CMOS Analog Circuit Design Page VII.1-5

COMPARATOR MODELS - OPEN LOOP

Zero Order Model

VOUT
VOH

- +
VP - VN

VOL

Model

VP
+
+ +
fo VP - VN VO
-
-
VN -

for ( V P - V N ) ≥ 0
 V O H
fo( V P - VN ) = 
 V OL for ( V P - V N ) ≤ 0
Allen and Holberg - CMOS Analog Circuit Design Page VII.1-6

COMPARATOR MODELS - CONT'D

First Order Model

Transfer Curve

VOUT

VOH

VIL
VP - VN
VIH

VOL

Model

VP
+
+ +
f1 VP - VN VO
-
-
VN -

 V O H for ( V P - V N ) ≥ VIH
f1( V P - V N ) = AV( V P - V N ) f o r V I L ≤ ( V P - V N ) ≤ V I H
 V OL for ( V P - V N ) ≤ VIL
Allen and Holberg - CMOS Analog Circuit Design Page VII.1-7

COMPARATOR MODELS - CONT'D

First Order Model with Offset

Transfer Curve
VOUT

VOS VOH

VIL
VP - VN
VIH

VOL

First Order Model with Offset

+-VOS
VP + - V'P +
+ +
f1 V'P - V'N VO
-
- -
VN V'N

Time Response of Noninverting, first order model

VOH
VOUT v = VOH + VOL
2
VOL

VIH
VP - VN tP v = VIH + VIL
2
VIL
Time
Allen and Holberg - CMOS Analog Circuit Design Page VII.2-1

VII.2 - DEVELOPMENT OF A CMOS

COMPARATOR

SIMPLE INVERTING COMPARATOR

VDD

vN M2
I2
vO
IB
VBIAS M1

VSS

Fig. 7.2-1 Simple inverting comparator

VDD ∆VIN

vO

VTRP
vN

Fig. 7.2-2 DC transfer curve of a simple comparator

Low gain ⇒ Poor resolution

VTRP = f V D D  + process parameters
Allen and Holberg - CMOS Analog Circuit Design Page VII.2-2

CALCULATION OF THE TRIP POINT, VTRP

vO
c t. vO = V IN + VT2
VDD 2a t.
VDD M a
2s
M
VIN M2

vO
M1 sat.
VBIAS M1 VBIAS - VT1
M1 act.
VSS VIN
VSS VSS VDD
vN VTRP
Operating Regions-
vDS1 ≥ v GS1 - VT ‘ vO - VSS ≥ V BIAS - VSS - VT1
v O ≥ V BIAS - V T 1

vSD2 ≥ vSG2 - VT2 ‘ V DD - vO ≥ VDD - vIN - VT2

v O ≤ v I N + VT2

Trip Point-
Assume both M1 and M2 are saturated, solve and equate drain
currents for VTRP. Assume λ ≈ 0.
K N W1 2
iD1 = 2 L V BIAS - V SS - V T 1
1
K P W2 2
iD2 = 2 L V D D - v I N - VT2 
2  

KN( W1/L1)
iD1=iD2 ‘ vIN = VTRP = VDD- VT2 - KP( W2/L2) ( V BIAS - V SS - V T 1)

 W1  W2
I.e. V DD = -VSS = 5V, VBIAS = -2V and KN L  = KP L 
 1  2
VTRP = 5-1-(-2+5-1) = 4-2 = 2V
Allen and Holberg - CMOS Analog Circuit Design Page VII.2-3

COMPARATOR USING A DIFFERENTIAL AMPLIFIER

VDD

M3 M4

vO
M1 M2
vP vN

VBIAS M5

vO

VOH = VDD
VOH'
M1 & M2 in
saturation

VOL'
VOL
VSS
vP - vN
-1 +1 Av

Gain is still low for a comparator

Allen and Holberg - CMOS Analog Circuit Design Page VII.2-4

DERIVATION OF OUTPUT SWING LIMITS

VDD vP > vN

M3 M4
1. Current in M1 increases and
vO current in M2 decreases.
I1 I2 2. Mirroring of M3-M4 will
M1 M2
vP vN cause vO to approach VDD .
3. VOH' = VDD - VDS4(sat)
ISS I4
VOH ' = VDD -
VBIAS β4
M5
I5
VOH ' = VDD -
VSS Kp'( W4/L4)

vP < vN I5
V O H ' = VD D -
Kp'( W3/L3)
Assume vN is a fixed DC voltage
4. Finally, vO ‘ V DD causing the
1. vO starts to decrease, M3-M4 mirror mirror M3-M4 to no longer be
is valid so that I1 = I2 = ISS/2 .
valid and V OH ≈ V DD.
2. VOL ' = vN - VGS2 + VDS2
when M2 becomes non-sat. we have (I2 = I4 = 0 , I3 = I1 = I5)
VDS2(sat) = VGS2 - VT so that
V OL ' = v N - V T 2
3. For further decrease in vO, M2 is non-
sat

and therefore the VGS2 can increase  I 1 still equals I2 due to mirror
allowing the sources of M1 and M2 to 
fall(as v P falls).
4. Eventually M5 becomes non-sat and I5
starts to decrease to zero. M2 becomes a
switch and v O tracks V S2(VDS5) all the
way to VSS.
∴ V OL = V SS .
 Allen and Holberg - CMOS Analog Circuit Design Page VII.2-5

TWO-STAGE COMPARATOR

Combine the differential amplifier stage with the inverter stage.

• Sufficient gain.
• Good signal swing.

VDD

M3 M4

M6

vN M1 M2
vP vO
I8

M5
M8 M7

VSS
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-1

VII.3 - DESIGN OF A TWO-STAGE CMOS

COMPARATOR

DC BALANCE CONDITIONS FOR TWO-STAGE

COMPARATOR

• Try to keep all devices in saturation - more gain and wider signal
swings.

• Based on gate-source and DC current relationship. I.e. if M1 and M2

are two matched devices and if VGS1 = VGS2, then ID1 = I D2 or vice
versa.

W1
Let S1 = L ,
1
M1 and M2 matched gives S 1 = S2.
M3 and M4 matched gives S 3 = S4.
also, I 1 = I2 = 0.5I5.
From gate-source matching, we have
 S7  S6
VGS5 = VGS7 ‘ I7 = I5   and I 6 = I4   ← Assume
S5 S4
VGS4 =VGS6
For balance conditions, I6 must be equal to I7, thus
I 5 S7 S6
.
I4 S5 = S4

I5
Since
I4 = 2, then DC balance is achieved under the following:
S6 S
= 2 . 7 ‘ VDG4 = 0 ‘ M4 is saturated.
S4 S5
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-2

SYSTEMATIC OFFSET ERROR

VDD =10V
+ +
2V
KN = 24.75 µA/V2 20 - 20 2V
10 10
KP = 10.125 µA/V2 M3 - M6 40
M4
VTN = -VTP = 1V 10
λN = 0.015V -1 20 20
10 10 i6
λP = 0.020V -1 vN vP vO =5V
I8 i7
M1 M2
20µA +
10
10 3V 10
M8
M5 M7 10
-
Find VOS to make i6 = i 7 VSS =0V

(1) Find the mismatch between i6 and i 7

i7 1 + λ N v D S 7 W7/L7 1 + (0.015)(5)
i5 = 1 + λ N v D S 5 W5/L5 = 1 + (0.015)(3) (1) = 1.029
i6 1 + λ P v D S 6 W6/L6 1 + (0.02)(5)
i4 = 1 + λ P v D S 4 W4/L4 = 1 + (0.02)(2) (2) = 2.115
i5 = 2i4
∴ i7 = (1.029)(2)i4 = 2.057i4 and i6 = 2.115i4

(2) Find how much vGS6 must be reduced to make i6 = i 7

∆vGS6 = vGS6(2.115i4) - vGS6(2.057i4)
2L6
∆vGS6 =  
KPW6 i 4  2.115 - 2.057 = 14.11 mV

(3) Reflecting ∆vGS6 into the input

 2  KN( W2/L2)
A v(diff) =   = 89.9
λ 2 + λ 4  I5
∆vGS6 14.1 mV
∴ VOS = A (diff) = 89.9 = 0.157 mV
v
 Allen and Holberg - CMOS Analog Circuit Design Page VI.3-3

DESIGNING FOR COMMON MODE INPUT RANGE

VDD
+
VSG3
- M3 vG1 (min) = VSS + VDS5 + VGS1
I5/2 I5
+ v G1 (min) = V SS + V DS5 + V T1 (max) +
VDG1 2β1
- +
VG1 VDS1
+ M1 - vG1 (max) = VDD - VSG3 - VDG1(sat)
VGS1 + I5
- v G1 (max) = V D D -
I5 2β3 - VT3(max) + V T1 (min)
VBIAS VDS5
where V DG1(sat) = -VT1
M5 -
VSS

Example

Design M1 through M4 for a CM input range 1.5 to 9 Volts when VDD =

10 V, ISS = 40µA, and VSS = 0V. Table 3.1-2 parameters with |VTN,P| =
0.4 to 1.0 Volts,
I5
vG1(min) = VSS + VDS5 + β1 + VT1(max)
40µA
1.5 = 0 + 0.1 + + 1 (assumed VDS5 ≈ 0.1V- it probably more
β1
reasonable to assume β1 is already defined and find β5)

KNW 1 W1 W 2
β1 = L1 = 250 µA/V ‘
2
L1 = L2 = 14.70
I5
vG1(max) = VDD - β3 - |VT3(max)| + VT1(min)

K PW 3 W3 W 4
β3 =
L3 = 250 µA/V ‘
2
L3 = L4 = 31.25
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-4

GAIN OF THE TWO-STAGE COMPARATOR

+ +
gm1vid r ds2 r ds4 v1 gm6v1 r ds6 r ds7 vout
- -

vid = vP - vN

 gm1   gm6 
Av = g   
 ds2 + g ds4  g ds6 + g ds7

 W1  W6
2 KNKP L  L 
 1  6 
Av =
( λ2 + λ4) ( λ6 + λ7) I1I6

W1 W6
Using L = 5, L = 5, λN = 0.015V-1 , λP = 0.02V-1
1 6
and Table 3.1-2 values;
2 (17)(8)(5)(5) . -6 95199.10-6
Av = 10 =
(0.015+0.02)2 I1I6 I1I6

Assume I1 = 10 µA and I6 = 100 µA

Av = 3010

V OH - VOL
= Resolution = 5 mV (assume)
Av
5 .
then VOH - V OL =
1000 3000 = 15 Volts
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-5

PROPAGATION DELAY OF THE TWO-STAGE

COMPARATOR

VDD
signal swing
less than the
M3 M4 output
VGS6 +
-
M6
vN vP i6 key node
M1 M2
CL1 vO
i7
CL2
M5
VBIAS M7
i5
VSS

V GS6 = VDD - v P + V D G 2

dv
iC = C dt , ∆t =
∆v
∆t2+ = C L2  
CI V TRP3 - V S S
 K P W6 V - v P - V D G 2 - |V T6 | ) 2 -

 2 L6 ( D D I7 
∆t+2

VTRP3
∆t2- = CL2  W L 
V
VDD
SS
V DD - V TRP3
  7 5  i 
VTRP3
  L7 W5 5 
∆t-2

isource/sink
Slew rate =
CLi
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-6

CALCULATION OF COMPARATOR PROPAGATION DELAY

Find the total propagation delay of +5V

the comparator shown when the input 10
vP goes from -1 to +1 in 2ns. Assume 10 40
M3 M4 10
the trip point of the output(next stage) vDO
C L1=0.3pF
M6
is zero. I6
vN M1 M2
20 vO
Total delay = 1st stage + 2nd stage 10 vP CL2=
10pF
delay delay
I5=20µA I7 =40µA
∆t = ∆t1 + ∆t2
-5V
( v DO (t 0 ) - V TRP2)
∆t1 = CL1 ,
I5
vDO(t0) = 5 because vP = -1V
2I7
VTRP2 = VDD - VGS6, VGS6 = |VT6 | +
KP'( W6/L6)
2.40
VGS6 = 1 + = 2.58 V ‘ VTRP2 = 5 - 2.58 = 2.42 V
8.4
 0.3pF
∴ ∆t1 = (5 - 2.42)  = 38.7ns
20µA
 CL2   CL2 
∆t2 = v O (t 0 ) - 0   =5 
I 6 - I 7  I 6 - I 7 
KP6' W6 
I6 = 2  L  V D D - V D O (min) - VT6  2
 6  
[VDO(min) is an optimistic assumption based on vDS2 ≈ 0]

I5
VDO(min) ≈ vDS2(≈0) - vGS1 + vN = -VT1 - = -1.77
KN.2
8.10-6
2 (4)(5 - (-1.77) -1) = 533 µA
I6 = 2

10 pF
∴ ∆t2 = 5 (533 - 40) µA = 101 ns

∆t = ∆t1 + ∆t2 ≈ 139 ns

Second order consideration: Charging of Csb of M1 and M2

Allen and Holberg - CMOS Analog Circuit Design Page VI.3-7

SIMULATION OF THE PROPAGATION DELAY

5v
+5V
10
10
M3 M4
M6 40
(6)
10
vN CL1
M1 M2 (9) vO
20
3v 10 vP
CL2
2.42v 10
M8 10 20
M7 10

-5V V(9)

1v vP

0v tprop=167 ns

Actual
-1 v

-1.54v V(6)

COMPARATOR PROPAGATION DELAY

Approx. VDD 10 0 DC 5V
VSS 11 0 DC -5V
VN 1 0 DC 0V
VP 2 0 PULSE(-1 1 0N 1N 1N 500N 1U)
M1 3 1 5 5 MNMOS W=20U L=10U
M2 6 2 5 5 MNMOS W=20U L=10U
M3 3 3 10 10 MPMOS W=10U L=10U
M4 6 3 10 10 MPMOS W=10U L=10U
-3 v M5 5 8 11 11 MNMOS W=10U L=10U
M6 9 6 10 10 MPMOS W=40U L=10U
M7 9 8 11 11 MNMOS W=20U L=10U
M8 8 8 11 11 MNMOS W=10U L=10U
CL1 6 0 0.3PF
CL2 9 0 10PF
IS 0 8 DC 20UA
.MODEL MNMOS NMOS VTO=1 KP=17U
+LAMBDA=0.015 GAMMA=0.8 PHI=0.6
.MODEL MPMOS PMOS VTO=-1 KP=8U
+LAMBDA=0.02 GAMMA=0.4 PHI=0.6
.TRAN 2N 300N
.PRINT TRAN V(6) V(9) V(2)
.PROBE
.END

-5 v
0ns 50ns 100ns 150ns 200ns 250ns 300ns
Time
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-8

SMALL SIGNAL PERFORMANCE

+ +
vin gm1 gm2
- - +

R1 C1 R2 C2 vout
-

vout(s) A oω p1ω p2
=
vin(s) ( s + ω p 1) ( s + ω p 2)
1
ω p1 = R C
1 1
1
ω p2 =
R2C2
Ao = gm1gm2R1R2

Example - (Fig 7.3-4)

1 1
I5 = 20µA ‘ R1 = g = 10µA = 3.33MΩ
ds2 + g ds4
1
ω p1 =
(0.3pF)(3.33MΩ) = 1Mrps

1 1
I7 = 40µA ‘ R2 = g =
ds6 + g ds7 40µA(.03) = 833KΩ
1
ω p2 =
(10pF)(833KΩ) = 120Krps

g m1 = 26µs, gm2 = 50.6µs ‘ A o = 1099

Allen and Holberg - CMOS Analog Circuit Design Page VI.3-9

TWO-STAGE, CMOS COMPARATOR

General Schematic

VDD

M3 M4

M6

vN M1 M2
vP vO
I8

M5
M8 M7

VSS

Key Relationships for Design:

β β
i D = (v G S - V T ) 2 ⇒ iD (sat) = 2 [vDS(sat)]2
2
or
2iD(sat)
v DS (sat) = β

Also,
gm = 2βI D

where
KW
β= L
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-10

COMPARATOR DESIGN PROCEDURE

1. Set the output current to meet the slew rate requirements.
dV
i = C dt

2. Determine the minimum sizes for M6 and M7 for the proper ouput
voltage swing.
2ID
vDS (sat) = β
3. Knowing the second stage current and minimum device size for M6,
calculate the second stage gain.
-g m6
A2 =
g ds6 + g ds7
4. Calculate the required first stage gain from A2 and gain specifications.
5. Determine the current in the first stage based upon proper mirroring
and minimum values for M6 and M7. Verify that Pdiss is met.
6. Calculate the device size of M1 from A1 and I DS1.
-g m1 2K'W/L
A1 = g and gm1 =
ds1 + g ds3 IDS1
7. Design minimum device size for M5 based on negative CMR require-
ment using the following (IDS1 = 0.5IDS5):
IDS5
vG1(min) = VSS + VDS5 + β1 + VT1(max)
2IDS5
where VDS5 =
β5 = VDS5(sat)
8. Increase either M5 or M7 for proper mirroring.
9. Design M4 for proper positive CMR using:
IDS5
vG1(max) = VDD -
β3 - VTO3 (max) + VT1
10. Increase M3 or M6 for proper mirroring.
11. Simulate circuit.
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-11

DESIGN OF A TWO-STAGE COMPARATOR

Specifications:

Avo > 66 dB Lambda = 0.05V-1 (L = 5 µm)

Pdiss < 10 mW VDD = 10 V
CL = 2 pF VSS = 0 V
K'W
tprop < 1 µs Recall that β = L

CMR = 4-6 V
Output swing is VDD - 2V and VSS + 2V

1). For t prop << 1 µs choose slew rate at 100 V/µs

dvOUT
∴ I7 = CL
dt = ( 2 10 ) ( 100 10 ) = 200 µA
. -12 . -6

2). Size M6 and M7 to get proper output swing,

M7:
2I7 2(200µA) W7
2V > vDS7(sat) = →
β7 = 17.0µA/V 2( W7/L7) L7 > 5.88

M6:
2( IOUT+I7) 2(400µA) W6
2V > vDS6(sat) = = →
β6 8.0µA/V 2( W6/L6) L6 > 12.5

-g m6  -1  2KP'W6
3). A 2 = g   I6L6 ≈ -10
=
ds6 + g ds7 λ N + λ P 

4). A vo = A 1A2 = 66 dB ≈ 2000 → A1 = 200

Allen and Holberg - CMOS Analog Circuit Design Page VI.3-12

COMPARATOR DESIGN - CONT'D

S4
5). Assuming vGS4 = v GS6, then I4 =
S6 I6
1
choose S 4 = 1 which gives I4 = 12.5 (200µA) = 16.0 µA
S5 200µA
5.88 = 34 µA
Assume S5 = 1 which gives I 5 = I 7 =
S7
1
and I4 = I5 = 17 µA
2
W
Choose I 4 = 17 µA to keep L ratios greater than 1.
W4 W 6  17 
∴ I5 = 34 µA
L4 = L6 200 = 1.06 ≈ 1.0
Pdiss = 10( I 7 + I 5 ) = 2.34 mW < 10 mW

1 2KN'W1 W1 I
6). A1 = λ + λ → = [ (λ 1 + λ 4 )A 1 ] 2 4 = 200
1 4 I4L 1 L1 2KN'
W1
∴ L = 200 (Good for noise)
1

I5
7). V DS5 = vG1(min) - VSS - β1 - VT1(max)
(34)
V DS5 = 4 - 0 - -1 = 2.90 V
2(17.0)(200)
2I5 2(34µ) W5
VDS5 = → L > 0.48
β5 = (17µ)S5 5

I5 34 W5
8). S5 = S = (5.88) = 1.0 →
I7 7 200 L5 = 1 . 0
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-13

COMPARATOR DESIGN - CONT'D

I5
9). VG1(max) = VDD - β3 - VTO3 (max) + VT1(min)
I5
β3 =
 V D D - V G1 (max) - VTO3 (max) + V T1 (min) 2
 
34 µA
= = 2.76.10 -6
( 1 0 - 6 - 1 + 0 . 5) 2
W3 (2.76)(2) W3 W 4
∴L = = 0.69
3 8 L3 = L4 > 0.69
W4
(Previously showed L > 1.06 so no modification is necessary)
4

10). Summary
 W
Wdrawn =  (L - 1.6)
L

Design Ratios Actual Values with 5µm Proper Mirroring

minimum geometry and LD = 0.8µm

W1 W2 W1 W 2 1000 680
= L = 200 = L = 5 5
L1 2 L1 2
W3 W4 W3 W4 5 3.4 5
= L = 1.0 = L =5 ‘5
L3 4 L3 4 5
W5 W5 3.4 5
= 1.0 = 1.0 ‘5
L5 L5 5
W6 W6 62.5 60
= 12.5 = 5 5
L6 L6
W7 W7 30 30
= 5.88 = 5 5
L7 L7
↑
S6 S7
(Need to adjust for proper mirroring) ⇒ = 2
S4 S5
Allen and Holberg - CMOS Analog Circuit Design Page VII.4-1

VII.4 - OTHER TYPES OF COMPARATORS

FOLDED CASCODE CMOS COMPARATOR
Circuit Diagram
VDD

MP3 MP4
MP8

MP6
MP12 MP13
vOUT

MN1 MN2
MN25 MN10 MN11
v2 v1

MN24 MN7 MN9 MN5

V SS

Small Signal Model

1 1 +
gm12 i1 gm13 i2
rout vout
i2 i1
gm1 v2 gm2 v1
-
where
R out ≈ (rds5gm11rds11)||((rds4||rds2)gm13rds13) =

1
=g
ds5gds11 (gds2+gds4)gds13
gm11 + gm13
The small signal voltage gain is
vout = r out (i2-i1) = (gm2 +gm1 )Rout vin = g  vin
gm1 +gm2
 ds5gds11 (gds2+gds4)gds13
 gm11 + gm13 
where vin = v1 - v2.
Allen and Holberg - CMOS Analog Circuit Design Page VII.4-2

FOLDED CASCODE CMOS COMPARATOR - CONTINUED

Frequency Response
Small signal model-

i2 +
C1 i1 C2 C3
1 vout
i2 i1 rout
gm1 v2 gm12 gm2 v1 1
gm13 -

where
C1 = C GS12 + C BS12 + C DG3 + C BD3

C2 = C GS13 + C BS13 + C DG4 + C BD4

and C3 = CDG11 + CBD11 + CDG13 + CBD13 + CLoad

AVD0ω3
AVD(s) ≈ s + ω
3

where
1
ω3 =
routC3

Typical performance-
W 1 W 2 W 11 W 13
ID1 = ID2 = 50µA and ID3= I D4 = 100µA,
L1 = L2 = L11 = L13
=1, assume C 3 ≈ 0.5pF, and using the values of Table 3.1-2 gives:

gm1 = gm2 = gm11 =41.2µS gm13 = 28.3µS

gds5 = gds11 = 0.5µS gds4 = gds13 = 0.25µS

Therefore, rout = 121MΩ, ω3 = 16.553krps, and AVD0 = 4,978

resulting in a gain-bandwidth of 13.11MHz.
C3∆V 0.5pFx10V
Delay = ∆T = I = 100µA = 50nS
max
Allen and Holberg - CMOS Analog Circuit Design Page VII.4-3

OPEN LOOP COMPARATOR - MC 14575

BIAS M1 M6
M8 M10
vO
- M2 M3 +
M9 M11
M7

M4 M5

Performance (ISET = 50 µA)

Rise time
= 100 ns into 50 pF
Fall time
Propagation delay = 1 µs
Slew rate = 2.7 Volts/µs
Loop Gain = 32,000

Comments
The inverter pair of M8-M9 and M10-M11 are for the purpose of
providing an output drive capability and minimizing the propagation delay.
Allen and Holberg - CMOS Analog Circuit Design Page VII.4-4

CLAMPED CMOS VOLTAGE COMPARATOR

VDD VDD

M8 M6

BIAS M1 VPB

vO
- +
M2 M3 VNB

M9 M4 M5 M7

VSS

Drain of M2 and M3 clamped to the gate voltages of M4 and M5.

M6 and M7 provide a current, push-pull output drive capability

similiar to the current , push-pull CMOS OP amp.

Comparator is really a voltage comparator with a current output.

Allen and Holberg - CMOS Analog Circuit Design Page VII.6-1

VII.5 - COMPARATORS WITH HYSTERESIS

HYSTERESIS

Why Hysteresis?
Eliminates "chattering" when the input is noisy.

Comparator with no Hysteresis

vin
Comparator
threshold

Time

Comparator
output

Comparator with Hysteresis

vin
vout

VTRP+
VTRP-

Time
vin
VTRP-
VTRP+ comparator
output
Allen and Holberg - CMOS Analog Circuit Design Page VII.6-2

VOLTAGE COMPARATORS USING EXTERNAL FEEDBACK

Inverting

vOUT

VOH
vB -
vOUT VREFR2
vA + R1 +R2

vB
R2 VOHR1
R1 R1 +R2
+
V
- REF VOL
VOLR1
R1 +R2

Noninverting

vOUT

R2
VOH
R1 vA +
vIN VREF R1 +R2
vOUT R2
vB -
vIN
+
R1 V
- VREF R2 OL
VOL
R1 V
R2 OH
Allen and Holberg - CMOS Analog Circuit Design Page VII.6-3

COMPARATORS WITH INTERNAL FEEDBACK

Cross-Coupled Bistable

VDD

M3 M10 M11 M4
M8 M6

M1 M2
vO

BIAS M5

M9 M7

VSS

(1). Positive feedback gives hysteresis.

(2). Also speeds up the propagation delay time.

 EXAMPLE 7.4-1 COMPARATOR WITH HYSTERESIS
6.0V

5.0V

4.0V
Allen and Holberg - CMOS Analog Circuit Design

3.0V

2.0V

1.0V
Page VII.6-4

-600m -400m -200m 0m 200m 400m 600m

Allen and Holberg - CMOS Analog Circuit Design Page VII.6-5

AUTO ZEROING OF VOLTAGE COMPARATORS

Model of the Comparator Including Offset

+
IDEAL
- + -
VOS

Auto Zero Scheme-First Half of Cycle

+
IDEAL
- + - +
VOS CAZ V
- OS

Auto Zero Scheme-Second Half of Cycle

VIN +
IDEAL
- + -
- +
VOS VOS
+ 0V
-
Allen and Holberg - CMOS Analog Circuit Design Page VII.6-6

GENERALIZED AUTO ZERO CONFIGURATION

φ1

φ2

vIN+ +
φ1 VOS IDEAL vOUT
+ - - + -
vIN-
CAZ VOS

φ2
φ1

Good for inverting or noninverting when the other terminal is not

on ground.
Allen and Holberg - CMOS Analog Circuit Design Page VII.6-7

Noninverting Auto-Zeroed Comparator

φ1

φ2

-
φ1 vOUT
vIN +
CAZ

φ2 φ1

Inverting Auto-Zeroed Comparator

φ1

φ2

CAZ
vIN -
vOUT
φ1 +

Use nonoverlapping, two-phase clock.

Allen and Holberg - CMOS Analog Circuit Design Page VII.6-1

VII.6 - HIGH SPEED COMPARATORS

Concept

Question: For a given input change, what combination of first-order open-

loop comparators and a latch gives minimum propagation delay?

+ Q
vIN C1 C2 C3 Cn Latch
- Q

n first-order, open-loop comparators

with identical gains, A
Concept:
voltage

High
Output
Level ∆ = input voltage
change Latch
n tn-1 )e-t/τ ]
vout = e t/τ ∆ v out = A [1 - (1 + (n-1)! ∆
A5∆ 5
A4∆ 4
A3 ∆ 3
v out = A2[1 - (1 + t)e -t/τ )] ∆
A2∆ 2
v out = A(1-e-t/τ )∆
A∆ n=1

t3 tL Time

Propagation delay time = t3 + tL for n=3

Answer:
tp(min) occurs when n=6 and A=2.72=e

Implementation:
n=3 and A≈6 gave nearly the same result with less area.
[Ref: Doernberg et al., “A 10-bit 5 MSPS CMOS Two-Step FLASH ADC”JSSC April 1989 pp 241-
249]
 Allen and Holberg - CMOS Analog Circuit Design Page VII.6-2

HIGH SPEED COMPARATORS-CONT'D

Conceptual Implementation-

+ + - + - + - Q
vIN Latch
- - + - + - + Q

VDD

Q
FB Reset
Q
FB

VB1 LATCH

Offset and level shifting- VB2

vIN-VOS VSS
+ - _
vIN

+
+
VOS
-
Allen and Holberg - CMOS Analog Circuit Design Page VII.7-1

VII.7 - COMPARATOR SUMMARY

• Key performance parameters:

Propagation time delay
Resolving capability
Input common mode swing
Input offset voltage
• Types of comparators:
Open loop
Regenerative
Open loop and regenerative
Charge balancing
• Open loop comparator needs differential input and second stage
• Systemative offset error is offset (using perfectly matched transistors)
that is due to current mirror errors.
• For fast comparators, keep all node swings at a minimum except for the
output (current comparators?).
• Key design equations:
KW 2iD 2KWID
iD = 2
2L (vGS-VT) , vDS(sat) = K(W/L) , and gm = L
• Positive feedback is used for regenerative comparators.
• Use autozeroing to remove offset voltages (charge injection is limit).
• Fastest comparators using low-gain, fast open loop amplifiers cascaded
with a latch.