VLSI Lab Report

Department of Electronics and Electrical Communication

Engineering

Submitted by:
Aditya Agarwal (Roll No.: 22EC10004)
Shreyans Sharma (Roll No. 22EC10072)

Group Number: 4

Experiment No.: 2
Asynchronous and Synchronous Counters

Date of Submission: 2nd February 2025

 OBJECTIVES
1. To design a 4-bit Asynchronous Down counter using D flip flop.

2. To design a 4-bit Synchronous Up counter using T flip flop.

THEORY
Asynchronous Counters
In asynchronous counters, each flip flop is triggered by the output of the previous flip flop
rather than a common clock. Due to the cascading logic, the circuit complexity of asynchronous
counters is lesser as the design is simpler. They are also known as ripple counters.

Figure 1: Asynchronous counter using D flip flop

Synchronous Counters
All flip-flops in a synchronous counter share a common clock signal and change state simultane-
ously. This parallel triggering eliminates the propagation delay seen in asynchronous counters.

Figure 2: Synchronous Up counter using T flip flop

1
 IMPLEMENTATION
4-bit Asynchronous Down counter

Listing 1: Implementation of 4-bit Asynchronous Down-counter

1 module a sy nc _d ow n_ co un te r (
2 input clk ,
3 input reset ,
4 output [3:0] count
5 );
6
7 wire q0 , q1 , q2 , q3 ;
8

9 d_flip_flop dff0 (
10 . clk ( clk ) ,
11 . reset ( reset ) ,
12 . d (~ q0 ) ,
13 . q ( q0 )
14 );
15
16 d_flip_flop dff1 (
17 . clk ( q0 ) ,
18 . reset ( reset ) ,
19 . d (~ q1 ) ,
20 . q ( q1 )
21 );
22
23 d_flip_flop dff2 (
24 . clk ( q1 ) ,
25 . reset ( reset ) ,
26 . d (~ q2 ) ,
27 . q ( q2 )
28 );
29
30 d_flip_flop dff3 (
31 . clk ( q2 ) ,
32 . reset ( reset ) ,
33 . d (~ q3 ) ,
34 . q ( q3 )
35 );
36
37 assign count = { q3 , q2 , q1 , q0 };
38
39 endmodule
40
41 module d_flip_flop (
42 input clk ,
43 input reset ,
44 input d ,
45 output reg q
46 );
47 always @ ( posedge clk or posedge reset ) begin
48 if ( reset )
49 q <= 1 ’ b0 ;
50 else
51 q <= d ;
52 end
53 endmodule

2
 4-bit Synchronous Up counter

Listing 2: Implementation of 4-bit Synchronous Up counter

1 module tff (
2 input clk ,
3 input reset ,
4 input t ,
5 output reg q
6 );
7
8 always @ ( posedge clk or posedge reset )
9 begin
10 if ( reset ) q =4 ’ b0 ;
11 else if ( t )q <=~ q ;
12 end
13
14 endmodule
15
16 module upcounter (
17 input clk ,
18 input reset ,
19 output [3:0] op
20 );
21
22 wire q0 , q1 , q2 , q3 ;
23
24 tff ff1 (. clk ( clk ) ,. reset ( reset ) ,. t (1) ,. q ( q0 ) ) ;
25 tff ff2 (. clk ( clk ) ,. reset ( reset ) ,. t ( q0 ) ,. q ( q1 ) ) ;
26 tff ff3 (. clk ( clk ) ,. reset ( reset ) ,. t ( q1 && q0 ) ,. q ( q2 ) ) ;
27 tff ff4 (. clk ( clk ) ,. reset ( reset ) ,. t ( q1 && q2 && q0 ) ,. q ( q3 ) ) ;
28
29 assign op = { q3 , q2 , q1 , q0 };
30
31 endmodule

3
 TESTBENCH CODES
Asynchronous Down Counter Testbench

Listing 3: Testbench for Asynchronous Down Counter

1 module t b _ a s y n c _ d o w n _ c o u n t e r () ;
2 reg clk ;
3 reg reset ;
4 wire [3:0] count ;
5 as yn c_ do wn _c ou nt er uut (
6 . clk ( clk ) ,
7 . reset ( reset ) ,
8 . count ( count )
9 );
10 initial begin
11 clk = 0;
12 forever #5 clk = ~ clk ;
13 end
14 initial begin
15 reset = 1;
16 #10 reset = 0;
17
18 #200 $stop ;
19 end
20 endmodule

Synchronous Up-counter Testbench

Listing 4: Testbench for Synchronous Up-counter

1 module t b _ s y n c _ 4 b i t _ u p c o u n t e r _ t f f () ;
2
3 reg clk , reset ;
4 wire [3:0] op ;
5
6 upcounter fnuc (. clk ( clk ) ,. reset ( reset ) ,. op ( op ) ) ;
7
8 initial
9 begin
10 clk = 1;
11 forever #5 clk = ~ clk ;
12 end
13
14 initial
15 begin
16 reset = 1;
17 #10 reset = 0;
18

19 #200 $stop ;
20 end
21 endmodule

4
 TIMING DIAGRAMS
Asynchronous Down-counter
Timing diagram illustrating the down counter:

Figure 3: Output waveform of the Asynchronous Down counter

Synchronous Up-counter
Timing diagram illustrating the up counter:

Figure 4: Output waveform of the Synchronous Up counter

DISCUSSIONS
SHREYANS SHARMA [22EC10072]
The asynchronous down counter uses D flip-flops, where the clock of each flip-flop is driven by
the output of the previous one, creating a ripple effect. Each D flip-flop is designed to toggle
by inverting its input, ensuring that the counter decrements with each clock pulse. Due to
the sequential triggering of flip-flops, there is a propagation delay in the asynchronous counter,
which limits its speed for high-frequency applications.
The synchronous up counter uses T flip-flops, where all flip-flops share the same clock signal,
making them switch states simultaneously. The toggling of each T flip-flop depends on the
outputs of the previous flip-flops, ensuring correct binary counting. The synchronous counter
eliminates ripple delay, providing faster and more stable operation compared to the asynchronous
counter, making it more suitable for precise timing applications.

5
ADITYA AGARWAL [22EC10004]
1. The timing diagrams illustrate the functionality of a 4-bit counter, operating in both
asynchronous down-counting and synchronous up-counting modes. The analysis of the
waveforms provides insights into the behavior of the counter under different conditions.

2. Asynchronous Down Counter (First Timing Diagram)

- The counter starts at F (1111) and decrements sequentially to 0 (0000) before wrapping
around to F again.
- This decrementing pattern is visible from 0 ns to 160 ns, where the output transitions
as follows:

F →E→D→C→B→A→9→8→7→6→5→4→3→2→1→0

- At 160 ns, the counter resets to F and resumes decrementing. - The asynchronous down
counter changes state at different times due to ripple effects.
- The individual bit transitions for count[3:0] confirm correct binary decrementing be-
havior.
- The reset signal (reset = 1 at the beginning) ensures the counter starts from a known
state (F) at 10 ns.

3. Synchronous Up Counter (Second Timing Diagram)

- The counter begins at 0 (0000) and increments sequentially to F (1111) before wrapping
around to 0 again.
- Observed from 0 ns to 160 ns, the output progresses as follows:

0→1→2→3→4→5→6→7→8→9→A→B→C→D→E→F

- At 160 ns, the counter resets to 0 and resumes incrementing.

- The synchronous up counter changes state precisely on the rising edge of the clock.
- The individual bit transitions for op[3:0] confirm correct binary incrementing behavior.

4. The least significant bit (count[0] / op[0]) toggles every clock cycle.

5. Higher bits (count[3] / op[3]) toggle at half the frequency of the preceding bit, confirm-
ing binary counting principles.

6. These wrap around behavior aligns with the expected operation of a 4-bit modulo-16
counter. The observed timing diagrams confirm the expected operation of a 4-bit counter.
The asynchronous down counter exhibits ripple effects, whereas the synchronous up counter
transitions smoothly on clock edges. The correct wrap-around at 0 and F demonstrates
proper modulus operation, verifying the correct design and implementation of both count-
ing mechanisms.