MOSFET Caps and Miller’s Theorem

David Johns

University of Toronto
david.johns@utoronto.ca
High Frequency Cutoff
For HF cutoff
− Some capacitors might be added to reduce bandwidth (say, for
noise reduction)
− However, there are also parasitic capacitors that always occur that
limits high freq bandwith
− There is also parasitic inductances but these are generally small
enough to be ignored in many circuits
Parasitic capacitor examples
− Wiring capacitances
(there is capacitance between any 2 conductors)
− Transistor internal capacitances
MOSFET transistor parasitic capacitances
− Cgs , Cgd : they are inherent to the operation of the transistor
Not possible to ever be zero
− Cdb , Csb : depend on the drain/source region area

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MOSFET Capacitor Model

D
Cgd
Cdb
G B
Csb
Cgs

S
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MOSFET Capacitor Model
ACTIVE REGION
 
2
Cgs = WLCox + WLov Cox (1)
3
Cgd = WLov Cox (2)
Cdb0 Csb0
Cdb = p Csb = p (3)
1 + (Vdb /V0 ) 1 + (Vsb /V0 )
Cox is the gate capacitance per unit area
2


3 WLCox is capacitance under the gate to the channel which is
connected to the source when in the active region
2


3 is due the shape of the channel when in the active region (a
triangle shape)
Lov is the overlap length of the gate extending over the
drain/source regions
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MOSFET Capacitor Model

WLov Cox is the overlap capacitance

Cdb0 is the drain to body capacitance when Vdb = 0
This value depends on the total junction surface area
Vdb is the reverse bias diode voltage of drain to bulk
V0 is the diode built-in voltage (V0 ≈ 0.7V)
Cdb value depends on the reverse bias voltage
Similar descriptions for Csb
TRIODE REGION
− Cgd , Cdb , Csb all the same
− However, Cgs = WLCox + WLov Cox
since channel is now rectangular shaped

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Active Region Small Signal Model with Caps
Assuming Vsb = 0 (bulk tied to source)
Cgd

G D

vgs Cgs gm vgs ro Cdb

Would like a figure of merit for transistor speed

Unity-Gain Frequency (fT )
− Where the short circuit current gain = 1
Recall ωT = 2πfT (can be in Hz or rad/s)

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MOSFET Unity Gain Freq
io

io

By definition for ωT ...

io
(jωT ) = 1 (4)
ii

Cgd io

i1
ii vgs Cgs gm vgs ro Cdb

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MOSFET Unity Gain Freq
iro = 0 and iCdb = 0 since they both have zero volts across them
 
1
vgs = ii (5)
s(Cgs + Cgd )
vgs
i1 =   = sCgd vgs (6)
1
sCgd
io = gm vgs − i1 = gm vgs − sCgd vgs (7)

io = (gm − sCgd )vgs (8)

combining (5) with (8)

io gm − sCgd
(s) = (9)
ii s(Cgs + Cgd )

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MOSFET Unity Gain Freq
Using the definition in (4)
gm − jωT Cgd
=1 (10)
(jωT )(Cgs + Cgd )
   
gm Cgd
− =1 (11)
(jωT )(Cgs + Cgd ) (Cgs + Cgd )

In most technologies, Cgd  Cgs so if we ignore the term

Cgd /(Cgs + Cgd )
 
gm
≈1 (12)
(jωT )(Cgs + Cgd )

solving for ωT , we have

gm gm
ωT ≈ fT ≈ (13)
Cgs + Cgd 2π(Cgs + Cgd )

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MOSFET Unity Gain Freq

How does fT change with technology or circuit choices?

Recall
gm = µn Cox (W /L)Vov (14)
2
Cgs ≈ WLCox (15)
3
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MOSFET Unity Gain Freq
If we assume Cgd  Cgs

gm µn Cox (W /L)Vov
fT ≈ = (16)
2πCgs 2π 23 WLCox

3µn Vov
fT ≈ (17)
4πL2

fT is ...
− independent of W
− proportional to 1/L2 and Vov and µn
Circuit designers can choose W , L, Vov while µn is given for a
technology

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MOSFET Unity Gain Freq

Why does the definition of fT use current gain instead of voltage

gain?
− If an ideal voltage source drives the gate, at high frequencies, the
input impedance goes to zero (due to Cgs ) and therefore the input
current would need to go to ∞
− Also, at very high freq, the output gain would be a voltage divider
between Cgd and Cdb
− It also turns out that fT is a good estimate of the voltage gain when
a transistor single transistor drives another transistor of the same
size and bias conditions.
Generally, circuits are designed to operate up to about fT /10 or
lower
− So fT is an important parameter to know when designing circuits

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Miller’s Theorem

In many amplifiers, there is an impedance between the input and

output of the amplifier which complicates analysis
Miller’s Theorem can be used to modify the circuit to simplify the
analysis
A common example is Cgd in a transistor amplifier
− Miller’s theorem can be used to replace Cgd with 2 grounded
capacitors ...
one at the gate and one at the drain

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Miller’s Theorem
Given a circuit where V2 = KV1 and Z is connected between
nodes V1 and V2 , Z can be replaced by 2 grounded impedances
where
Z Z
Z1 = Z2 = 1
(18)
1−K 1− K

1 2 Z1 1 2 Z2
3 3

Original Circuit Miller Equivalent

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Miller’s Theorem Proof
30
Z Z1 Z2

1 2 1 2
3 3

Original Circuit Equivalent Circuit

Define
V2
K ≡ (19)
V1
Break Z into Z1 and Z2
Find Z1 , Z2 such that the following 2 equations hold
Z1 + Z2 = Z (20)

V30 = V3 = 0 (21)
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Miller’s Theorem Proof
 
V2 − V1
V30 = V1 + Z1 (22)
Z1 + Z2

Combining (19) - (22), we find

Z Z
Z1 = Z2 = 1
(23)
1−K 1− K
We can now attach V30 to V3 since both are at the same voltage
− no extra current flows in or out of V3 since the current through Z1
equals the negative value of the current through Z2

[Davidovic, IEEE Trans. on Ed, 1999]

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Miller’s Theorem
Note that for Z > 0
− For K < 0, both Z1 and Z2 will be positive
− For K > 0, one of Z1 , Z2 will be negative
− For K = 1, both Z1 , Z2 go to ∞
For Z = R
R R
R1 = R2 = (24)
1−K 1 − K1

1
For Z = sC

1
C1 = C(1 − K ) C2 = C(1 − ) (25)
K

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Miller’s Theorem Example
Find Rin and vo /vi in the circuit below where the amplifier is ideal
and has a gain of -10.
R2 = 10k

R1 = 2k
A vo
A = −10
vi Rin

We can use Miller’s Theorem to find the equiv circuit

R1 v1
-10 vo

vi Rin R2,1 R2,2

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Miller’s Theorem Example

R2 10k
R2,1 = = = 909.1Ω (26)
1−A 11
R2 10k
R2,2 = = = 9.1Ω (27)
1 − (1/A) 1.1
Here, we see that Rin = R2,1 = 909.1Ω
We can find v1 /vi as ...
v1 Rin 909.1
= = = 0.3125 V/V (28)
vi Rin + R1 909.1 + 2k

And since vo = −10v1 , we have

v1 vo
vo /vi = × = 0.3125 × −10 = −3.125 V/V (29)
vi v1

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Miller’s Theorem Example
Find the input capacitance of the following circuit where the
amplifier is ideal.
C = 1pF

A = −100
Ceq

Using Miller’s Theorem

Ceq = C(1 − A) = 101C = 101pF (30)

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Miller’s Theorem Example - Bootstrapping
When the amplifier is slightly less than 1, the input capacitance
can be reduced while the input resistance is increased.
C = 1pF

A
A = 0.95
Ceq

Ceq = C(1 − A) = 0.05C = 50fF (31)

R = 1k

A
A = 0.95
Rin

R 1k
Rin = = = 20kΩ (32)
1−A 0.05
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Topics Covered

High freq cutoff

− Mosfet cap modelling
− Mosfet unity gain freq
− Miller’s theorem

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