STM32F469xx

Arm®Cortex®-M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/384+4KB RAM, USB OTG HS/FS,
Ethernet, FMC, dual Quad-SPI, Graphical accelerator, Camera IF, LCD-TFT & MIPI DSI
Datasheet - production data

Features
• Includes ST state-of-the-art patented technology
• Core: Arm® 32-bit Cortex®-M4 CPU with FPU,
LQFP100 (14 × 14 mm)
adaptive real-time accelerator (ART UFBGA169 (7 × 7 mm)
LQFP144 (20 × 20 mm)
Accelerator™) allowing 0-wait state execution LQFP176 (24 × 24 mm)
WLCSP168 UFBGA176 (10 x 10 mm)
from flash memory, frequency up to 180 MHz, LQFP208 (28 × 28 mm)
TFBGA216 (13 x 13 mm)
MPU, 225 DMIPS/1.25 DMIPS/MHz
• Debug mode
(Dhrystone 2.1), and DSP instructions – SWD and JTAG interfaces
• Memories – Cortex®-M4 Trace Macrocell™
– 512 bytes of OTP memory • Up to 161 I/O ports with interrupt capability
– Up to 2 MB of flash memory organized into two – Up to 157 fast I/Os up to 90 MHz
banks allowing read-while-write – Up to 159 5 V-tolerant I/Os
– Up to 384+4 KB of SRAM including 64 KB of • Up to 21 communication interfaces
CCM (core coupled memory) data RAM
– Up to three I2C interfaces (SMBus/PMBus)
– Flexible external memory controller with up to
32-bit data bus: SRAM, PSRAM, – Up to four USARTs and four UARTs
SDRAM/LPSDR, SDRAM, flash NOR/NAND (11.25 Mbit/s, ISO7816 interface, LIN, IrDA,
memories modem control)
– Dual-flash mode Quad-SPI interface – Up to six SPIs (45 Mbits/s), two with muxed
• Graphics full-duplex I2S for audio class accuracy via
– Chrom-ART Accelerator™ (DMA2D), internal audio PLL or external clock
graphical hardware accelerator enabling – 1x SAI (serial audio interface)
enhanced graphical user interface with – 2× CAN (2.0B Active)
minimum CPU load – SDIO interface
– LCD parallel interface, 8080/6800 modes • Advanced connectivity
– LCD TFT controller supporting up to XGA – USB 2.0 full-speed device/host/OTG
resolution controller with on-chip PHY
– MIPI® DSI host controller supporting up to – USB 2.0 high-speed/full-speed
720p 30 Hz resolution device/host/OTG controller with dedicated
• Clock, reset, and supply management DMA, on-chip full-speed PHY and ULPI
– 1.7 V to 3.6 V application supply and I/Os – Dedicated USB power rail enabling on-chip
– POR, PDR, PVD, and BOR PHYs operation throughout the entire MCU
– 4-to-26 MHz crystal oscillator power supply range
– Internal 16 MHz factory-trimmed RC – 10/100 Ethernet MAC with dedicated DMA:
(1% accuracy) supports IEEE 1588v2 hardware, MII/RMII
– 32 kHz oscillator for RTC with calibration • 8- to 14-bit parallel camera interface up to
– Internal 32 kHz RC with calibration 54 Mbytes/s.
• Low power • True random number generator
– Sleep, Stop, and Standby modes • CRC calculation unit
– VBAT supply for RTC, 20×32 bit backup • RTC: subsecond accuracy, hardware calendar
registers + optional 4 KB backup SRAM • 96-bit unique ID
• 3× 12-bit, 2.4 MSPS ADC: up to 24 channels and Table 1. Device summary
7.2 MSPS in triple interleaved mode
• 2× 12-bit D/A converters Reference Part numbers
• General-purpose DMA: 16-stream DMA STM32F469AE, STM32F469AG, STM32F469AI
STM32F469BE, STM32F469BG, STM32F469BI
controller with FIFOs and burst support STM32F469IE, STM32F469IG, STM32F469II
STM32F469xx
• Up to 17 timers: up to twelve 16-bit and two STM32F469NE, STM32F469NG, STM32F469NI
32-bit timers up to 180 MHz, each with up to four STM32F469VE, STM32469VG, STM32469VI
STM32F469ZE, STM32469ZG, STM32469ZI
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input. 2x watchdogs and
SysTick timer

November 2023 DS11189 Rev 8 1/225

This is information on a product in full production. www.st.com
Contents STM32F469xx

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1 Compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.1.1 LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.1.2 LQFP208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.1.3 UFBGA176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1.4 TFBGA216 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1 Arm® Cortex®-M4 with FPU and embedded flash and SRAM . . . . . . . . . 20
2.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 20
2.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 21
2.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.9 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.10 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.11 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.12 DSI Host (DSIHOST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.13 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.14 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 26
2.15 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.16 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.17 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.18 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.19 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.19.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.19.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.20 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.20.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.20.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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2.20.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 34

2.21 Real-time clock (RTC), backup SRAM, and backup registers . . . . . . . . . 34
2.22 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.23 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.24.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.24.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.24.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.24.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.24.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.24.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.25 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.26 Universal synchronous/asynchronous receiver transmitters (USART) . . 39
2.27 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.28 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.29 Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.30 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.31 Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.32 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 41
2.33 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 42
2.34 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.35 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 43
2.36 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 43
2.37 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.38 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.39 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.40 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.41 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.42 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.43 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.44 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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Contents STM32F469xx

4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 95
5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 95
5.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 95
5.3.6 Overdrive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.3.8 Wake-up time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 122
5.3.13 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.3.14 MIPI D-PHY PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.3.15 MIPI D-PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.3.16 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.3.17 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.3.18 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 132
5.3.19 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.3.20 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.3.21 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.3.22 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.3.23 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.3.24 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

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5.3.25 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

5.3.26 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
5.3.27 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
5.3.28 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.3.29 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
5.3.30 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
5.3.31 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 186
5.3.32 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 187
5.3.33 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 189
5.3.34 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

6.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.2 LQFP100 package information (1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.3 LQFP144 package information (1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
6.4 WLCSP168 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.5 UFBGA169 package information (A0YV) . . . . . . . . . . . . . . . . . . . . . . . . 202
6.6 LQFP176 package information (1T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
6.7 UFBGA(176+25) package information (A0E7) . . . . . . . . . . . . . . . . . . . . 209
6.8 TFBGA216 package information (A0L2) . . . . . . . . . . . . . . . . . . . . . . . . .211
6.9 LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
6.10 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 221

A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

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List of tables STM32F469xx

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F469xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 31
Table 4. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 5. Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 6. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 7. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 8. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 9. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 10. STM32F469xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 11. FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 12. Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 13. STM32F469xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 18. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 94
Table 19. VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 20. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 95
Table 21. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 95
Table 22. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 23. Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled except prefetch) or RAM,
regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled), regulator ON . . . . . . . . . . . . . . 100
Table 26. Typical and maximum current consumption in Run mode, code with data
processing running from Flash memory (ART accelerator enabled except prefetch),
regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 27. Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 102
Table 28. Typical and maximum current consumption in Sleep mode, regulator OFF . . . . . . . . . . . 103
Table 29. Typical and maximum current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 30. Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 105
Table 31. Typical and maximum current consumption in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 106
Table 32. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 33. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 34. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 35. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 36. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 37. HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 38. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 39. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 40. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 41. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 42. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 43. PLLSAI (audio and LCD-TFT PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

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STM32F469xx List of tables

Table 44. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 45. MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 46. MIPI D-PHY AC characteristics LP mode and HS/LP transitions . . . . . . . . . . . . . . . . . . . 125
Table 47. DSI-PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 48. DSI regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 49. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 50. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 51. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 52. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 53. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 54. EMI characteristics for fHSE=8 MHz and fCPU=168 MHz . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 55. EMI characteristics for fHSE=8 MHz and fCPU=180 MHz . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 56. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 57. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 58. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 59. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 60. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 61. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 62. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 63. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 64. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 65. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 66. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 67. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 68. USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 69. USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 70. USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 71. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 72. USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 73. Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 74. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 75. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 76. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 77. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 78. ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 79. ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 80. ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 81. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 160
Table 82. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 160
Table 83. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 84. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 85. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 86. internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 87. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 88. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR - read timings . . . . . . . . . . . . . . . . 168
Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 168
Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 169
Table 92. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 170
Table 93. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 94. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 171
Table 95. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 172

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List of tables STM32F469xx

Table 96. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 173

Table 97. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 98. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 99. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 100. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 101. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 102. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 103. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 104. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 105. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 106. LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 107. Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 108. Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 109. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 110. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 111. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V . . . . . . . . . . . . . 190
Table 112. Dynamic characteristics: SD / MMC characteristics, VDD = 1.71 to 1.9 V . . . . . . . . . . . . 191
Table 113. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 114. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 115. LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 116. WLCSP168 - 168-ball, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 117. WLCSP168 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 118. UFBGA169 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 119. UFBGA169 - Example of PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . 203
Table 120. LQFP176 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 121. UFBGA(176+25) - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 122. UFBGA(176+25) - Example of PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 210
Table 123. TFBGA216 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 124. TFBGA216 - Example of PCB design rules (0.8 mm pitch) . . . . . . . . . . . . . . . . . . . . . . . 214
Table 125. LQFP208 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 126. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 127. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 221
Table 128. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

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STM32F469xx List of figures

List of figures

Figure 1. Incompatible board design for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 2. Incompatible board design for LQFP208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3. UFBGA176 port-to-terminal assignment differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 4. TFBGA216 port-to-terminal assignment differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5. STM32F469xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. STM32F469xx Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7. VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . . . 28
Figure 8. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 29
Figure 9. PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 11. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1 , VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 12. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1 , VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13. STM32F46x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 14. STM32F46x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 15. STM32F46x WLCSP168 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 16. STM32F46x UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 17. STM32F46x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 18. STM32F46x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 19. STM32F46x LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 20. STM32F46x TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 21. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 22. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 23. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 24. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 25. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 26. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 27. Typical VBAT current consumption
(RTC ON / backup SRAM ON and LSE in Low drive mode) . . . . . . . . . . . . . . . . . . . . . . 106
Figure 28. Typical VBAT current consumption
(RTC ON / backup SRAM ON and LSE in High drive mode) . . . . . . . . . . . . . . . . . . . . . . 107
Figure 29. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 30. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 31. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 32. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 33. ACCHSI vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 34. ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 35. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 36. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 37. MIPI D-PHY HS/LP clock lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 38. MIPI D-PHY HS/LP data lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 39. FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 40. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 41. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 42. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 43. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 44. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

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List of figures STM32F469xx

Figure 45. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Figure 46. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 47. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 48. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 49. USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 151
Figure 50. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 51. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 52. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 53. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 54. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 55. Typical connection diagram using the ADC with FT/TT pins featuring analog switch funcion
161
Figure 56. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 162
Figure 57. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 162
Figure 58. 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 59. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 167
Figure 60. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 169
Figure 61. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 62. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 63. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 64. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 65. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 66. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 67. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 68. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 69. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 70. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 71. Quad-SPI SDR timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 72. Quad-SPI DDR timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 73. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 74. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 75. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 76. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 77. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 78. LQFP100 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 79. LQFP100 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 80. LQFP144 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 81. LQFP144 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 82. WLCSP168 - 168-ball, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 83. WLCSP168 - 168-ball, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 84. UFBGA169 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 85. UFBGA169 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 86. LQFP176 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 87. LQFP176 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 88. UFBGA(176+25) - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 89. UFBGA(176+25) - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 90. TFBGA216 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 91. TFBGA216 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 92. LQFP208 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 93. LQFP208 - footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

10/225 DS11189 Rev 8

STM32F469xx Description

1 Description

The STM32F469xx devices are based on the high-performance Arm®(a) Cortex®-M4 32-bit
RISC core operating at a frequency of up to 180 MHz. The Cortex®-M4 core features a
floating-point unit (FPU) single precision which supports all Arm® single-precision data-
processing instructions and data types. It also implements a full set of DSP instructions and
a memory protection unit (MPU) which enhances application security.
The STM32F469xx devices incorporate high-speed embedded memories (Flash memory
up to 2 Mbytes, up to 384 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an
extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB
buses and a 32-bit multi-AHB bus matrix.
All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers,
and a true random number generator (RNG). They also feature standard and advanced
communication interfaces.
• Up to three I2Cs
• Six SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can
be clocked via a dedicated internal audio PLL or via an external clock to allow
synchronization.
• Four USARTs plus four UARTs
• One USB OTG full-speed and one USB OTG high-speed with full-speed capability
(with the ULPI)
• Two CANs
• One SAI serial audio interface
• An SDMMC host interface
• Ethernet and camera interface
• LCD-TFT display controller
• Chrom-ART Accelerator™
• DSI Host.
Advanced peripherals include an SDMMC interface, a flexible memory control (FMC)
interface, a Quad-SPI flash memory, and a camera interface for CMOS sensors. Refer to
Table 2 for the list of peripherals available on each part number.
The STM32F469xx devices operate in the –40 to +105 °C temperature range from a 1.7 to
3.6 V power supply. A dedicated supply input for USB (OTG_FS and OTG_HS) only in full
speed mode, is available on all packages.
The supply voltage can drop to 1.7 V (refer to Section 2.19.2). A comprehensive set of
power-saving modes allows the design of low-power applications.
The STM32F469xx devices are offered in eight packages, ranging from 100 to 216 pins.
The set of included peripherals changes with the device chosen, according to Table 2.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS11189 Rev 8 11/225

46
Description STM32F469xx

These features make the STM32F469xx microcontrollers suitable for a wide range of
applications:
• Motor drive and application control
• Medical equipment
• Industrial applications: PLC, inverters, circuit breakers
• Printers, and scanners
• Alarm systems, video intercom, and HVAC
• Home audio appliances
Figure 5 shows the general block diagram of the device family.

Table 2. STM32F469xx features and peripheral counts

STM32F469Ax

STM32F469Bx

STM32F469Nx
STM32F469Vx

STM32F469Zx

STM32F469Ix
Peripherals

512 512 512 512 512 512

Flash memory in Kbytes 1024 1024 1024 1024 1024 1024
2048 2048 2048 2048 2048 2048

SRAM in System 384 (160+32+128+64)

Kbytes Backup 4
FMC memory controller Yes
Quad-SPI Yes
Ethernet No Yes
General-
10
purpose
Timers Advanced-
2
control
Basic 2
Random number generator Yes
2 (1)
SPI / I S 4/2(full duplex) 6/2(full duplex)(1)
I2C 3
USART/UART 4/3 4/4

Communication USB OTG FS Yes

interfaces USB OTG HS Yes
CAN 2
SAI 1
SDIO Yes
Camera interface Yes
MIPI-DSI Host Yes

12/225 DS11189 Rev 8

STM32F469xx Description

Table 2. STM32F469xx features and peripheral counts (continued)

STM32F469Ax

STM32F469Bx

STM32F469Nx
STM32F469Vx

STM32F469Zx

STM32F469Ix
Peripherals

LCD-TFT Yes
Chrom-ART Accelerator™
Yes
(DMA2D)
GPIOs 71 106 128 131 161 161

12-bit ADC 3
Number of channels 14 20 24 16 24 24
12-bit DAC Yes
Number of channels 2
Maximum CPU frequency 180 MHz
Operating voltage 1.7 to 3.6V(2)
Ambient operating temperature: −40 to 85 °C / −40 to 105 °C
Operating temperatures
Junction temperature: −40 to 105 °C / −40 to 125 °C
UFBGA169 LQFP176
Package LQFP100 LQPF144 LQFP208 TFBGA216
WLCSP168 UFBGA176
1. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
2. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.19.2).

For information on the device errata with respect to the datasheet and reference manual,
refer to the errata sheet (ES0321), available from the STMicroelectronics website
www.st.com.

DS11189 Rev 8 13/225

46
Description STM32F469xx

1.1 Compatibility throughout the family

STM32F469xx devices are not compatible with other STM32F4xx devices.
Figure 1 and Figure 2 show incompatible board designs, respectively, for LQFP176 and
LQFP208 packages (highlighted pins).
The UFBGA176 and TFBGA216 ballouts are compatible with other STM32F4xx devices,
only a few IO port pins are substituted, as shown in Figure 3 and Figure 4.
The LQFP100, LQFP144, and UFBGA169 packages are incompatible with other
STM32F4xx devices.

14/225 DS11189 Rev 8

STM32F469xx Description

1.1.1 LQFP176 package

Figure 1. Incompatible board design for LQFP176 package

VSS
VSS

PI3
PI2
PI3
PI1
135 134 133 135 134 133
132 PI0 132 PI1
131 VDD 131 PI0
130 VSS 130 PH15
129 VCAP2 129 PH14
128 PA13 128 PH13
127 PA12 127 VDD
126 PA11 126 VSS
125 PA10 125 VCAP2
124 PA9 124 PA13
123 PA8 123 PA12
122 PC9 122 PA11
121 PC8 121 PA10
120 PC7 120 PA9
119 PC6 119 PA8
118 VDDUSB 118 PC9
117 VSS 117 PC8
116 PG8 116 PC7
STM32F469xx/479xx 115 PG7 STM32F4xx 115 PC6
LQFP176 114 PG6 LQFP176 114 VDD
113 PG5 113 VSS
112 PG4 112 PG8
111 PG3 111 PG7
110 PG2 110 PG6
109 VSSDSI 109 PG5
108 DSIHOST_D1N 108 PG4
107 DSIHOST_D1P 107 PG3
106 VDD12DSI 106 PG2
105 DSIHOST_CKN 105 PD15
104 DSIHOST_CKP 104 PD14
103 VSSDSI 103 VDD
102 DSIHOST_D0N 102 VSS
101 DSIHOST_D0P 101 PD13
100 VCAPDSI 100 PD12
99 VDDSI 99 PD11
98 PD15 98 PD10
97 PD14 97 PD9
96 VDD 96 PD8
95 VSS 95 PB15
94 PD13 94 PB14
93 PD12 93 PB13
92 PD11 92 PB12
91 PD10 91 VDD
90 PD9 90 VSS
89 PD8 89 PH12
84 85 86 87 88 84 85 86 87 88
PH7
PH8

PH10
PH9

PH11
PB12
PH7

PB13

PB14

PB15

MS38294V2

1. Pins from 85 to 133 are not compatible.

DS11189 Rev 8 15/225

46
Description STM32F469xx

1.1.2 LQFP208 package

Figure 2. Incompatible board design for LQFP208 package

138 PC6 138 PC6

137 VDDUSB 137 VDD
136 VSS 136 VSS
135 PG8 135 PG8
134 PG7 134 PG7
133 PG6 133 PG6
132 PG5 132 PG5
131 PG4 131 PG4
STM32F469xx/479xx 130 PG3 STM32F42x/STM32F43x 130 PG3
LQFP208 129 PG2 LQFP208 129 PG2
128 VSSDSI 128 PK2
127 DSIHOST_D1N 127 PK1
126 DSIHOST_D1P 126 PK0
125 VDD12DSI 125 VSS
124 DSIHOST_CKN 124 VDD
123 DSIHOST_CKP 123 PJ11
122 VSSDSI 122 PJ10
121 DSIHOST_D0N 121 PJ9
120 DSIHOST_D0P 120 PJ8
119 VCAPDSI 119 PJ7
118 VDDDSI 118 PJ6
117 PD15 117 PD15
116 PD14 116 PD14

MS38295V1

1. Pins from 118 to 128 and pin 137 are not compatible.

16/225 DS11189 Rev 8

STM32F469xx Description

1.1.3 UFBGA176 package

Figure 3. UFBGA176 port-to-terminal assignment differences

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A PE3 PE2 PE 1 PE0 PB8 PB5 PG14 PG13 PB 4 PB3 PD7 PC12 PA15 PA14 PA13

PE 6 PB9 PB7 PB6

B PE4 PE5 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12

PI7 PI6 PI5 VDD PDR

C VBA T VDD VDD VDD PG9 PD5 PD1 PI3 NC PA11
_ON

D PC13 PI8 VSS VSS VSS VSS PD4 PD 3 PD2 VDD12 PI1 PA10
PI9 PI4 BOO T0
DSI

DSI DSI
E PC14 PF0 PI10 PI11 HOST_ HOST_ PI0 PA 9
D1P D1N

F PC15 VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP2 PC9 PA 8

G PH0 VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7

H PF2 PF1 PH4 VSS VDD_

PH1 VSS VSS VSS VSS VSS PG8 PC6
DSI USB

PF4 VDD
J NR ST PF3 PH5 VSS VSS VSS VSS VSS VDD PG7 PG6
DSI

K PF6 VDD VCAP

PF7 PF5 VSS VSS VSS VSS VSS PG5 PG4 PG3
DSI

DSI DSI
L PF9 PF8 BYPASS PD15 PG2
PF10 HOST_ HOST_
_REG
CKP CKN
DSI DSI
VCAP PH6 PD14 PD13
M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS HOST_ HOST_
_1
D0P D0N

N VREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10

VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE 8 PE 9 PE11 PE14 PB 12 PB13 PD9 PD8
P

VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PF10 PE12 PE15 PB 10 PB11 PB14 PB15
R

STM32F42xx/3xx STM32F469xx
STM32F40xx/41xx STM32F479xx
PD1 PI3 PI2 PD1 PI3 NC

PD2 PI1 PD2 VDD12 PI1

PH15
DSI

DSI DSI
PH13 PH14 PI0 HOST_ HOST_ PI0
D1P D1N

VSS VCAP2 PC9 VSS VCAP2 PC9

VSS VDD PC8 VSS VDD PC8

VSS VDD_
VSS VDD PG8 PG8
DSI USB

VDD
VDD VDD PG7 VDD PG7
DSI

VCAP
PH12 PG5 PG4 PG5 PG4
DSI

DSI DSI
PH11 PH10 PD15 HOST_ HOST_ PD15
CKP CKN
DSI DSI
PH8 PH9 PD14 HOST_ HOST_ PD14
D0P D0N
MS39403V1

1. The highlighted pins are substituted with dedicated DSI IO pins on STM32F469xx/479xx devices.

DS11189 Rev 8 17/225

46
Description STM32F469xx

1.1.4 TFBGA216 package

Figure 4. TFBGA216 port-to-terminal assignment differences

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A PE4 PE3 PE2 PG14 PE1 PE0 PB8 PB5 PB4 PB3 PD7 PC12 PA15 PA14 PA13

B PE5 PE6 PG13 PB9 PB7 PB6 PG15 PG11 PJ13 PJ12 PD6 PD0 PC11 PC10 PA12

C VBAT PI8 PI4 PK7 PK6 PK5 PG12 PG10 PJ14 PD5 PD3 PD1 PI3 PI2 PA11

D PC13 PF0 PI5 PI7 PI10 PI6 PK4 PK3 PG9 PJ15 PD4 PD2 PH15 PI1 PA10

PDR
E PC14 PF1 PI12 PI9 BOOT0 VDD VDD VDD VDD VCAP2 PH13 PH14 PI0 PA9
ON

F PC15 VSS PI11 VDD VDD VSS VSS VSS VSS VSS VDD PC9 PA8

G PH0 PF2 PI13 PI15 VDD VSS VSS PC8 PC7

H PH1 PF3 PI14 PH4 VDD VSS VSS PG8 PC6

J NRST PF4 PH5 PH3 VDD VSS VSS VDD PG7 PG6

K PF7 PF6 PF5 PH2 VDD VSS VSS VSS VSS VSS VDD PD15 PB13 PD10

BYPASS
L PF10 PF9 PF8 PC3 VSS VDD VDD VDD VDD VCAP1 PD14 PB12 PD9 PD8
-REG

M VSSA PC0 PC1 PC2 PB2 PF12 PG1 PF15 PJ4 PD12 PD13 PG3 PG2 PJ5 PH12

N VREF- PA1 PA0 PA4 PC4 PF13 PG0 PJ3 PE8 PD11 PG5 PG4 PH7 PH9 PH11

P VREF+ PA2 PA6 PA5 PC5 PF14 PJ2 PF11 PE9 PE11 PE14 PB10 PH6 PH8 PH10

R VDDA PA3 PA7 PB1 PB0 PJ0 PJ1 PE7 PE10 PE12 PE15 PE13 PB11 PB14 PB15

STM32F42xx/3xx STM32F469xx
STM32F40xx/41xx STM32F479xx
DSI DSI
VDD PK1 PL2 VDD HOST_ HOST_
D1P D1N

VDDD VSS VDD12

VDD PJ11 PK0 USB DSI DSI

DSI DSI
VDD HOST_
VDD PJ8 PJ10 HOST_
DSI
CKP CKN

DSI DSI
VDD PJ7 PJ9 VDD HOST_ HOST_
D0P D0N

VCAP
VDD PJ6 PD15 VDD PD15
DSI

MSv39404V1

1. The highlighted pins are substituted with dedicated DSI IO pins on STM32F469xx/479xx devices.

18/225 DS11189 Rev 8

STM32F469xx Description

Figure 5. STM32F469xx block diagram

CCM data RAM 64 KB

JTRST, JTDI, CLK, NE[3:0], A[23:0], D[31:0],
JTCK/SWCLK NOE, NWEN, NBL[3:0],
JTDO/SWD, JTDO
JTAG & SW MPUFPU EXT MEM CTRL (FMC)
ETM NVIC SRAM, PSRAM, NOR Flash SDCLKE[1:0], SDNE[1:0],
TRACECK NRAS, NCAS, NADV,
TRACED(3:0) NAND Flash, SDRAM NWAIT, INTR
ARM
Cortex M4 D-BUS CLK,
Quad-SPI BK1_NCS, BK2_NCS,
180MHz I-BUS
D[7:0]
S-BUS

AHB BUS MATRIX

ACCEL/
Flash 1MB

CACHE
Flash 1MB
PHY

D+, D-
VDDUSB = 3.0 to 3.6 V
USB DMA/
ULPI : CLK, D(7:0), OTG HS FIFO
DIR, STP, NXT RNG
SCL/SDA, INT, ID, VBUS 8 Streams SRAM1 160KB HSYNC, VSYNC
GP-DMA2

FIFO FIFO
FIFO CAMERA PIXCK, D(13:0)
SRAM2 32KB ITF
8 Streams
GP-DMA1 SRAM3 128KB USB

PHY
FIFO D+, D-,
OTG FS VDDUSB = 3.0 to 3.6 V,
AHB2
AHB2 180 MHz
180MHz SCL, SDA, INT, ID, VBUS
LCD-TFT FIFO
AHB1 180MHz
DMA-2D FIFO

PA[15:0] @VDDA
USART
GPIO PORT
2MBpsA
POR SUPPLY
RC HS
PB[15:0] GPIO PORT SUPERVISION
USART 2MBpsB Reset
RC LS POR/PDR/
PC[15:0] Int BOR VDDA, VSSA,
GPIO PORT
USART 2MBpsC PLL1,2,3 NRST
PVD
PD[15:0]
USART
GPIO PORT
2MBpsD
@VDDA @VDD
PE[15:0] USART
GPIO PORT
2MBpsE XTAL OSC OSCIN
RESET&
CLOCK 4-26MHz OSCOUT
PF[15:0] MANAGT
GPIO PORT
USART 2MBpsF CTRL
IWDG
PG[15:0] USART
GPIO PORT
2MBpsG Standbyinterface
VBAT = 1.8 to 3.6 V
HCLKx
PCLKx

@VBAT
PH[15:0] USART
GPIO PORT
2MBpsH OSC32_IN
XTAL 32kHz OSC32_OUT
LS

PI[15:0] USART
GPIO 2MBps
PORT I RTC RTC_TAMP1
CRC AWU RTC_TAMP2
PJ[15:0] USART
GPIO PORT
2MBpsJ Backup Register
RTC_OUT
LS

4KB BKPRAM RTC_REFIN

PK[7:0] USART
GPIO PORT
2MBpsK RTC_TS
DSIHOST_D0 P/N TIM2 32b 4 Channels, ETR as AF
DSIHOST_D1 P/N
DSI
PHI

DSIHOST_CK P/N
VDD12DSI, VDDSI, VSSDSI DSI Host TIM3 16b 4 Channels, ETR as AF
VCAPDSI
DSIHOST_TE
DMA2 DMA1 TIM4 16b 4 Channels, ETR as AF
168 AF EXT IT.
USART WKUP
2MBps
TIM5 32b 4 Channels
FIFO

D[7:0]
CMD, CK as AF SDIO / MMC AHB/APB2 AHB/APB1
4 compl. chan. (TIM1_CH1[1:4]N), TIM12 16b 2 Channels as AF
4 chan. (TIM8_CH1[1:4]ETR), 16b
BKIN as AF USART
TIMER 12MBps
/ PWM
4 compl. chan. (TIM1_CH1[1:4]N), TIM13 16b 1 Channels as AF
4 chan. (TIM8_CH1[1:4]ETR), 16b
BKIN as AF USART
TIMER 82MBps
/ PWM
TIM14 16b 1 CH as AF
16b
APB1 45 MHz

2 channels as AF TIMER
USART92MBps smcard RX, TX, SCK,
USART2
irDA CTS, RTS as AF
1 channel as AF 16b
TIMER10
USART 2MBps smcard RX, TX, SCK
USART3
irDA CTS, RTS as AF
16b
1 channel as AF TIMER11
USART 2MBps WWDG
UART4 RX, TX as AF
APB2 90 MHz

RX, TX, SCK, smcard

CTS, RTS as AF
USART USART
2MBps 1
irDA UART5 RX, TX as AF

RX, TX, SCK, smcard

USART USART
2MBps 6 UART7 RX, TX as AF
CTS, RTS as AF irDA
MOSI, MISO, SCK,
NSS as AF USART 2MBps
SPI1/I2S UART8 RX, TX as AF

MOSI, MISO, SCK

MOSI, MISO, SCK,
USARTSPI
2MBps
4 16b SPI2/I2S
NSS as AF TIMER6 NSS/WS, MCK as AF

16b
APB2 60M Hz

MOSI, MISO, SCK,

NSS as AF
USARTSPI5
2MBps TIMER7 SPI3/I2S MOSI, MISO, SCK
NSS/WS, MCK as AF
MOSI, MISO, SCK,
NSS as AF
USARTSPI6
2MBps
SCL, SDA, SMBA as AF
I2C1/SMBUS
FIFO

SD, SCK, FS
Dig. Filter

MCLK as AF USARTSAI 1
2MBps
SCL, SDA, SMBA as AF
I2C2/SMBUS
@VDDA
SCL, SDA, SMBA as AF
V DDREF_ADC I2C3/SMBUS
USART 2MBps
TEMP SENSOR @VDDA
8 analog inputs common
to the 3 ADCs
ADC1 DAC1
ITF bxCAN1 TX, RX
FIFO

8 analog inputs common ADC2 DAC2

to the ADC1 & 2 IF bxCAN2 TX, RX
ADC 3
8 analog inputs to ADC3

DAC1 as AF DAC2 as AF
MS38288V1

1. The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to
APB1 are clocked from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration
in the RCC_DCKCFGR register.

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Functional overview STM32F469xx

2 Functional overview

2.1 Arm® Cortex®-M4 with FPU and embedded flash and SRAM
The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for
embedded systems, developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU core is a 32-bit RISC processor that features exceptional
code-efficiency, delivering the high-performance expected from an Arm® core in the
memory size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions that allow efficient signal processing and
complex algorithm execution. Its single-precision FPU (floating-point unit) speeds up
software development by using metalanguage development tools, while avoiding saturation.
The STM32F46x line is compatible with all Arm® tools and software.
Figure 5 shows the general block diagram of the STM32F46x line.
Note: Cortex®-M4 with FPU core is binary compatible with the Cortex®-M3 core.

2.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator optimized for STM32 industry-standard
Arm® Cortex®-M4 with FPU processors. It balances the inherent performance advantage of
the Arm® Cortex®-M4 with FPU over flash memory technologies, which normally require the
processor to wait for the flash memory at higher frequencies.
To release the processor full 225 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit flash memory. Based on the CoreMark® benchmark, the
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from flash memory at a CPU frequency up to 180 MHz.

2.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU access to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 Gbytes
of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.

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2.4 Embedded flash memory

The devices embed 512 bytes of OTP memory and a flash memory of up to 2 Mbytes
available for storing programs and data.

2.5 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.

2.6 Embedded SRAM

All devices embed:
• Up to 384 Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory)
data RAM
RAM is accessed (read/write) at CPU clock speed with 0 wait states.
• 4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write access, and is retained in Standby or VBAT mode.

2.7 Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB
HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, QUADSPI, AHB,
and APB peripherals) and ensures a seamless and efficient operation even when several
high-speed peripherals work simultaneously.

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Functional overview STM32F469xx

Figure 6. STM32F469xx Multi-AHB matrix

64-Kbyte ARM GP GP MAC USB OTG Chrom ART

DMA1 LCD-TFT
CCM data RAM Cortex-M4 DMA2 Ethernet HS Accelerator(DMA2D)
I-bus

D-bus

S-bus

DMA2D
DMA_PI

DMA_P2
DMA_MEM1

DMA_MEM2

USB_HS_M

LCD-TFT_M
ETHERNET_M
ICODE
Flash

ACCEL
DCODE memory

SRAM1
160 Kbyte
SRAM2
32 Kbyte
SRAM3
128 Kbyte
AHB2
APB1
peripherals
AHB1
peripherals APB2
FMC external
MemCtl

QuadSPI
Bus matrix-S MS33862V1

2.8 DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory, and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.

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The DMA can be used with the main peripherals:

• SPI and I2S
• I2C
• USART
• General-purpose, basic, and advanced-control timers TIMx
• DAC
• SDIO
• Camera interface (DCMI)
• ADC
• SAI1
• QUADSPI.

2.9 Flexible memory controller (FMC)

The flexible memory controller (FMC) includes three memory controllers:
• The NOR/PSRAM memory controller
• The NAND/memory controller
• The synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller

The main features of the FMC controller are the following:

• Interface with static-memory mapped devices including:
– Static random-access memory (SRAM)
– NOR flash memory/OneNAND flash memory
– PSRAM
– NAND flash memory with ECC hardware to check up to 8 Kbytes of data
• Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
• 8-,16-,32-bit data bus width
• Independent Chip Select control for each memory bank
• Independent configuration for each memory bank
• Write FIFO
• Read FIFO for SDRAM controller
• The Maximum FMC_CLK/FMC_SDCLK frequency for synchronous access is HCLK/2.

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.

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Functional overview STM32F469xx

2.10 Quad-SPI memory interface (QUADSPI)

All STM32F469xx devices embed a Quad-SPI memory interface, which is a specialized
communication interface targeting Single, Dual, Quad or Dual-flash SPI memories. It can
work in direct mode through registers, external flash status register polling mode and
memory mapped mode. Up to 256 Mbytes external flash memory are mapped, supporting 8,
16 and 32-bit access. Code execution is supported.
The opcode and the frame format are fully programmable. Communication can be either in
Single Data Rate or Dual Data Rate.

2.11 LCD-TFT controller

The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
• 2 display layers with dedicated FIFO (64x32-bit)
• Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
• Up to 8 Input color formats selectable per layer
• Flexible blending between two layers using alpha value (per pixel or constant)
• Flexible programmable parameters for each layer
• Color keying (transparency color)
• Up to 4 programmable interrupt events.

2.12 DSI Host (DSIHOST)

The DSI Host is a dedicated peripheral for interfacing with MIPI® DSI compliant displays. It
includes a dedicated video interface internally connected to the LTDC and a generic APB
interface that can be used to transmit information to the display.
These interfaces are as follows:
• LTDC interface:
– Used to transmit information in Video Mode, in which the transfers from the host
processor to the peripheral take the form of a real-time pixel stream (DPI).
– Through a customized for mode, this interface can be used to transmit information
in full bandwidth in the Adapted Command Mode (DBI).
• APB slave interface:
– Allows the transmission of generic information in Command mode, and follows a
proprietary register interface.
– Can operate concurrently with either LTDC interface in either Video Mode or
Adapted Command Mode.
• Video mode pattern generator:
– Allows the transmission of horizontal/vertical color bar and D-PHY BER testing
pattern without any kind of stimuli.

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The DSI Host main features:

• Compliant with MIPI® Alliance standards
• Interface with MIPI® D-PHY
• Supports all commands defined in the MIPI® Alliance specification for DCS:
– Transmission of all Command mode packets through the APB interface
– Transmission of commands in low-power and high-speed during Video Mode
• Supports up to two D-PHY data lanes
• Bidirectional communication and escape mode support through data lane 0
• Supports non-continuous clock in D-PHY clock lane for additional power saving
• Supports Ultra Low-Power mode with PLL disabled
• ECC and Checksum capabilities
• Support for End of Transmission Packet (EoTp)
• Fault recovery schemes
• 3D transmission support
• Configurable selection of system interfaces:
– AMBA APB for control and optional support for Generic and DCS commands
– Video Mode interface through LTDC
– Adapted Command Mode interface through LTDC
• Independently programmable Virtual Channel ID in
– Video Mode
– Adapted Command Mode
– APB Slave

Video Mode interfaces features

• LTDC interface color coding mappings into 24-bit interface:
– 16-bit RGB, configurations 1, 2, and 3
– 18-bit RGB, configurations 1 and 2
– 24-bit RGB
• Programmable polarity of all LTDC interface signals
• Maximum resolution is limited by available DSI physical link bandwidth:
– Number of lanes: 2
– Maximum speed per lane: 500 Mbps

Adapted interface features

• Support for sending large amounts of data through the memory_write_start (WMS) and
memory_write_continue (WMC) DCS commands
• LTDC interface color coding mappings into 24-bit interface:
– 16-bit RGB, configurations 1, 2, and 3
– 18-bit RGB, configurations 1 and 2
– 24-bit RGB

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Video mode pattern generator

• Vertical and horizontal color bar generation without LTDC stimuli
• BER pattern without LTDC stimuli

2.13 Chrom-ART Accelerator™ (DMA2D)

The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
• Rectangle filling with a fixed color
• Rectangle copy
• Rectangle copy with pixel format conversion
• Rectangle composition with blending and pixel format conversion.
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.

2.14 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 93 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-
M4 with FPU core.
• Closely coupled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support tail chaining
• Processor state automatically saved on interrupt entry, and restored on interrupt exit,
with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.

2.15 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 23 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 159 GPIOs can be connected
to the 16 external interrupt lines.

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2.16 Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full
temperature range. The application can then select as system clock either the RC oscillator
or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is
detected, the system automatically switches back to the internal RC oscillator and a
software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing
to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL
clock entry is available when necessary (for example if an indirectly used external oscillator
fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 180 MHz while the maximum frequency of the high-speed APB domains is
90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.
The devices embed a dedicated PLL (PLLI2S) and PLLSAI, which allows to achieve audio
class performance. In this case, the I2S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.

2.17 Boot modes

At startup, boot pins are used to select one out of three boot options:
• Boot from user flash
• Boot from system memory
• Boot from embedded SRAM
The bootloader is located in system memory. It is used to reprogram the flash memory
through a serial interface. Refer to application note AN2606 for details.

2.18 Power supply schemes

• VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
• VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset
blocks, RCs, and PLL. VDDA and VSSA must be connected to VDD and VSS,
respectively.
Note: VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to
Section 2.19.2). Refer to Table 3 to identify the packages supporting this option.
• VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
• VDDUSB can be connected either to VDD or an external independent power supply (3.0
to 3.6 V) for USB transceivers.
For example, when the device is powered at 1.8 V, an independent power supply 3.3 V
can be connected to VDDUSB. When the VDDUSB is connected to a separated power
supply, it is independent from VDD or VDDA but it must be the last supply to be provided
and the first to disappear.

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Functional overview STM32F469xx

The following conditions must be respected:

– During the power-on phase (VDD < VDD_MIN), VDDUSB should be always lower
than VDD
– During the power-down phase (VDD < VDD_MIN), VDDUSB should be always lower
than VDD
– VDDUSB rising and falling time rate specifications must be respected.
– In operating mode phase, VDDUSB could be lower or higher than VDD:
–If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by
VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.The VDDUSB
supplies both USB transceivers (USB OTG_HS and USB OTG_FS).
–If only one USB transceiver is used in the application, the GPIOs associated to
the other USB transceiver are still supplied by VDDUSB.
–If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by
VDDUSB are operating between VDD_MIN and VDD_MAX.
–If USB (USB OTG_HS/OTG_FS) is not used and the associated GPIOs powered
by VDDUSB are not used, then VDDUSB should be tied to VSS or VDD (VDDUSB
must not be floating).

Figure 7. VDDUSB connected to an external independent power supply

VDDUSB_MAX
USB functional area
VDDUSB

VDDUSB_MIN
USB non USB non
functional VDD = VDDA functional
area area
VDD_MIN

Power-down time
Power-on Operating mode

MS37590V1

The DSI (Display serial interface) subsystem uses several power supply pins that are
independent from the other supply pins:
• VDDDSI is an independent DSI power supply dedicated for DSI regulator and MIPI
D-PHY. This supply must be connected to global VDD.
• VCAPDSI pin is the output of DSI regulator (1.2 V), which must be connected
externally to VDD12DSI.
• VDD12DSI pin is used to supply the MIPI D-PHY, and to supply clock and data lanes
pins. An external capacitor of 2.2 µF must be connected on VDD12DSI pin.
• VSSDSI pin is an isolated supply ground used for DSI subsystem.
• If DSI functionality is not used at all, then:
– VDDDSI pin must be connected to global VDD.

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– VCAPDSI pin must be connected externally to VDD12DSI but the external

capacitor is no more needed.
– VSSDSI pin must be grounded.

2.19 Power supply supervisor

2.19.1 Internal reset ON

On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On other packages the power supply supervisor is always enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes. The device remains in reset mode when VDD is below a specified threshold,
VPOR/PDR or VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.

2.19.2 Internal reset OFF

This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor VDD and NRST and should maintain
the device in reset mode as long as VDD is below a specified threshold. PDR_ON must be
connected to VSS, as shown in Figure 8.

Figure 8. Power supply supervisor interconnection with internal reset OFF

VDD

STM32F469xx
Application reset
signal (optional)
VBAT

PDR_ON

VSS
PDR not active: 1.7 V < VDD < 3.6 V
MS38296V1

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The VDD specified threshold, below which the device must be maintained under reset, is
1.7 V (see Figure 9).
A comprehensive set of power-saving modes allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
• The brownout reset (BOR) circuitry must be disabled
• The embedded programmable voltage detector (PVD) is disabled
• VBAT functionality is no more available and VBAT pin should be connected to VDD.
All packages allow to disable the internal reset through the PDR_ON signal when connected
to VSS.

Figure 9. PDR_ON control with internal reset OFF

V DD

PDR = 1.7 V

time

Reset by other source than

power supply supervisor

NRST

PDR_ON PDR_ON time

MS19009V7

1. PDR_ON signal to be kept always low.

2.20 Voltage regulator

The regulator has four operating modes:
• Regulator ON
– Main regulator mode (MR)
– Low power regulator (LPR)
– Power-down
• Regulator OFF

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2.20.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
• MR mode used in Run/sleep modes or in Stop modes
– In Run/Sleep mode
The MR mode is used either in the normal mode (default mode) or the overdrive
mode (enabled by software). Different voltage scalings are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
The overdrive mode allows operating at a higher frequency than the normal mode
for a given voltage scaling.
– In Stop modes
The MR can be configured in two ways during stop mode:
MR operates in normal mode (default mode of MR in stop mode).
MR operates in underdrive mode (reduced leakage mode).
• LPR is used in the Stop modes:
The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during stop mode:
– LPR operates in normal mode (default mode when LPR is ON)
– LPR operates in underdrive mode (reduced leakage mode).
• Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Refer to Table 3 for a summary of voltage regulator modes versus device operating modes.
Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin. Refer to
Section 2.18 and Table 126: Package thermal characteristics.
All packages have the regulator ON feature.

Table 3. Voltage regulator configuration mode versus device operating mode(1)

Voltage regulator
Run mode Sleep mode Stop mode Standby mode
configuration

Normal mode MR MR MR or LPR -

Over-drive mode(2) MR MR - -
Under-drive mode - - MR or LPR -
Power-down mode - - - Yes
1. ‘-’ means that the corresponding configuration is not available.
2. The overdrive mode is not available when VDD = 1.7 to 2.1 V.

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2.20.2 Regulator OFF

This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency. Refer to Section A.1: Operating
conditions.The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling
capacitors. Refer to Section 2.18.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as a power-on reset on V12 power domain.
In regulator OFF mode, the following features are no more supported:
• PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain, which is not reset by the NRST pin.
• As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or prereset is required.
• The overdrive and underdrive modes are not available.
• The Standby mode is not available.

Figure 10. Regulator OFF

V12
External VCAP_1/2 power
supply supervisor Application reset
Ext. reset controller active signal (optional)
when VCAP_1/2 < Min V12

VDD
PA0 NRST
VDD

BYPASS_REG
V12

VCAP_1

VCAP_2
ai18498V3

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The following conditions must be respected:

• VDD must always be higher than VCAP_1 and VCAP_2 to avoid current injection between
power domains.
• If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.7 V, then PA0 must be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 11).
• Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 can be asserted low externally (see
Figure 12).
• If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
Note: The minimum value of V12 depends on the maximum frequency targeted in the application
(see Section A.1: Operating conditions).

Figure 11. Startup in regulator OFF: slow VDD slope

- power-down reset risen after VCAP_1 , VCAP_2 stabilization

VDD

PDR = 1.7 or 1.8 V VCAP_1, VCAP_2

V12
Min V12

time

NRST

PA0

time ai18491g

1. This figure is valid whatever the internal reset mode (ON or OFF).

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Figure 12. Startup in regulator OFF mode: fast VDD slope

- power-down reset risen before VCAP_1 , VCAP_2 stabilization
VDD

PDR = 1.7 or 1.8 V (2)

VCAP_1, VCAP_2
V12
Min V12

time
NRST
PA0

time ai18492f

1. This figure is valid whatever the internal reset mode (ON or OFF).

2.20.3 Regulator ON/OFF and internal reset ON/OFF availability

Table 4. Regulator ON/OFF and internal reset ON/OFF availability

Package Regulator ON Regulator OFF Internal reset ON Internal reset OFF

WLCSP168
UFBGA169
Yes No
LQFP144
LQFP208 Yes Yes
PDR_ON set to VDD PDR_ON set to VSS
LQFP176 Yes Yes
UFBGA176 BYPASS_REG set BYPASS_REG set
TFBGA216 to VSS to VDD

LQFP100 Yes No Yes No

2.21 Real-time clock (RTC), backup SRAM, and backup registers

The backup domain includes:
• The real-time clock (RTC)
• 4 Kbytes of backup SRAM
• 20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-
coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC provides a programmable alarm and programmable
periodic interrupts with wake-up from Stop and Standby modes. The subseconds value is
also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC

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has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary autoreload downcounter with programmable resolution is available
and allows automatic wake-up and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data,
which need to be retained in VBAT and standby mode. This memory area is disabled by
default to minimize power consumption (see Section 2.22). It can be enabled by software.
The backup registers are 32-bit registers used to store 80 bytes of user application data
when VDD power is not present. Backup registers are not reset by a system, a power reset,
or when the device wakes up from the Standby mode (see Section 2.22).
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
Like backup SRAM, the RTC and backup registers are supplied through a switch that is
powered either from the VDD supply when present or from the VBAT pin.

2.22 Low-power modes

The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wake-up sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled.
The voltage regulator can be put either in main regulator mode (MR) or in low-power
mode (LPR). Both modes can be configured as follows (see Table 5):
– Normal mode (default mode when MR or LPR is enabled)
– Underdrive mode.
The device can be woken up from the Stop mode by any of the EXTI lines (the EXTI
line source can be one of the 16 external lines, the PVD output, the RTC alarm / wake-
up / tamper / time stamp events, the USB OTG FS/HS wake-up or the Ethernet wake-
up).

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Table 5. Voltage regulator modes in stop mode

Voltage regulator
Main regulator (MR) Low-power regulator (LPR)
configuration

Normal mode MR ON LPR ON

Under-drive mode MR in under-drive mode LPR in under-drive mode

• Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on the WKUP pin, or an RTC alarm / wake-up / tamper /time stamp event
occurs.
The standby mode is not supported when the embedded voltage regulator is bypassed
and the 1.2 V domain is controlled by an external power.

2.23 VBAT operation

The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when no external battery neither an external supercapacitor are
present.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers, and the backup SRAM.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no
more available and VBAT pin should be connected to VDD.

2.24 Timers and watchdogs

The devices include two advanced-control timers, eight general-purpose timers, two basic
timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 6 compares the features of the advanced-control, general-purpose and basic timers.

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Table 6. Timer feature comparison

Max Max
DMA Capture/
Timer Counter Counter Prescaler Complementary interface timer
Timer request compare
type resolution type factor output clock clock
generation channels
(MHz) (MHz)(1)

Up, Any integer

Advanced TIM1,
16-bit Down, between 1 Yes 4 Yes 90 180
control TIM8
Up/down and 65536
Up, Any integer
TIM2,
32-bit Down, between 1 Yes 4 No 45 90/180
TIM5
Up/down and 65536
Up, Any integer
TIM3,
16-bit Down, between 1 Yes 4 No 45 90/180
TIM4
Up/down and 65536

Any integer
TIM9 16-bit Up between 1 No 2 No 90 180
General and 65536
purpose TIM10 Any integer
, 16-bit Up between 1 No 1 No 90 180
TIM11 and 65536

Any integer
TIM12 16-bit Up between 1 No 2 No 45 90/180
and 65536
TIM13 Any integer
, 16-bit Up between 1 No 1 No 45 90/180
TIM14 and 65536

Any integer
TIM6,
Basic 16-bit Up between 1 Yes 0 No 45 90/180
TIM7
and 65536

1. The maximum timer clock is either 90 or 180 MHz depending on the TIMPRE bit configuration in the
RCC_DCKCFGR register.

2.24.1 Advanced-control timers (TIM1, TIM8)

The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge- or center-aligned modes)
• One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.

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2.24.2 General-purpose timers (TIMx)

There are ten synchronizable general-purpose timers embedded in the STM32F46x devices
(see Table 6 for differences).
• TIM2, TIM3, TIM4, TIM5
The STM32F46x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3,
and TIM4.The TIM2 and TIM5 timers are based on a 32-bit autoreload up/down
counter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit
autoreload up/down counter and a 16-bit prescaler. They all feature 4 independent
channels for input capture/output compare, PWM, or one-pulse mode output. This
gives up to 16 input capture/output compare/PWMs on the largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
• TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit autoreload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9
and TIM12 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers. They can also be used as simple time bases.

2.24.3 Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.

2.24.4 Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.

2.24.5 Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.

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2.24.6 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
• a 24-bit downcounter
• autoreload capability
• maskable system interrupt generation when the counter reaches 0
• programmable clock source.

2.25 Inter-integrated circuit interface (I2C)

Up to three I²C bus interfaces can operate in multimaster and slave modes. They can
support the standard (up to 100 kHz), and fast (up to 400 kHz) modes. They support the
7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC
generation/verification is embedded.
The I²C bus interfaces can be served by DMA and support SMBus 2.0/PMBus.
The devices also include programmable analog and digital noise filters (see Table 7).

Table 7. Comparison of I2C analog and digital filters

Filter Analog Digital

Pulse width of suppressed spikes ≥ 50 ns Programmable length, from one to fifteen I2C peripheral clocks

2.26 Universal synchronous/asynchronous receiver transmitters

(USART)
The devices embed four universal synchronous/asynchronous receiver transmitters
(USART1, USART2, USART3, and USART6) and four universal asynchronous receiver
transmitters (UART4, UART5, UART7, and UART8).
These six interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to
communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate
at up to 5.62 Mbit/s.
USART1, USART2, USART3, and USART6 also provide hardware management of the CTS
and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication
capability. All interfaces can be served by the DMA controller.

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Table 8. USART feature comparison(1)

Max. baud rate in Mbit/s
Standard Modem SPI Smartcard APB
Name LIN irDA
features (RTS/CTS) master (ISO 7816) Oversampling Oversampling mapping
by 16 by 8

APB2
USART1 X X X X X X 5.62 11.25 (max.
90 MHz)
APB1
USART2 X X X X X X 2.81 5.62 (max.
45 MHz)
APB1
USART3 X X X X X X 2.81 5.62 (max.
45 MHz)
APB1
UART4 X - X - X - 2.81 5.62 (max.
45 MHz)
APB1
UART5 X - X - X - 2.81 5.62 (max.
45 MHz)
APB2
USART6 X X X X X X 5.62 11.25 (max.
90 MHz)
APB1
UART7 X - X - X - 2.81 5.62 (max.
45 MHz)
APB1
UART8 X - X - X - 2.81 5.62 (max.
45 MHz)
1. X = feature supported.

2.27 Serial peripheral interface (SPI)

The devices feature up to six SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 45 Mbits/s,
SPI2 and SPI3 can communicate at up to 22.5 Mbit/s. The 3-bit prescaler gives 8 master
mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the
DMA controller.
The SPI interface can be configured to operate in TI mode for communications in master
mode and slave mode.

2.28 Inter-integrated sound (I2S)

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be
operated in master or slave mode, in full duplex and simplex communication modes, and
can be configured to operate with a 16-/32-bit resolution as an input or output channel.

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Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of
the I2S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.
Note: For I2S2 full-duplex mode, I2S2_CK and I2S2_WS signals can be used only on GPIO Port
B and GPIO Port D.

2.29 Serial Audio interface (SAI1)

The serial audio interface (SAI1) is based on two independent audio subblocks which can
operate as transmitter or receiver with their FIFO. Many audio protocols are supported by
each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both subblocks
can be configured in master or in slave mode.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two subblocks can be configured in synchronous mode when full-duplex mode is
required.
SAI1 can be served by the DMA controller.

2.30 Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows
to achieve error-free I2S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU, USB, and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 kHz to 192 kHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the
I2S/SAI flow with an external PLL (or Codec output).

2.31 Audio and LCD PLL(PLLSAI)

An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the
PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or
11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.
The PLLSAI is also used to generate the LCD-TFT clock.

2.32 Secure digital input/output interface (SDIO)

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

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The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital
protocol Rev1.1.

2.33 Ethernet MAC interface with dedicated DMA and IEEE 1588
support
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
The devices include the following features:
• Supports 10 and 100 Mbit/s rates
• A dedicated DMA controller allowing high-speed transfers between the dedicated
SRAM and the descriptors (see the STM32F4xx reference manual for details)
• Tagged MAC frame support (VLAN support)
• Half-duplex (CSMA/CD) and full-duplex operation
• MAC control sublayer (control frames) support
• 32-bit CRC generation and removal
• Several address filtering modes for physical and multicast address (multicast and
group addresses)
• 32-bit status code for each transmitted or received frame
• Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
• Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
• Triggers interrupt when system time becomes greater than target time

2.34 Controller area network (bxCAN)

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for each CAN.

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2.35 Universal serial bus on-the-go full-speed (OTG_FS)

The device embeds one USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint settings and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The main features are:
• Combined Rx and Tx FIFO size of 1.28 KB with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
• 12 host channels with periodic OUT support
• Software configurable to OTG1.3 and OTG2.0 modes of operation
• USB 2.0 LPM (Link Power Management) support
• Internal FS OTG PHY support
• HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected.

2.36 Universal serial bus on-the-go high-speed (OTG_HS)

The device embeds a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral.
The USB OTG HS supports both full-speed and high-speed operations. It integrates the
transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI)
for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an
external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
2.0 specification. It has software-configurable endpoint settings and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The main features are:
• Combined Rx and Tx FIFO size of 4 KB with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 8 bidirectional endpoints
• 16 host channels with periodic OUT support
• Software configurable to OTG1.3 and OTG2.0 modes of operation
• USB 2.0 LPM (Link Power Management) support
• Internal FS OTG PHY support
• External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
• Internal USB DMA
• HNP/SNP/IP inside (no need for any external resistor)
• for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected

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2.37 Digital camera interface (DCMI)

The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:
• Programmable polarity for the input pixel clock and synchronization signals
• Parallel data communication can be 8-, 10-, 12- or 14-bit
• Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
• Supports continuous mode or snapshot (a single frame) mode
• Capability to automatically crop the image black & white.

2.38 True random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.

2.39 General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 90 MHz.

2.40 Analog-to-digital converters (ADCs)

Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
• Simultaneous sample and hold
• Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.

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2.41 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the
sensor output voltage into a digital value. When the temperature sensor and VBAT
conversion are enabled at the same time, only VBAT conversion is performed.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.

2.42 Digital-to-analog converter (DAC)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital interface supports the following features:
• two DAC converters: one for each output channel
• 8-bit or 10-bit monotonic output
• left or right data alignment in 12-bit mode
• synchronized update capability
• noise-wave generation
• triangular-wave generation
• dual DAC channel independent or simultaneous conversions
• DMA capability for each channel
• external triggers for conversion
• input voltage reference VREF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.

2.43 Serial wire JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be reused as GPIO with an alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.

2.44 Embedded Trace Macrocell™

The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F46x through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or

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any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third-party debugger software tools.

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3 Pinouts and pin description

Figure 13. STM32F46x LQFP100 pinout

BOOT0

VCAP2
PC12

PC10
PC11

PA15
PA14
VDD

VDD
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 PA13
VSS 2 74 PA12
VBAT 3 73 PA11
PC13 4 72 PA10
PC14 5 71 PA9
PC15 6 70 PA8
VSS 7 69 PC9
VDD 8 68 PC8
PH0 9 67 PC7
PH1 10 66 PC6
NRST 11 65 VDDUSB
PC0 12 64 DSIHOST_D1N
PC1 13 LQFP100 63 DSIHOST_D1P
PC2 14 62 VDD12DSI
PC3 15 61 DSIHOST_CKN
VSSA 16 60 DSIHOST_CKP
VREF+ 17 59 VSSDSI
VDDA 18 58 DSIHOST_D0N
PA0 19 57 DSIHOST_D0P
PA1 20 56 VCAPDSI
PA2 21 55 VDDDSI
PA3 22 54 PD15
VSS 23 53 PD14
VDD 24 52 PD10
PA4 25 51 PD9
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PB0
PB1
PB2
PE7
PE8
PE9
PE10

PE12
PE13
PE14
PE15
PB10

VCAP1
VSS
VDD
PB12
PB13
PB14
PB15
PD8
PA5
PA6
PA7

PE11

PB11

MS40560V1

1. The above figure shows the package top view.

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Pinouts and pin description STM32F469xx

Figure 14. STM32F46x LQFP144 pinout

PDR_ON

BOOT0

PG15

PG12

PG10

PC12

PC10
PG11

PC11

PA15
PA14
VDD

VDD

VDD

VDD
VSS

PG9

VSS

VSS
PD6

PD5
PD4
PD3
PD2
PD1
PD0
PE2

PE1
PE0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120

109
119
118
117
116
115
114
113
112

110
111
PE3 1 108 VCAP2
PE4 2 107 PA13
PE5 3 106 PA12
PE6 4 105 PA11
VBAT 5 104 PA10
PC13 6 103 PA9
PC14 7 102 PA8
PC15 8 101 PC9
PF0 9 100 PC8
PF1 10 99 PC7
PF2 11 98 PC6
PF3 12 97 VDDUSB
PF4 13 96 PG8
PF5 14 95 PG7
VSS 15 94 PG6
VDD 16 93 PG5
PF10 17 92 PG4
PH0 18 91 PG3
PH1 19 LQFP144 90 PG2
NRST 20 89 DSIHOST_D1N
PC0 21 88 DSIHOST_D1P
PC1 22 87 VDD12DSI
PC2 23 86 DSIHOST_CKN
PC3 24 85 DSIHOST_CKP
VDD 25 84 VSSDSI
VSSA 26 83 DSIHOST_D0N
VREF+ 27 82 DSIHOST_D0P
VDDA 28 81 VCAPDSI
PA0 29 80 VDDDSI
PA1 30 79 PD15
PA2 31 78 PD14
PA3 32 77 VDD
VSS 33 76 VSS
VDD 34 75 PD12
PA4 35 74 PD11
PA5 36 73 PD10
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PC4
PC5
PB0
PB1
PB2

PF12
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10

PE12
PE13
PE14
PE15
PB10

VCAP1
VDD
PB12
PB13
PB14
PB15
PD8
PD9
PA6
PA7

PF11

PE11

PB11

MS40561V2

1. The above figure shows the package top view.

48/225 DS11189 Rev 8

STM32F469xx Pinouts and pin description

Figure 15. STM32F46x WLCSP168 pinout

12 11 10 9 8 7 6 5 4 3 2 1

A PI7 VDD PE0 PB7 PB3 VDD PG12 PD7 VSS PD1 PA15 PI2

B PE5 PI6 VSS PB8 PB5 VSS PG11 VDD PD4 PC11 PI3 PH13

C VBAT PE4 PI5 PE1 PB4 PG10 PD5 PD2 PC12 PI1 VDD VSS

PDR_
D PC13 PE6 PI4 PG15 PG9 PD3 PC10 PA14 PH14 VCAP2 PA13
ON

E PC15 PC14 PE3 PB9 PG13 PD6 PD0 PI0 PH15 PA10 PA9 PA8

VDD
F VSS PI11 PI10 PE2 BOOT0 PA11 PA12 PC9 PC8 PC6 VSS
USB

G PF2 VDD PF0 PI9 PB6 PC7 PG8 PG2 PG3 PG6 PG4 PG5

DSI DSI
VSS
H PF5 PF3 PF1 NRST PF15 VSS PG7 PB12 PD13 HOST HOST
DSI
_D1P _D1N

DSI DSI DSI

J VDD VSS PF4 PC0 PA7 PF13 PG0 PE14 PD11 HOST HOST HOST
_D0N _CKN _CKP

DSI
VDD12 VCAP
PH1 PH0 PF10 PA1 PH5 PF11 PE9 PB11 PB13 HOST
K _D0P
DSI DSI

VDD
L PC1 VSSA PA0 PA2 PA5 PF14 PE13 PH9 PD8 PD14 PD15
DSI

PF12 PE8 PE12 PH8 PH10 PD10 PD12 VSS

M VDDA PH2 PH4 PA4

N PH3 VSS PA3 PB1 VSS PE7 PE11 PB10 VCAP1 PH11 PB15 PD9

P VDD PA6 PB0 PB2 VDD PG1 PE10 PE15 VSS VDD PH12 PB14

MSv35729V2

1. The above figure shows the package bottom view.

DS11189 Rev 8 49/225

82
Pinouts and pin description STM32F469xx

Figure 16. STM32F46x UFBGA169 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13

A PI6 PI5 PE1 PE0 BOOT0 PG13 PG12 PD7 PC12 PA14 PA13 PA12 PA11

B PI7 PE2 PI4 PB7 PB3 PG11 PD5 PD2 PC11 PAI3 PA15 PI2 PI0

PDR_
C PE3 PE4
ON
PB9 PB6 PD4 PD1 PD3 PD0 PC10 PI1 PH15 PH14

D PE5 PE6 VDD PB8 PB5 PB4 PD6 PA8 PH13 VDD VSS VCAP2 PG8

E PC14 PI9 VSS PI10 VBAT PG9 PG10 PA9 PA10 PC8 PG7 PG5 PG4

F PC15 PI11 PF0 VDD VSS PG15 VDD VSS PC6 PC7 PG6 PG3 PG2

DSI DSI
VDD
G PH1 PH0 PF1 PC13 PF2 PE8 VSS VDD VSS PC9 HOST_ HOST_
USB
D1P D1N

DSI DSI_
H PF10 NRST PF5 PF3 PF14 PE9 PE10 PH8 PH9 PH12 VSSDSI HOST_ HOST
CKP CKN

DSI DSI
VDD12
J VSS VSSA VDDA VDD PA0 VSS VSS PE13 PH10 VSS
DSI
HOST_ HOST_
D0P D0N

VCAP VDD
K PA1 PA2 PA3 PA7 PB1 VDD PE11 PE14 PH11 VDD VSSDSI
DSI DSI

L PH3 PH2 PH5 PF4 PB2 VDD PE12 PE15 VDD PD8 PD10 PD14 PD15

M PC0 PH4 PA5 PF13 PF11 PF15 PG1 PB10 VSS PD9 PD11 PD13 PD12

N PC1 PA4 PA6 PB0 PF12 PG0 PE7 PB11 VCAP1 PB12 PB13 PB14 PB15

MSv35730V2

1. The above figure shows the package top view.

50/225 DS11189 Rev 8

STM32F469xx Pinouts and pin description

Figure 17. STM32F46x UFBGA176 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A PE3 PE2 PE 1 PE0 PB8 PB5 PG 14 PG 13 PB 4 PB3 PD7 PC12 PA15 PA14 P A 13

B PE4 PE5 PE6 PB9 PB7 PB6 PG 15 PG 12 PG 11 PG 10 PD6 PD0 PC11 PC10 PA12

P I7 P I6 P I5 PDR
VBAT VDD VDD VDD VDD PG9 PD5 PD1 P I3 NC PA11
C _ON

D P C 13 PI8 VSS BOOT0 VSS VSS VSS PD4 PD 3 PD2 VDD12 PI1 PA10
P I9 P I4
DSI

DSI DSI
E P C 14 PF0 PI10 P I1 1 HOST_ HOST_ P I0 PA 9
D1P D1N

F P C 15 VSS VDD PH2 VSS VSS VSS VSS VSS V SS VCAP2 PC9 PA 8

VSS VSS VSS VSS VSS V SS VDD PC8 PC7

G PH0 VS S V DD PH3

H PF2 PF1 PH4 VSS VDD_

PH1 VSS VSS VSS VSS VSS PG8 PC6
DSI USB

P F4 VDD
J NRST PF3 PH5 VSS VSS VSS VSS VSS VDD PG7 PG6
DSI

K PF6 V DD VCAP
PF7 PF5 VSS VSS VSS VSS VSS PG5 PG4 PG3
DSI

DSI DSI
L PF9 PF8 BYPASS PD15 PG2
PF10 HOST_ HOST_
_REG
CKP CKN

DSI DSI
VCAP PH6
M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS HOST_ HOST_ PD14 PD13
_1
D0P D0N

N VREF- PA1 PA0 PF13 PG0 V DD V DD V DD PE13 PH7 PD12 PD11 P D 10

PA4 PC4

VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE 8 PE 9 P E 11 PE14 PB 1 2 PB13 PD9 PD8
P

VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 P B 14 P B 15
R

MS39400V2

1. The above figure shows the package top view.

DS11189 Rev 8 51/225

82
Pinouts and pin description STM32F469xx

Figure 18. STM32F46x LQFP176 pinout

PDR_ON

BOOT0

PG15

PG14
PG13
PG12

PG10

PC12

PC10
PG11

PC11

PA15
PA14
VDD

VDD

VDD

VDD
VSS

PG9

VSS

VSS
PD7
PD6

PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
PI7
PI6
PI5
PI4

PI3
PI1
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153

141
140
152
151
150
149
148
147
146
145
144
143
142

139
138
137
136
135
134
133
PE2 1 132 PI0
PE3 2 131 VDD
PE4 3 130 VSS
PE5 4 129 VCAP2
PE6 5 128 PA13
VBAT 6 127 PA12
PI8 7 126 PA11
PC13 8 125 PA10
PC14 9 124 PA9
PC15 10 123 PA8
PI9 11 122 PC9
PI10 12 121 PC8
PI11 13 120 PC7
VSS 14 119 PC6
VDD 15 118 VDDUSB
PF0 16 117 VSS
PF1 17 116 PG8
PF2 18 115 PG7
PF3 19 114 PG6
PF4 20 113 PG5
PF5 21 112 PG4
VSS
VDD
22
23
LQFP176 111
110
PG3
PG2
PF6 24 109 VSSDSI
PF7 25 108 DSIHOST_D1N
PF8 26 107 DSIHOST_D1P
PF9 27 106 VDD12DSI
PF10 28 105 DSIHOST_CKN
PH0 29 104 DSIHOST_CKP
PH1 30 103 VSSDSI
NRST 31 102 DSIHOST_D0N
PC0 32 101 DSIHOST_D0P
PC1 33 100 VCAPDSI
PC2 34 99 VDDDSI
PC3 35 98 PD15
VDD 36 97 PD14
VSSA 37 96 VDD
VREF+ 38 95 VSS
VDDA 39 94 PD13
PA0 40 93 PD12
PA1 41 92 PD11
PA2 42 91 PD10
PH2 43 90 PD9
PH3 44 89 PD8
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

80
69
70
71
72
73
74
75
76
77
78
79

88
81
82
83
84
85
86
87
PH4
PH5

VDD

PC4
PC5
PB0
PB1
PB2

PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10

PE12
PE13
PE14
PE15
PB10

VCAP_1
VDD
PH6
PH7
PB12
PB13
PB14
PB15
BYPASS_REG
PA3

PA4
PA5
PA6
PA7

PF11

PE11

PB11

MS33870V4

1. The above figure shows the package top view.

52/225 DS11189 Rev 8

STM32F469xx Pinouts and pin description

Figure 19. STM32F46x LQFP208 pinout

PDR_ON

BOOT0

PG15

PG14
PG13
PG12

PG10

PC12

PC10
PG11

PC11

PA15
PA14
PJ15
PJ14
PJ13
PJ12
VDD

VDD

VDD

VDD
VSS

VSS

PG9

VSS
PD7
PD6

PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8

PB7
PB6
PB5
PB4
PB3

PK7
PK6
PK5
PK4
PK3
PI7
PI6
PI5
PI4

PI3
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
PE2 1 156 PI2
PE3 2 155 PI1
PE4 3 154 PI0
PE5 4 153 PH15
PE6 5 152 PH14
VBAT 6 151 PH13
PI8 7 150 VDD
PC13 8 149 VSS
PC14 9 148 VCAP2
PC15 10 147 PA13
PI9 11 146 PA12
PI10 12 145 PA11
PI11 13 144 PA10
VSS 14 143 PA9
VDD 15 142 PA8
PF0 16 141 PC9
PF1 17 140 PC8
PF2 18 139 PC7
PI12 19 138 PC6
PI13 20 137 VDDUSB
PI14 21 136 VSS
PF3 22 135 PG8
PF4 23 134 PG7
PF5 24 133 PG6
VSS 25 132 PG5
VDD
PF6
26
27 LQFP208 131
130
PG4
PG3
PF7 28 129 PG2
PF8 29 128 VSSDSI
PF9 30 127 DSIHOST_D1N
PF10 31 126 DSIHOST_D1P
PH0 32 125 VDD12DSI
PH1 33 124 DSIHOST_CKN
NRST 34 123 DSIHOST_CKP
PC0 35 122 VSSDSI
PC1 36 121 DSIHOST_D0N
PC2 37 120 DSIHOST_D0P
PC3 38 119 VCAPDSI
VDD 39 118 VDDDSI
VSSA 40 117 PD15
VREF+ 41 116 PD14
VDDA 42 115 VDD
PA0 43 114 VSS
PA1 44 113 PD13
PA2 45 112 PD12
PH2 46 111 PD11
PH3 47 110 PD10
PH4 48 109 PD9
PH5 49 108 PD8
PA3 50 107 PB15
VSS 51 106 PB14
VDD 52 105 PB13
100
101
102
103
104
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
PC4
PC5
VDD
VSS
PB0
PB1
PB2

VSS

PE9
VSS
PI15
PJ0
PJ1
PJ2
PJ3
PJ4

PF12

VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8

VDD
PE10

PE12
PE13
PE14
PE15
PB10

VCAP1
VSS
VDD
PJ5
PH6
PH7
PH8
PH9
PH10

PH12
VDD
PB12
PA4
PA5
PA6
PA7

PF11

PE11

PB11

PH11

MSv33876V5

1. The above figure shows the package top view.

DS11189 Rev 8 53/225

82
Pinouts and pin description STM32F469xx

Figure 20. STM32F46x TFBGA216 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A PE4 PE3 PE2 PG14 PE1 PE0 PB8 PB5 PB4 PB3 PD7 PC12 PA15 PA14 PA13

B PE5 PE6 PG13 PB9 PB7 PB6 PG15 PG11 PJ13 PJ12 PD6 PD0 PC11 PC10 PA12

C VBAT PI8 PI4 PK7 PK6 PK5 PG12 PG10 PJ14 PD5 PD3 PD1 PI3 PI2 PA11

D PC13 PF0 PI5 PI7 PI10 PI6 PK4 PK3 PG9 PJ15 PD4 PD2 PH15 PI1 PA10

PDR
E PC14 PF1 PI12 PI9 BOOT0 VDD VDD VDD VDD VCAP2 PH13 PH14 PI0 PA9
ON

DSI DSI
F PC15 VSS PI11 VDD VDD VSS VSS VSS VSS VSS VDD HOST_ HOST_ PC9 PA8
D1P D1N

VDDD VSS VDD12

G PH0 PF2 PI13 PI15 VDD VSS VSS PC8 PC7
USB DSI DSI

DSI DSI
VDD
H PH1 PF3 PI14 PH4 VDD VSS VSS HOST_ HOST_ PG8 PC6
DSI
CKP CKN

DSI DSI
J NRST PF4 PH5 PH3 VDD VSS VSS VDD HOST_ HOST_ PG7 PG6
D0P D0N

VCAP
K PF7 PF6 PF5 PH2 VDD VSS VSS VSS VSS VSS VDD PD15 PB13 PD10
DSI

BYPASS-
L PF10 PF9 PF8 PC3 VSS VDD VDD VDD VDD VCAP1 PD14 PB12 PD9 PD8
REG

M VSSA PC0 PC1 PC2 PB2 PF12 PG1 PF15 PJ4 PD12 PD13 PG3 PG2 PJ5 PH12

N VREF- PA1 PA0 PA4 PC4 PF13 PG0 PJ3 PE8 PD11 PG5 PG4 PH7 PH9 PH11

P VREF+ PA2 PA6 PA5 PC5 PF14 PJ2 PF11 PE9 PE11 PE14 PB10 PH6 PH8 PH10

R VDDA PA3 PA7 PB1 PB0 PJ0 PJ1 PE7 PE10 PE12 PE15 PE13 PB11 PB14 PB15

MSv33871V4

1. The above figure shows the package top view.

54/225 DS11189 Rev 8

STM32F469xx Pinouts and pin description

Table 9. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after
Pin name
reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
TTa 3.3 V tolerant I/O directly connected to analog parts
I/O structure
B Dedicated BOOT0 pin
RST Bidirectional reset pin with weak pull-up resistor

Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset

Alternate
Functions selected through GPIOx_AFR registers
functions

Additional
Functions directly selected/enabled through peripheral registers
functions

DS11189 Rev 8 55/225

82
Pinouts and pin description STM32F469xx

Table 10. STM32F469xx pin and ball definitions

Pin number

I/O structures
Pin types
UFBGA176(2)
Pin name
WLCSP168
UFBGA169

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function after Alternate functions
functions
reset)(1)

TRACECLK, SPI4_SCK,
SAI1_MCLK_A,
1 144 B2 F9 A2 1 1 A3 PE2 I/O FT - QUADSPI_BK1_IO2, -
ETH_MII_TXD3, FMC_A23,
EVENTOUT

NC TRACED0, SAI1_SD_B,
(3) 1 C1 E10 A1 2 2 A2 PE3 I/O FT - -
FMC_A19, EVENTOUT

TRACED1, SPI4_NSS,
NC SAI1_FS_A, FMC_A20,
(3) 2 C2 C11 B1 3 3 A1 PE4 I/O FT - -
DCMI_D4, LCD_B0,
EVENTOUT

TRACED2, TIM9_CH1,
NC SPI4_MISO, SAI1_SCK_A,
(3) 3 D1 B12 B2 4 4 B1 PE5 I/O FT - -
FMC_A21, DCMI_D6,
LCD_G0, EVENTOUT

TRACED3, TIM9_CH2,
NC SPI4_MOSI, SAI1_SD_A,
(3) 4 D2 D11 B3 5 5 B2 PE6 I/O FT - -
FMC_A22, DCMI_D7,
LCD_G1, EVENTOUT
2 - - - - - - G6 VSS S - - - -

- - - - - - - F5 VDD S - - - -

3 5 E5 C12 C1 6 6 C1 VBAT S - - - -

(4) RTC_TAMP1/
- - - - D2 7 7 C2 PI8 I/O FT (5) EVENTOUT RTC_TAMP2/
RTC_TS

(4) RTC_TAMP1/
4 6 G4 D12 D1 8 8 D1 PC13 I/O FT (5) EVENTOUT RTC_TS/
RTC_OUT
(4)
PC14-OSC32_IN
5 7 E1 E11 E1 9 9 E1 I/O FT (5) EVENTOUT OSC32_IN
(PC14)

PC15- (4)
6 8 F1 E12 F1 10 10 F1 OSC32_OUT I/O FT (5) EVENTOUT OSC32_OUT
(PC15)

- - - - - - - G5 VDD S - - - -

CAN1_RX, FMC_D30,
- - E2 G9 D3 11 11 E4 PI9 I/O FT -
LCD_VSYNC, EVENTOUT

ETH_MII_RX_ER,
- - E4 F10 E3 12 12 D5 PI10 I/O FT FMC_D31, LCD_HSYNC, -
EVENTOUT

LCD_G6,
- - F2 F11 E4 13 13 F3 PI11 I/O FT OTG_HS_ULPI_DIR, -
EVENTOUT

- - F5 F12 F2 14 14 F2 VSS S - - - -

56/225 DS11189 Rev 8

STM32F469xx Pinouts and pin description

Table 10. STM32F469xx pin and ball definitions (continued)

Pin number

I/O structures
Pin types
UFBGA176(2)
Pin name
WLCSP168
UFBGA169

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function after Alternate functions
functions
reset)(1)

- - F4 G11 F3 15 15 F4 VDD S - - - -

I2C2_SDA, FMC_A0,
- 9 F3 G10 E2 16 16 D2 PF0 I/O FT -
EVENTOUT

I2C2_SCL, FMC_A1,
- 10 G3 H10 H3 17 17 E2 PF1 I/O FT -
EVENTOUT

I2C2_SMBA, FMC_A2,
- 11 G5 G12 H2 18 18 G2 PF2 I/O FT -
EVENTOUT

- - - - - - 19 E3 PI12 I/O FT LCD_HSYNC, EVENTOUT -

- - - - - - 20 G3 PI13 I/O FT LCD_VSYNC, EVENTOUT -

- - - - - - 21 H3 PI14 I/O FT LCD_CLK, EVENTOUT -

- 12 H4 H11 J2 19 22 H2 PF3 I/O FT (6) FMC_A3, EVENTOUT ADC3_IN9

(6)
- 13 L4 J10 J3 20 23 J2 PF4 I/O FT FMC_A4, EVENTOUT ADC3_IN14
- 14 H3 H12 K3 21 24 K3 PF5 I/O FT (6) FMC_A5, EVENTOUT ADC3_IN15

7 15 G7 J11 G2 22 25 H6 VSS S - - - -

8 16 G8 J12 G3 23 26 H5 VDD S - - - -

TIM10_CH1, SPI5_NSS,
(6) SAI1_SD_B, UART7_Rx,
- - - - K2 24 27 K2 PF6 I/O FT ADC3_IN4
QUADSPI_BK1_IO3,
EVENTOUT

TIM11_CH1, SPI5_SCK,
(6) SAI1_MCLK_B, UART7_Tx,
- - - - K1 25 28 K1 PF7 I/O FT ADC3_IN5
QUADSPI_BK1_IO2,
EVENTOUT

SPI5_MISO, SAI1_SCK_B,
(6) TIM13_CH1,
- - - - L3 26 29 L3 PF8 I/O FT ADC3_IN6
QUADSPI_BK1_IO0,
EVENTOUT

SPI5_MOSI, SAI1_FS_B,
(6) TIM14_CH1,
- - - - L2 27 30 L2 PF9 I/O FT ADC3_IN7
QUADSPI_BK1_IO1,
EVENTOUT

QUADSPI_CLK,
- 17 H1 K10 L1 28 31 L1 PF10 I/O FT (6) DCMI_D11, LCD_DE, ADC3_IN8
EVENTOUT
PH0-OSC_IN
9 18 G2 K11 G1 29 32 G1 I/O FT - EVENTOUT OSC_IN
(PH0)

PH1-OSC_OUT
10 19 G1 K12 H1 30 33 H1 I/O FT - EVENTOUT OSC_OUT
(PH1)

11 20 H2 H9 J1 31 34 J1 NRST I/O RST -

OTG_HS_ULPI_STP,
(6) ADC123_
12 21 M1 J9 M2 32 35 M2 PC0 I/O FT FMC_SDNWE, LCD_R5,
IN10
EVENTOUT

DS11189 Rev 8 57/225

82
Pinouts and pin description STM32F469xx

Table 10. STM32F469xx pin and ball definitions (continued)

Pin number

I/O structures
Pin types
UFBGA176(2)
Pin name
WLCSP168
UFBGA169

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function after Alternate functions
functions
reset)(1)

TRACED0,
(6) SPI2_MOSI/I2S2_SD, ADC123_
13 22 N1 L12 M3 33 36 M3 PC1 I/O FT
SAI1_SD_A, ETH_MDC, IN11
EVENTOUT

SPI2_MISO, I2S2ext_SD,
(6) OTG_HS_ULPI_DIR, ADC123_
14 23 - - M4 34 37 M4 PC2 I/O FT
ETH_MII_TXD2, IN12
FMC_SDNE0, EVENTOUT

SPI2_MOSI/I2S2_SD,
OTG_HS_ULPI_NXT,
(6) ADC123_
15 24 - - M5 35 38 L4 PC3 I/O FT ETH_MII_TX_CLK,
IN13
FMC_SDCKE0,
EVENTOUT

- 25 - - - 36 39 J5 VDD S - - - -

- - - - - - - J6 VSS S - - - -

16 26 J2 L11 M1 37 40 M1 VSSA S - - - -

- - - - N1 - - N1 VREF- S - - - -

17 27 - - P1 38 41 P1 VREF+ S - - - -
18 28 J3 M12 R1 39 42 R1 VDDA S - - - -

TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
(7) ADC123_IN0,
19 29 J5 L10 N3 40 43 N3 PA0-WKUP(PA0) I/O FT USART2_CTS, UART4_TX,
WKUP
ETH_MII_CRS,
EVENTOUT

TIM2_CH2, TIM5_CH2,
USART2_RTS, UART4_RX,
(6) QUADSPI_BK1_IO3,
20 30 K1 K9 N2 41 44 N2 PA1 I/O FT ADC123_IN1
ETH_MII_RX_CLK/ETH_R
MII_REF_CLK, LCD_R2,
EVENTOUT

TIM2_CH3, TIM5_CH3,
(6) TIM9_CH1, USART2_TX,
21 31 K2 L9 P2 42 45 P2 PA2 I/O FT ADC123_IN2
ETH_MDIO, LCD_R1,
EVENTOUT

QUADSPI_BK2_IO0,
ETH_MII_CRS,
- - L2 M11 F4 43 46 K4 PH2 I/O FT - -
FMC_SDCKE0, LCD_R0,
EVENTOUT

QUADSPI_BK2_IO1,
ETH_MII_COL,
- - L1 N12 G4 44 47 J4 PH3 I/O FT - -
FMC_SDNE0, LCD_R1,
EVENTOUT

I2C2_SCL, LCD_G5,
- - M2 M10 H4 45 48 H4 PH4 I/O FT - OTG_HS_ULPI_NXT, -
LCD_G4, EVENTOUT

58/225 DS11189 Rev 8

STM32F469xx Pinouts and pin description

Table 10. STM32F469xx pin and ball definitions (continued)

Pin number

I/O structures
Pin types
UFBGA176(2)
Pin name
WLCSP168
UFBGA169

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function after Alternate functions
functions
reset)(1)

I2C2_SDA, SPI5_NSS,
- - L3 K8 J4 46 49 J3 PH5 I/O FT - -
FMC_SDNWE, EVENTOUT

TIM2_CH4, TIM5_CH4,
TIM9_CH2, USART2_RX,
(6) LCD_B2,
22 32 K3 N10 R2 47 50 R2 PA3 I/O FT ADC123_IN3
OTG_HS_ULPI_D0,
ETH_MII_COL, LCD_B5,
EVENTOUT

23 33 J1 N11 - - 51 K6 VSS S - - - -

- - - - L4 48 - L5 BYPASS_REG I FT - - -

24 34 J4 P12 K4 49 52 K5 VDD S - - - -

SPI1_NSS,
SPI3_NSS/I2S3_WS,
USART2_CK, ADC12_IN4,
25 35 N2 M9 N4 50 53 N4 PA4 I/O TTa -
OTG_HS_SOF, DAC_OUT1
DCMI_HSYNC,
LCD_VSYNC, EVENTOUT

TIM2_CH1/TIM2_ETR,
TIM8_CH1N, SPI1_SCK, ADC12_IN5,
26 36 M3 L8 P4 51 54 P4 PA5 I/O TTa -
OTG_HS_ULPI_CK, DAC_OUT2
LCD_R4, EVENTOUT

TIM1_BKIN, TIM3_CH1,
TIM8_BKIN, SPI1_MISO,
(6)
27 37 N3 P11 P3 52 55 P3 PA6 I/O FT TIM13_CH1, ADC12_IN6
DCMI_PIXCLK, LCD_G2,
EVENTOUT

TIM1_CH1N, TIM3_CH2,
TIM8_CH1N, SPI1_MOSI,
TIM14_CH1,
28 38 K4 J8 R3 53 56 R3 PA7 I/O FT (6) QUADSPI_CLK, ADC12_IN7
ETH_MII_RX_DV/ETH_RMI
I_CRS_DV, FMC_SDNWE,
EVENTOUT

ETH_MII_RXD0/ETH_RMII
NC (6)
(3) 39 - - N5 54 57 N5 PC4 I/O FT _RXD0, FMC_SDNE0, ADC12_IN14
EVENTOUT

ETH_MII_RXD1/ETH_RMII
NC (6)
(3) 40 - - P5 55 58 P5 PC5 I/O FT _RXD1, FMC_SDCKE0, ADC12_IN15
EVENTOUT

- - - - - - 59 L7 VDD S - - - -
- - - - - - 60 L6 VSS S - - - -

TIM1_CH2N, TIM3_CH3,
TIM8_CH2N, LCD_R3,
(6)
29 41 N4 P10 R5 56 61 R5 PB0 I/O FT OTG_HS_ULPI_D1, ADC12_IN8
ETH_MII_RXD2, LCD_G1,
EVENTOUT

DS11189 Rev 8 59/225

82
Pinouts and pin description STM32F469xx

Table 10. STM32F469xx pin and ball definitions (continued)

Pin number

I/O structures
Pin types
UFBGA176(2)
Pin name
WLCSP168
UFBGA169

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function after Alternate functions
functions
reset)(1)

TIM1_CH3N, TIM3_CH4,
TIM8_CH3N, LCD_R6,
(6)
30 42 K5 N9 R4 57 62 R4 PB1 I/O FT OTG_HS_ULPI_D2, ADC12_IN9
ETH_MII_RXD3, LCD_G0,
EVENTOUT

PB2-
31 43 L5 P9 M6 58 63 M5 I/O FT - EVENTOUT -
BOOT1(PB2)

LCD_G2, LCD_R0,
- - - - - - 64 G4 PI15 I/O FT - -
EVENTOUT

LCD_R7, LCD_R1,
- - - - - - 65 R6 PJ0 I/O FT - -
EVENTOUT

- - - - - - 66 R7 PJ1 I/O FT - LCD_R2, EVENTOUT -

DSIHOST_TE, LCD_R3,
- - - - - - 67 P7 PJ2 I/O FT - -
EVENTOUT

- - - - - - 68 N8 PJ3 I/O FT - LCD_R4, EVENTOUT -

- - - - - - 69 M9 PJ4 I/O FT - LCD_R5, EVENTOUT -

SPI5_MOSI,
- 44 M5 K7 R6 59 70 P8 PF11 I/O FT - FMC_SDNRAS, -
DCMI_D12, EVENTOUT

- 45 N5 M8 P6 60 71 M6 PF12 I/O FT - FMC_A6, EVENTOUT -

- - J6 N8 M8 61 72 K7 VSS S - - - -
- 46 K6 P8 N8 62 73 L8 VDD S - - - -

- 47 M4 J7 N6 63 74 N6 PF13 I/O FT - FMC_A7, EVENTOUT -

- 48 H5 L7 R7 64 75 P6 PF14 I/O FT - FMC_A8, EVENTOUT -

- 49 M6 H8 P7 65 76 M8 PF15 I/O FT - FMC_A9, EVENTOUT -

- 50 N6 J6 N7 66 77 N7 PG0 I/O FT - FMC_A10, EVENTOUT -

- 51 M7 P7 M7 67 78 M7 PG1 I/O FT - FMC_A11, EVENTOUT -

TIM1_ETR, UART7_Rx,
32 52 N7 N7 R8 68 79 R8 PE7 I/O FT - QUADSPI_BK2_IO0, -
FMC_D4, EVENTOUT

TIM1_CH1N, UART7_Tx,
33 53 G6 M7 P8 69 80 N9 PE8 I/O FT - QUADSPI_BK2_IO1, -
FMC_D5, EVENTOUT

TIM1_CH1,
34 54 H6 K6 P9 70 81 P9 PE9 I/O FT - QUADSPI_BK2_IO2, -
FMC_D6, EVENTOUT

- 55 J7 - M9 71 82 K8 VSS S - - - -

- 56 L6 - N9 72 83 L9 VDD S - - - -

60/225 DS11189 Rev 8

STM32F469xx Pinouts and pin description

Table 10. STM32F469xx pin and ball definitions (continued)

Pin number

I/O structures
Pin types
UFBGA176(2)
Pin name
WLCSP168
UFBGA169

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function after Alternate functions
functions
reset)(1)

TIM1_CH2N,
35 57 H7 P6 R9 73 84 R9 PE10 I/O FT - QUADSPI_BK2_IO3, -
FMC_D7, EVENTOUT

TIM1_CH2, SPI4_NSS,
36 58 K7 N6 P10 74 85 P10 PE11 I/O FT - FMC_D8, LCD_G3, -
EVENTOUT

TIM1_CH3N, SPI4_SCK,
37 59 L7 M6 R10 75 86 R10 PE12 I/O FT - FMC_D9, LCD_B4, -
EVENTOUT

TIM1_CH3, SPI4_MISO,
38 60 J8 L6 N11 76 87 R12 PE13 I/O FT - FMC_D10, LCD_DE, -
EVENTOUT

TIM1_CH4, SPI4_MOSI,
39 61 K8 J5 P11 77 88 P11 PE14 I/O FT - FMC_D11, LCD_CLK, -
EVENTOUT
TIM1_BKIN, FMC_D12,
40 62 L8 P5 R11 78 89 R11 PE15 I/O FT - -
LCD_R7, EVENTOUT

TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
USART3_TX,
41 63 M8 N5 R12 79 90 P12 PB10 I/O FT - QUADSPI_BK1_NCS, -
OTG_HS_ULPI_D3,
ETH_MII_RX_ER, LCD_G4,
EVENTOUT
TIM2_CH4, I2C2_SDA,
USART3_RX,
OTG_HS_ULPI_D4,
42 64 N8 K5 R13 80 91 R13 PB11 I/O FT - -
ETH_MII_TX_EN/ETH_RMI
I_TX_EN, DSIHOST_TE,
LCD_G5, EVENTOUT

43 65 N9 N4 M10 81 92 L11 VCAP1 S - - - -

44 - M9 P4 - - 93 K9 VSS S - - - -

45 66 L9 P3 N10 82 94 L10 VDD S - - - -

- - - - - - 95 M14 PJ5 I/O FT - LCD_R6, EVENTOUT -

I2C2_SMBA, SPI5_SCK,
TIM12_CH1,
- - - - M11 83 96 P13 PH6 I/O FT - ETH_MII_RXD2, -
FMC_SDNE1, DCMI_D8,
EVENTOUT

I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
- - - - N12 84 97 N13 PH7 I/O FT - -
FMC_SDCKE1, DCMI_D9,
EVENTOUT

DS11189 Rev 8 61/225

82
Pinouts and pin description STM32F469xx

Table 10. STM32F469xx pin and ball definitions (continued)

Pin number

I/O structures
Pin types
UFBGA176(2)
Pin name
WLCSP168
UFBGA169

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function after Alternate functions
functions
reset)(1)

I2C3_SDA, FMC_D16,
- - H8 M5 - - 98 P14 PH8 I/O FT - DCMI_HSYNC, LCD_R2, -
EVENTOUT

I2C3_SMBA, TIM12_CH2,
- - H9 L5 - - 99 N14 PH9 I/O FT - FMC_D17, DCMI_D0, -
LCD_R3, EVENTOUT

TIM5_CH1, FMC_D18,
- - J9 M4 - - 100 P15 PH10 I/O FT - DCMI_D1, LCD_R4, -
EVENTOUT

TIM5_CH2, FMC_D19,
- - K9 N3 - - 101 N15 PH11 I/O FT - DCMI_D2, LCD_R5, -
EVENTOUT

TIM5_CH3, FMC_D20,
- - H10 P2 - - 102 M15 PH12 I/O FT - DCMI_D3, LCD_R6, -
EVENTOUT
- - - H7 - - - K10 VSS S - - - -

- 66 - - - - 103 K11 VDD S - - - -

TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
USART3_CK, CAN2_RX,
46 67 N10 H5 P12 85 104 L13 PB12 I/O FT - OTG_HS_ULPI_D5, -
ETH_MII_TXD0/ETH_RMII
_TXD0, OTG_HS_ID,
EVENTOUT
TIM1_CH1N,
SPI2_SCK/I2S2_CK,
USART3_CTS, CAN2_TX, OTG_HS_
47 68 N11 K4 P13 86 105 K14 PB13 I/O FT -
OTG_HS_ULPI_D6, VBUS
ETH_MII_TXD1/ETH_RMII
_TXD1, EVENTOUT

TIM1_CH2N, TIM8_CH2N,
SPI2_MISO, I2S2ext_SD,
48 69 N12 P1 R14 87 106 R14 PB14 I/O FT - USART3_RTS, -
TIM12_CH1, OTG_HS_DM,
EVENTOUT

RTC_REFIN, TIM1_CH3N,
TIM8_CH3N,
49 70 N13 N2 R15 88 107 R15 PB15 I/O FT - SPI2_MOSI/I2S2_SD, -
TIM12_CH2, OTG_HS_DP,
EVENTOUT

USART3_TX, FMC_D13,
50 71 L10 L4 P15 89 108 L15 PD8 I/O FT - -
EVENTOUT

USART3_RX, FMC_D14,
51 72 M10 N1 P14 90 109 L14 PD9 I/O FT - -
EVENTOUT

USART3_CK, FMC_D15,
52 73 L11 M3 N15 91 110 K15 PD10 I/O FT - -
LCD_B3, EVENTOUT

62/225 DS11189 Rev 8

STM32F469xx Pinouts and pin description

Table 10. STM32F469xx pin and ball definitions (continued)

Pin number

I/O structures
Pin types
UFBGA176(2)
Pin name
WLCSP168
UFBGA169

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function after Alternate functions
functions
reset)(1)

USART3_CTS,
QUADSPI_BK1_IO0,
- 74 M11 J4 N14 92 111 N10 PD11 I/O FT - -
FMC_A16/FMC_CLE,
EVENTOUT

TIM4_CH1, USART3_RTS,
QUADSPI_BK1_IO1,
- 75 M13 M2 N13 93 112 M10 PD12 I/O FT - -
FMC_A17/FMC_ALE,
EVENTOUT

TIM4_CH2,
- - M12 H4 M15 94 113 M11 PD13 I/O FT - QUADSPI_BK1_IO3, -
FMC_A18, EVENTOUT

- 76 J10 M1 - 95 114 J10 VSS S - - - -

- 77 K10 - J13 96 115 J11 VDD S - - - -

TIM4_CH3, FMC_D0,
53 78 L12 L3 M14 97 116 L12 PD14 I/O FT - -
EVENTOUT

TIM4_CH4, FMC_D1,
54 79 L13 L2 L14 98 117 K13 PD15 I/O FT - -
EVENTOUT

55 80 K13 L1 J12 99 118 H11 VDDDSI S - - - -

- - - - - - - H10 VSS S - - - -

56 81 K12 K1 K12 100 119 K12 VCAPDSI S - - - -

- - - K2 D13 - - G13 VDD12DSI S - - - -

57 82 J12 K3 M12 101 120 J12 DSIHOST_D0P I/O - - - -

58 83 J13 J3 M13 102 121 J13 DSIHOST_D0N I/O - - - -

59 84 K11 H1 H12 103 122 G12 VSSDSI S - - - -

60 85 H12 J1 L12 104 123 H12 DSIHOST_CKP I/O - - - -

61 86 H13 J2 L13 105 124 H13 DSIHOST_CKN I/O - - - -

62 87 J11 - D13 106 125 - VDD12DSI S - - - -

63 88 G12 H3 E12 107 126 F12 DSIHOST_D1P I/O - - - -

64 89 G13 H2 E13 108 127 F13 DSIHOST_D1N I/O - - - -

- - H11 - H12 109 128 - VSSDSI S - - - -

- 90 F13 G5 L15 110 129 M13 PG2 I/O FT - FMC_A12, EVENTOUT -

- 91 F12 G4 K15 111 130 M12 PG3 I/O FT - FMC_A13, EVENTOUT -

FMC_A14/FMC_BA0,
- 92 E13 G2 K14 112 131 N12 PG4 I/O FT - -
EVENTOUT

FMC_A15/FMC_BA1,
- 93 E12 G1 K13 113 132 N11 PG5 I/O FT - -
EVENTOUT

DCMI_D12, LCD_R7,
- 94 F11 G3 J15 114 133 J15 PG6 I/O FT - -
EVENTOUT

DS11189 Rev 8 63/225

82
Pinouts and pin description STM32F469xx

Table 10. STM32F469xx pin and ball definitions (continued)

Pin number

I/O structures
Pin types
UFBGA176(2)
Pin name
WLCSP168
UFBGA169

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function after Alternate functions
functions
reset)(1)

SAI1_MCLK_A,
USART6_CK, FMC_INT,
- 95 E11 H6 J14 115 134 J14 PG7 I/O FT - -
DCMI_D13, LCD_CLK,
EVENTOUT

SPI6_NSS, USART6_RTS,
ETH_PPS_OUT,
- 96 D13 G6 H14 116 135 H14 PG8 I/O FT - -
FMC_SDCLK, LCD_G7,
EVENTOUT

- - G9 F2 G12 117 136 G10 VSS S - - - -

65 97 G11 F1 H13 118 137 G11 VDDUSB S - - - -

TIM3_CH1, TIM8_CH1,
I2S2_MCK, USART6_TX,
66 98 F9 F3 H15 119 138 H15 PC6 I/O FT - -
SDIO_D6, DCMI_D0,
LCD_HSYNC, EVENTOUT

TIM3_CH2, TIM8_CH2,
I2S3_MCK, USART6_RX,
67 99 F10 G7 G15 120 139 G15 PC7 I/O FT - -
SDIO_D7, DCMI_D1,
LCD_G6, EVENTOUT
TRACED1, TIM3_CH3,
TIM8_CH3, USART6_CK,
68 100 E10 F4 G14 121 140 G14 PC8 I/O FT - -
SDIO_D0, DCMI_D2,
EVENTOUT

MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN,
69 101 G10 F5 F14 122 141 F14 PC9 I/O FT - -
QUADSPI_BK1_IO0,
SDIO_D1, DCMI_D3,
EVENTOUT
MCO1, TIM1_CH1,
I2C3_SCL, USART1_CK,
70 102 D8 E1 F15 123 142 F15 PA8 I/O FT - -
OTG_FS_SOF, LCD_R6,
EVENTOUT

TIM1_CH2, I2C3_SMBA,
SPI2_SCK/I2S2_CK, OTG_FS_
71 103 E8 E2 E15 124 143 E15 PA9 I/O FT -
USART1_TX, DCMI_D0, VBUS
EVENTOUT

TIM1_CH3, USART1_RX,
72 104 E9 E3 D15 125 144 D15 PA10 I/O FT - OTG_FS_ID, DCMI_D1, -
EVENTOUT

TIM1_CH4, USART1_CTS,
73 105 A13 F7 C15 126 145 C15 PA11 I/O FT - CAN1_RX, OTG_FS_DM, -
LCD_R4, EVENTOUT

TIM1_ETR, USART1_RTS,
74 106 A12 F6 B15 127 146 B15 PA12 I/O FT - CAN1_TX, OTG_FS_DP, -
LCD_R5, EVENTOUT

64/225 DS11189 Rev 8

STM32F469xx Pinouts and pin description

Table 10. STM32F469xx pin and ball definitions (continued)

Pin number

I/O structures
Pin types
UFBGA176(2)
Pin name
WLCSP168
UFBGA169

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function after Alternate functions
functions
reset)(1)

PA13(JTMS-
75 107 A11 D1 A15 128 147 A15 I/O FT - JTMS-SWDIO, EVENTOUT -
SWDIO)

76 108 D12 D2 F13 129 148 E11 VCAP2 S - - - -

- 109 D11 C1 F12 130 149 F10 VSS S - - - -

77 110 D10 C2 G13 131 150 F11 VDD S - - - -

TIM8_CH1N, CAN1_TX,
- - D9 B1 - - 151 E12 PH13 I/O FT - FMC_D21, LCD_G2, -
EVENTOUT

TIM8_CH2N, FMC_D22,
- - C13 D3 - - 152 E13 PH14 I/O FT - DCMI_D4, LCD_G3, -
EVENTOUT

TIM8_CH3N, FMC_D23,
- - C12 E4 - - 153 D13 PH15 I/O FT - DCMI_D11, LCD_G4, -
EVENTOUT

TIM5_CH4,
SPI2_NSS/I2S2_WS(8),
- - B13 E5 E14 132 154 E14 PI0 I/O FT - -
FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT
SPI2_SCK/I2S2_CK(8),
- - C11 C3 D14 133 155 D14 PI1 I/O FT - FMC_D25, DCMI_D8, -
LCD_G6, EVENTOUT

TIM8_CH4, SPI2_MISO,
NC I2S2ext_SD, FMC_D26,
- - B12 A1 - (3) 156 C14 PI2 I/O FT - -
DCMI_D9, LCD_G7,
EVENTOUT

TIM8_ETR,
SPI2_MOSI/I2S2_SD,
- - B10 B2 C13 134 157 C13 PI3 I/O FT - -
FMC_D27, DCMI_D10,
EVENTOUT

78 - - - D9 135 - F9 VSS S - - - -

- - - B5 C9 136 158 E10 VDD S - - - -

PA14(JTCK-
79 111 A10 D4 A14 137 159 A14 I/O FT - JTCK-SWCLK, EVENTOUT -
SWCLK)

JTDI,
TIM2_CH1/TIM2_ETR,
80 112 B11 A2 A13 138 160 A13 PA15(JTDI) I/O FT - SPI1_NSS, -
SPI3_NSS/I2S3_WS,
EVENTOUT

SPI3_SCK/I2S3_CK,
USART3_TX, UART4_TX,
81 113 C10 D5 B14 139 161 B14 PC10 I/O FT - QUADSPI_BK1_IO1, -
SDIO_D2, DCMI_D8,
LCD_R2, EVENTOUT

DS11189 Rev 8 65/225

82
Pinouts and pin description STM32F469xx

Table 10. STM32F469xx pin and ball definitions (continued)

Pin number

I/O structures
Pin types
UFBGA176(2)
Pin name
WLCSP168
UFBGA169

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function after Alternate functions
functions
reset)(1)

I2S3ext_SD, SPI3_MISO,
USART3_RX, UART4_RX,
82 114 B9 B3 B13 140 162 B13 PC11 I/O FT - QUADSPI_BK2_NCS, -
SDIO_D3, DCMI_D4,
EVENTOUT

TRACED3,
SPI3_MOSI/I2S3_SD,
83 115 A9 C4 A12 141 163 A12 PC12 I/O FT - USART3_CK, UART5_TX, -
SDIO_CK, DCMI_D9,
EVENTOUT

CAN1_RX, FMC_D2,
84 116 C9 E6 B12 142 164 B12 PD0 I/O FT - -
EVENTOUT

CAN1_TX, FMC_D3,
85 117 C7 A3 C12 143 165 C12 PD1 I/O FT - -
EVENTOUT

TRACED2, TIM3_ETR,
86 118 B8 C5 D12 144 166 D12 PD2 I/O FT - UART5_RX, SDIO_CMD, -
DCMI_D11, EVENTOUT

SPI2_SCK/I2S2_CK,
USART2_CTS, FMC_CLK,
87 119 C8 D6 D11 145 167 C11 PD3 I/O FT - -
DCMI_D5, LCD_G7,
EVENTOUT
USART2_RTS, FMC_NOE,
88 120 C6 B4 D10 146 168 D11 PD4 I/O FT - -
EVENTOUT

USART2_TX, FMC_NWE,
89 121 B7 C6 C11 147 169 C10 PD5 I/O FT - -
EVENTOUT

- 122 F8 A4 D8 148 170 F8 VSS S - - - -

- 123 F7 - C8 149 171 E9 VDD S - - - -

SPI3_MOSI/I2S3_SD,
SAI1_SD_A, USART2_RX,
90 124 D7 E7 B11 150 172 B11 PD6 I/O FT - -
FMC_NWAIT, DCMI_D10,
LCD_B2, EVENTOUT

USART2_CK, FMC_NE1,
91 - A8 A5 A11 151 173 A11 PD7 I/O FT - -
EVENTOUT

LCD_G3, LCD_B0,
- - - - - - 174 B10 PJ12 I/O FT - -
EVENTOUT

LCD_G4, LCD_B1,
- - - - - - 175 B9 PJ13 I/O FT - -
EVENTOUT

- - - - - - 176 C9 PJ14 I/O FT - LCD_B2, EVENTOUT -

- - - - - - 177 D10 PJ15 I/O FT - LCD_B3, EVENTOUT -

USART6_RX,
QUADSPI_BK2_IO2,
- 125 E6 D7 C10 152 178 D9 PG9 I/O FT - -
FMC_NE2/FMC_NCE,
DCMI_VSYNC, EVENTOUT

66/225 DS11189 Rev 8

STM32F469xx Pinouts and pin description

Table 10. STM32F469xx pin and ball definitions (continued)

Pin number

I/O structures
Pin types
UFBGA176(2)
Pin name
WLCSP168
UFBGA169

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function after Alternate functions
functions
reset)(1)

LCD_G3, FMC_NE3,
- 126 E7 C7 B10 153 179 C8 PG10 I/O FT - DCMI_D2, LCD_B2, -
EVENTOUT

ETH_MII_TX_EN/ETH_RMI
- 127 B6 B6 B9 154 180 B8 PG11 I/O FT - I_TX_EN, DCMI_D3, -
LCD_B3, EVENTOUT

SPI6_MISO,
USART6_RTS, LCD_B4,
- 128 A7 A6 B8 155 181 C7 PG12 I/O FT - -
FMC_NE4, LCD_B1,
EVENTOUT

TRACED0, SPI6_SCK,
USART6_CTS,
- - A6 E8 A8 156 182 B3 PG13 I/O FT - ETH_MII_TXD0/ETH_RMII -
_TXD0, FMC_A24,
LCD_R0, EVENTOUT

TRACED1, SPI6_MOSI,
USART6_TX,
QUADSPI_BK2_IO3,
- - - - A7 157 183 A4 PG14 I/O FT - -
ETH_MII_TXD1/ETH_RMII
_TXD1, FMC_A25,
LCD_B0, EVENTOUT
- 129 - B7 D7 158 184 F7 VSS S - - - -

- 130 - A7 C7 159 185 E8 VDD S - - - -

- - - - - - 186 D8 PK3 I/O FT - LCD_B4, EVENTOUT -

- - - - - - 187 D7 PK4 I/O FT - LCD_B5, EVENTOUT -

- - - - - - 188 C6 PK5 I/O FT - LCD_B6, EVENTOUT -

- - - - - - 189 C5 PK6 I/O FT - LCD_B7, EVENTOUT -

- - - - - - 190 C4 PK7 I/O FT - LCD_DE, EVENTOUT -

USART6_CTS,
- 131 F6 D8 B7 160 191 B7 PG15 I/O FT - FMC_SDNCAS, -
DCMI_D13, EVENTOUT
JTDO/TRACESWO,
PB3(JTDO/TRA TIM2_CH2, SPI1_SCK,
92 132 B5 A8 A10 161 192 A10 I/O FT - -
CESWO) SPI3_SCK/I2S3_CK,
EVENTOUT

NJTRST, TIM3_CH1,
93 133 D6 C8 A9 162 193 A9 PB4(NJTRST) I/O FT - SPI1_MISO, SPI3_MISO, -
I2S3ext_SD, EVENTOUT

DS11189 Rev 8 67/225

82
Pinouts and pin description STM32F469xx

Table 10. STM32F469xx pin and ball definitions (continued)

Pin number

I/O structures
Pin types
UFBGA176(2)
Pin name
WLCSP168
UFBGA169

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function after Alternate functions
functions
reset)(1)

TIM3_CH2, I2C1_SMBA,
SPI1_MOSI,
SPI3_MOSI/I2S3_SD,
CAN2_RX,
94 134 D5 B8 A6 163 194 A8 PB5 I/O FT - -
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1, DCMI_D10,
LCD_G7, EVENTOUT

TIM4_CH1, I2C1_SCL,
USART1_TX, CAN2_TX,
95 135 C5 G8 B6 164 195 B6 PB6 I/O FT - QUADSPI_BK1_NCS, -
FMC_SDNE1, DCMI_D5,
EVENTOUT

TIM4_CH2, I2C1_SDA,
96 136 B4 A9 B5 165 196 B5 PB7 I/O FT - USART1_RX, FMC_NL, -
DCMI_VSYNC, EVENTOUT

97 137 A5 F8 D6 166 197 E6 BOOT0 I B - - VPP

TIM4_CH3, TIM10_CH1,
I2C1_SCL, CAN1_RX,
98 138 D4 B9 A5 167 198 A7 PB8 I/O FT - ETH_MII_TXD3, SDIO_D4, -
DCMI_D6, LCD_B6,
EVENTOUT

TIM4_CH4, TIM11_CH1,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
99 139 C4 E9 B4 168 199 B4 PB9 I/O FT - -
CAN1_TX, SDIO_D5,
DCMI_D7, LCD_B7,
EVENTOUT

TIM4_ETR, UART8_Rx,
NC
(3) 140 A4 A10 A4 169 200 A6 PE0 I/O FT - FMC_NBL0, DCMI_D2, -
EVENTOUT

NC UART8_Tx, FMC_NBL1,
(3) 141 A3 C9 A3 170 201 A5 PE1 I/O FT - -
DCMI_D3, EVENTOUT

- - E3 B10 D5 - 202 F6 VSS S - - - -

- 142 C3 D9 C6 171 203 E5 PDR_ON S - - - -

100 143 D3 A11 C5 172 204 E7 VDD S - - - -

TIM8_BKIN, FMC_NBL2,
- - B3 D10 D4 173 205 C3 PI4 I/O FT - DCMI_D5, LCD_B4, -
EVENTOUT

TIM8_CH1, FMC_NBL3,
- - A2 C10 C4 174 206 D3 PI5 I/O FT - DCMI_VSYNC, LCD_B5, -
EVENTOUT

68/225 DS11189 Rev 8

STM32F469xx Pinouts and pin description

Table 10. STM32F469xx pin and ball definitions (continued)

Pin number

I/O structures
Pin types
UFBGA176(2)
Pin name
WLCSP168
UFBGA169

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function after Alternate functions
functions
reset)(1)

TIM8_CH2, FMC_D28,
- - A1 B11 C3 175 207 D6 PI6 I/O FT - DCMI_D6, LCD_B6, -
EVENTOUT

TIM8_CH3, FMC_D29,
- - B1 A12 C2 176 208 D4 PI7 I/O FT - DCMI_D7, LCD_B7, -
EVENTOUT

1. Function availability depends on the chosen device.

2. For the UFBGA176 package, the balls F6, F7, F8, F9, F10, G6, G7, G8, G9, G10, H6, H7, H8, H9, H10, J6, J7, J8, J9, J10,
K6, K7, K8, K9, K10 are connected to VSS. Their purpose is heat dissipation and package mechanical stability.
3. NC (not-connected) pins are not bonded. They must be configured by software to output push-pull and forced to “0” in the
output data register to avoid extra current consumption in low power modes.
4. PC13, PC14, PC15, and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (for example, to drive one LED).
5. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F4xx reference manual, available from www.st.com.
6. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0, and PH1).
7. If the device is delivered in one WLCSP168, UFBGA169, UFBGA176, LQFP176 or TFBGA216 package, and the
BYPASS_REG pin is set to VDD (Regulator OFF/internal reset ON mode), then PA0 is used as an internal reset (active
low).
8. PI0 and PI1 cannot be used for I2S2 full-duplex mode.

DS11189 Rev 8 69/225

82
Pinouts and pin description STM32F469xx

Table 11. FMC pin definition

Pin name NOR/PSRAM/SRAM NOR/PSRAM Mux NAND16 SDRAM

PF0 A0 - - A0
PF1 A1 - - A1
PF2 A2 - - A2
PF3 A3 - - A3
PF4 A4 - - A4
PF5 A5 - - A5
PF12 A6 - - A6
PF13 A7 - - A7
PF14 A8 - - A8
PF15 A9 - - A9
PG0 A10 - - A10
PG1 A11 - - A11
PG2 A12 - - A12
PG3 A13 - -
PG4 A14 - - BA0
PG5 A15 - - BA1
PD11 A16 A16 CLE -
PD12 A17 A17 ALE -
PD13 A18 A18 - -
PE3 A19 A19 - -
PE4 A20 A20 - -
PE5 A21 A21 - -
PE6 A22 A22 - -
PE2 A23 A23 - -
PG13 A24 A24 - -
PG14 A25 A25 - -
PD14 D0 DA0 D0 D0
PD15 D1 DA1 D1 D1
PD0 D2 DA2 D2 D2
PD1 D3 DA3 D3 D3
PE7 D4 DA4 D4 D4
PE8 D5 DA5 D5 D5
PE9 D6 DA6 D6 D6
PE10 D7 DA7 D7 D7
PE11 D8 DA8 D8 D8

70/225 DS11189 Rev 8

STM32F469xx Pinouts and pin description

Table 11. FMC pin definition (continued)

Pin name NOR/PSRAM/SRAM NOR/PSRAM Mux NAND16 SDRAM

PE12 D9 DA9 D9 D9
PE13 D10 DA10 D10 D10
PE14 D11 DA11 D11 D11
PE15 D12 DA12 D12 D12
PD8 D13 DA13 D13 D13
PD9 D14 DA14 D14 D14
PD10 D15 DA15 D15 D15
PH8 D16 - - D16
PH9 D17 - - D17
PH10 D18 - - D18
PH11 D19 - - D19
PH12 D20 - - D20
PH13 D21 - - D21
PH14 D22 - - D22
PH15 D23 - - D23
PI0 D24 - - D24
PI1 D25 - - D25
PI2 D26 - - D26
PI3 D27 - - D27
PI6 D28 - - D28
PI7 D29 - - D29
PI9 D30 - - D30
PI10 D31 - - D31
PD7 NE1 NE1 - -
PG9 NE2 NE2 NCE -
PG10 NE3 NE3 - -
PG11 - - - -
PG12 NE4 NE4 - -
PD3 CLK CLK - -
PD4 NOE NOE NOE -
PD5 NWE NWE NWE -
PD6 NWAIT NWAIT NWAIT -
PB7 NADV NADV - -
PF6 - - - -
PF7 - - - -

DS11189 Rev 8 71/225

82
Pinouts and pin description STM32F469xx

Table 11. FMC pin definition (continued)

Pin name NOR/PSRAM/SRAM NOR/PSRAM Mux NAND16 SDRAM

PF8 - - - -
PF9 - - - -
PF10 - - - -
PG6 - - - -
PG7 - - INT -
PE0 NBL0 NBL0 - NBL0
PE1 NBL1 NBL1 - NBL1
PI4 NBL2 - - NBL2
PI5 NBL3 - - NBL3
PG8 - - - SDCLK
PC0 - - - SDNWE
PF11 - - - SDNRAS
PG15 - - - SDNCAS
PH2 - - - SDCKE0
PH3 - - - SDNE0
PH6 - - - SDNE1
PH7 - - - SDCKE1
PH5 - - - SDNWE
PC2 - - - SDNE0
PC3 - - - SDCKE0
PB5 - - - SDCKE1
PB6 - - - SDNE1

72/225 DS11189 Rev 8

 STM32F469xx
Table 12. Alternate function
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

USAR CAN1/2/ QUAD FMC/

Port SPI2/3/ T6/ TIM12/ SPI/OT DCMI/
TIM3/4/ TIM8/9/ SPI1/2/3 SPI2/3/ SDIO/
SYS TIM1/2 I2C1/2/3 USART UART 13/14/ G2_HS ETH DSI LCD SYS
5 10/11 /4/5/6 SAI1 OTG2_
1/2/3 4/5/7/ QUAD /OTG1 HOST
FS
8 SPI/LCD _FS
TIM2_CH1/ USART2_ UART4_ EVENT
PA0 - TIM5_CH1 TIM8_ETR - - - - - ETH_MII_CRS - - -
TIM2_ETR CTS TX OUT

ETH_MII_RX_
USART2_ UART4_ QUADSPI_ EVENT
PA1 - TIM2_CH2 TIM5_CH2 - - - - RTS RX BK1_IO3 - CLK/ETH_RMI - - LCD_R2
OUT
I_REF_CLK

USART2_T EVENT
PA2 - TIM2_CH3 TIM5_CH3 TIM9_CH1 - - - X - - - ETH_MDIO - - LCD_R1
OUT

USART2_ OTG_HS EVENT

PA3 - TIM2_CH4 TIM5_CH4 TIM9_CH2 - - - RX - LCD_B2
_ULPI_D0
ETH_MII_COL - - LCD_B5
OUT

SPI3_NSS/ USART2_ OTG_HS_S DCMI_HS LCD_VSY EVENT

PA4 - - - - - SPI1_NSS
I2S3_WS CK - - - - OF YNC NC OUT
DS11189 Rev 8

OTG_HS
TIM2_CH1/ TIM8_CH1 EVENT
PA5 - TIM2_ETR
-
N - SPI1_SCK - - - - _ULPI_C - - - LCD_R4
OUT
K

TIM8_BKI SPI1_ DCMI_PIX EVENT

PA6 - TIM1_BKIN TIM3_CH1
N
- MISO - - - TIM13_CH1 - - -
CLK
LCD_G2
OUT

ETH_MII_RX_
TIM1_ TIM8_CH1 SPI1_ QUADSPI FMC_SDN EVENT
Port PA7 - CH1N
TIM3_CH2
N - MOSI - - - TIM14_CH1
_CLK
DV/ETH_RMII
WE - - OUT
A _CRS_DV

USART1_ OTG_FS_ EVENT

PA8 MCO1 TIM1_CH1 - - I2C3_SCL - - CK - - SOF - - - LCD_R6
OUT

SPI2_SCK/I USART1_T EVENT

PA9 - TIM1_CH2 - - I2C3_SMBA
2S2_CK - X - - - - - DCMI_D0 - OUT

Pinouts and pin description

USART1_ OTG_FS_ EVENT
PA10 - TIM1_CH3 - - - - - RX - - ID - - DCMI_D1 - OUT

USART1_ OTG_FS_ EVENT

PA11 - TIM1_CH4 - - - - - CTS - CAN1_RX
DM - - - LCD_R4
OUT

USART1_ OTG_FS_ EVENT

PA12 - TIM1_ETR - - - - - RTS - CAN1_TX
DP - - - LCD_R5
OUT

JTMS- EVENT
PA13
SWDIO - - - - - - - - - - - - - - OUT

JTCK- EVENT
PA14
SWCLK - - - - - - - - - - - - - - OUT
73/225

TIM2_CH1/ SPI3_NSS/ EVENT

PA15 JTDI
TIM2_ETR
- - - SPI1_NSS
I2S3_WS - - - - - - - - ‘OUT
 Table 12. Alternate function (continued)
74/225

Pinouts and pin description

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

USAR CAN1/2/ QUAD FMC/

Port SPI2/3/ T6/ TIM12/ SPI/OT DCMI/
TIM3/4/ TIM8/9/ SPI1/2/3 SPI2/3/ SDIO/
SYS TIM1/2 I2C1/2/3 USART UART 13/14/ G2_HS ETH DSI LCD SYS
5 10/11 /4/5/6 SAI1 OTG2_
1/2/3 4/5/7/ QUAD /OTG1 HOST
FS
8 SPI/LCD _FS
TIM8_CH2 OTG_HS ETH_MII_ EVENT
PB0 - TIM1_CH2N TIM3_CH3 - - - - - LCD_R3 - - LCD_G1
N _ULPI_D1 RXD2 OUT

TIM8_CH3 OTG_HS ETH_MII_ EVENT

PB1 - TIM1_CH3N TIM3_CH4
N - - - - - LCD_R6
_ULPI_D2 RXD3 - - LCD_G0
OUT

EVENT
PB2 - - - - - - - - - - - - - - - OUT

JTDO /
SPI3_SCK/ EVENT
PB3 TRACES TIM2_CH2 - - SPI1_SCK
I2S3_CK - - - - - - - - OUT
WO

SPI3_MIS I2S3ext EVENT

PB4 NJTRST - TIM3_CH1 - - SPI1_MISO
O _SD - - - - - - - OUT
DS11189 Rev 8

SPI3_MOS OTG_HS ETH_PPS FMC_ EVENT

PB5 - - TIM3_CH2 - I2C1_SMBA SPI1_MOSI
I/I2S3_SD - CAN2_RX
_ULPI_D7 OUT SDCKE1
DCMI_D10 LCD_G7
OUT

QUADSPI
USART1 FMC_ EVENT
PB6 - - TIM4_CH1 - I2C1_SCL - - _TX - CAN2_TX _BK1_NC - SDNE1
DCMI_D5
OUT
S

USART1_ DCMI_VS EVENT

PB7 - - TIM4_CH2 - I2C1_SDA - - RX - - - - FMC_NL
YNC OUT
Port
B TIM10_CH ETH_MII_ EVENT
PB8 - - TIM4_CH3
1
I2C1_SCL - - - - CAN1_RX - TXD3
SDIO_D4 DCMI_D6 LCD_B6
OUT

TIM11_CH SPI2_NSS/I EVENT

PB9 - - TIM4_CH4
1
I2C1_SDA
2S2_WS - - - CAN1_TX - - SDIO_D5 DCMI_D7 LCD_B7
OUT

SPI2_SCK/I USART3 QUADSPI_ OTG_HS ETH_MII_RX_ EVENT

PB10 - TIM2_CH3 - - I2C2_SCL
2S2_CK - _TX - BK1_NCS _ULPI_D3 ER - - LCD_G4
OUT

ETH_MII_TX_
USART3 OTG_HS DSIHOST_ EVENT
PB11 - TIM2_CH4 - - I2C2_SDA - _RX - _ULPI_D4
EN/ETH_RMII - TE
LCD_G5
OUT
_TX_EN

ETH_MII_TXD
SPI2_NSS/I USART3 OTG_HS OTG_HS_ EVENT
PB12 - TIM1_BKIN - - I2C2_SMBA
2S2_WS - _CK - CAN2_RX
_ULPI_D5
0/ETH_RMII_T
ID - - OUT
XD0

ETH_MII_TXD

STM32F469xx
SPI2_SCK/I USART3 OTG_HS EVENT
PB13 - TIM1_CH1N - - - 2S2_CK - _CTS - CAN2_TX
_ULPI_D6
1/ETH_RMII_T - - - OUT
XD1

TIM8_CH2 I2S2ext_S USART3 OTG_HS_ EVENT

PB14 - TIM1_CH2N - N - SPI2_MISO
D _RTS - TIM12_CH1 - - ‘DM - - OUT

RTC TIM8_CH3 SPI2_MOSI OTG_HS_ EVENT

PB15
_REFIN
TIM1_CH3N - N
- /I2S2_SD
- - - TIM12_CH2 - - DP
- - ‘OUT
 Table 12. Alternate function (continued)

STM32F469xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

USAR CAN1/2/ QUAD FMC/

Port SPI2/3/ T6/ TIM12/ SPI/OT DCMI/
TIM3/4/ TIM8/9/ SPI1/2/3 SPI2/3/ SDIO/
SYS TIM1/2 I2C1/2/3 USART UART 13/14/ G2_HS ETH DSI LCD SYS
5 10/11 /4/5/6 SAI1 OTG2_
1/2/3 4/5/7/ QUAD /OTG1 HOST
FS
8 SPI/LCD _FS
OTG_HS
FMC_SDN EVENT
PC0 - - - - - - - - - - _ULPI_ST - - LCD_R5
WE OUT
P

TRACE SPI2_MOSI SAI1_SD_ EVENT

PC1
D0 - - - - /I2S2_SD A
- - - ETH_MDC - - - OUT

OTG_HS
I2S2ext_S ETH_MII_TXD FMC_SDN EVENT
PC2 - - - - - SPI2_MISO
D - - - _ULPI_DI
2 E0 - - OUT
R

OTG_HS
SPI2_MOSI ETH_MII_TX_ FMC_SDC EVENT
PC3 - - - - - /I2S2_SD
- - - - _ULPI_N
CLK KE0 - - OUT
XT

ETH_MII_RXD
DS11189 Rev 8

FMC_SDN EVENT
PC4 - - - - - - - - - - - 0/ETH_RMII_R
E0 - - OUT
XD0

ETH_MII_RXD
FMC_SDC EVENT
PC5 - - - - - - - - - - - 1/ETH_RMII_R
KE0 - - OUT
XD1

USART6 LCD_HSY EVENT

PC6 - - TIM3_CH1 TIM8_CH1 - I2S2_MCK - - _TX - - - SDIO_D6 DCMI_D0
NC OUT
Port
C USART6 EVENT
PC7 - - TIM3_CH2 TIM8_CH2 - - I2S3_MCK - _RX - - - SDIO_D7 DCMI_D1 LCD_G6
OUT

TRACE USART6 EVENT

PC8
D1 - TIM3_CH3 TIM8_CH3 - - - - _CK - - - SDIO_D0 DCMI_D2 - OUT

QUADSPI_ EVENT
PC9 MCO2 - TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN - - - BK1_IO0 - - SDIO_D1 DCMI_D3 - OUT

Pinouts and pin description

SPI3_SCK/ USART3_ UART4_ QUADSPI_ EVENT
PC10 - - - - - - I2S3_CK TX TX BK1_IO1 - - SDIO_D2 DCMI_D8 LCD_R2
OUT

SPI3_MIS USART3_ UART4_ QUADSPI_ EVENT

PC11 - - - - - I2S3ext_SD
O RX RX BK2_NCS - - SDIO_D3 DCMI_D4 - OUT

TRACE SPI3_MOS USART3_ UART5_ EVENT

PC12
D3 - - - - -
I/I2S3_SD CK TX - - - SDIO_CK DCMI_D9 - OUT

EVENT
PC13 - - - - - - - - - - - - - - - OUT

EVENT
PC14 - - - - - - - - - - - - - - - OUT
75/225

EVENT
PC15 - - - - - - - - - - - - - - - ‘OUT
 Table 12. Alternate function (continued)
76/225

Pinouts and pin description

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

USAR CAN1/2/ QUAD FMC/

Port SPI2/3/ T6/ TIM12/ SPI/OT DCMI/
TIM3/4/ TIM8/9/ SPI1/2/3 SPI2/3/ SDIO/
SYS TIM1/2 I2C1/2/3 USART UART 13/14/ G2_HS ETH DSI LCD SYS
5 10/11 /4/5/6 SAI1 OTG2_
1/2/3 4/5/7/ QUAD /OTG1 HOST
FS
8 SPI/LCD _FS
EVENT
PD0 - - - - - - - - - CAN1_RX - - FMC_D2 - -
OUT

EVENT
PD1 - - - - - - - - - CAN1_TX - - FMC_D3 - - OUT

TRACE UART5_ EVENT

PD2
D2 - TIM3_ETR - - - - - RX - - - SDIO_CMD DCMI_D11 -
OUT

SPI2_SCK/I USART2_ EVENT

PD3 - - - - - 2S2_CK - CTS - - - - FMC_CLK DCMI_D5 LCD_G7
OUT

USART2_ EVENT
PD4 - - - - - - - RTS - - - - FMC_NOE - - OUT

USART2_T EVENT
- - - - - - - - - - - - -
DS11189 Rev 8

PD5 FMC_NWE
X OUT

SPI3_MOSI SAI1_SD_ USART2_ FMC_NWAI EVENT

PD6 - - - - - /I2S3_SD A RX - - - - T
DCMI_D10 LCD_B2
OUT

USART2_ EVENT
PD7 - - - - - - - CK - - - - FMC_NE1 - - OUT
Port
D
USART3_T EVENT
PD8 - - - - - - - X - - - - FMC_D13 - - OUT

USART3_ EVENT
PD9 - - - - - - - RX - - - - FMC_D14 - - OUT

USART3_ EVENT
PD10 - - - - - - - CK - - - - FMC_D15 - LCD_B3
OUT

USART3_ QUADSPI_ FMC_A16/F EVENT

PD11 - - - - - - - CTS - BK1_IO0 - - MC_CLE - - OUT

USART3_ QUADSPI_ FMC_A17/F EVENT

PD12 - - TIM4_CH1 - - - - RTS - BK1_IO1 - - MC_ALE - - OUT

QUADSPI_ EVENT
PD13 - - TIM4_CH2 - - - - - - BK1_IO3 - - FMC_A18 - - OUT

EVENT
PD14 - - TIM4_CH3 - - - - - - - - - FMC_D0 - - OUT

STM32F469xx
EVENT
PD15 - - TIM4_CH4 - - - - - - - - - FMC_D1 - - ‘OUT
 Table 12. Alternate function (continued)

STM32F469xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

USAR CAN1/2/ QUAD FMC/

Port SPI2/3/ T6/ TIM12/ SPI/OT DCMI/
TIM3/4/ TIM8/9/ SPI1/2/3 SPI2/3/ SDIO/
SYS TIM1/2 I2C1/2/3 USART UART 13/14/ G2_HS ETH DSI LCD SYS
5 10/11 /4/5/6 SAI1 OTG2_
1/2/3 4/5/7/ QUAD /OTG1 HOST
FS
8 SPI/LCD _FS
UART8_ EVENT
PE0 - - TIM4_ETR - - - - - - - - FMC_NBL0 DCMI_D2 -
Rx OUT

UART8_ EVENT
PE1 - - - - - - - - Tx - - - FMC_NBL1 DCMI_D3 - OUT

TRACE SAI1_ QUADSPI_ ETH_MII_TXD EVENT

PE2
CLK - - - - SPI4_SCK
MCLK_A - - BK1_IO2
-
3
FMC_A23 - - OUT

TRACE SAI1 EVENT

PE3
D0 - - - - -
_SD_B - - - - - FMC_A19 - - OUT

TRACE SAI1 EVENT

PE4
D1 - - - - SPI4_NSS
_FS_A - - - - - FMC_A20 DCMI_D4 LCD_B0
OUT

TRACE SAI1 EVENT

- - - - - - - -
DS11189 Rev 8

PE5 TIM9_CH1 SPI4_MISO FMC_A21 DCMI_D6 LCD_G0

D2 _SCK_A OUT

TRACE SAI1 EVENT

PE6
D3
- - TIM9_CH2 - SPI4_MOSI
_SD_A
- - - - - FMC_A22 DCMI_D7 LCD_G1
OUT

UART7_ QUADSPI EVENT

PE7 - TIM1_ETR - - - - - - Rx - _BK2_IO0 - FMC_D4 - - OUT
Port
E
UART7_ QUADSPI EVENT
PE8 - TIM1_CH1N - - - - - - Tx - _BK2_IO1 - FMC_D5 - - OUT

QUADSPI EVENT
PE9 - TIM1_CH1 - - - - - - - - _BK2_IO2 - FMC_D6 - - OUT

QUADSPI EVENT
PE10 - TIM1_CH2N - - - - - - - - _BK2_IO3 - FMC_D7 - - OUT

EVENT
PE11 - TIM1_CH2 - - - SPI4_NSS - - - - - - FMC_D8 - LCD_G3

Pinouts and pin description

OUT

EVENT
PE12 - TIM1_CH3N - - - SPI4_SCK - - - - - - FMC_D9 - LCD_B4
OUT

EVENT
PE13 - TIM1_CH3 - - - SPI4_MISO - - - - - - FMC_D10 - LCD_DE
OUT

EVENT
PE14 - TIM1_CH4 - - - SPI4_MOSI - - - - - - FMC_D11 - LCD_CLK
OUT

EVENT
PE15 - TIM1_BKIN - - - - - - - - - - FMC_D12 - LCD_R7
‘OUT
77/225
 Table 12. Alternate function (continued)
78/225

Pinouts and pin description

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

USAR CAN1/2/ QUAD FMC/

Port SPI2/3/ T6/ TIM12/ SPI/OT DCMI/
TIM3/4/ TIM8/9/ SPI1/2/3 SPI2/3/ SDIO/
SYS TIM1/2 I2C1/2/3 USART UART 13/14/ G2_HS ETH DSI LCD SYS
5 10/11 /4/5/6 SAI1 OTG2_
1/2/3 4/5/7/ QUAD /OTG1 HOST
FS
8 SPI/LCD _FS
EVENT
PF0 - - - - I2C2_SDA - - - - - - - FMC_A0 - -
OUT

EVENT
PF1 - - - - I2C2_SCL - - - - - - - FMC_A1 - -
OUT

EVENT
PF2 - - - - I2C2_SMBA - - - - - - - FMC_A2 - -
OUT

EVENT
PF3 - - - - - - - - - - - - FMC_A3 - -
OUT

EVENT
PF4 - - - - - - - - - - - - FMC_A4 - -
OUT

EVENT
DS11189 Rev 8

PF5 - - - - - - - - - - - - FMC_A5 - -
OUT

TIM10_CH SAI1_ UART7_ QUADSPI_ EVENT

PF6 - - - - SPI5_NSS - - - - - -
1 SD_B Rx BK1_IO3 OUT

TIM11_CH SAI1_ UART7_ QUADSPI_ EVENT

PF7 - - - - SPI5_SCK - - - - - -
1 MCLK_B Tx BK1_IO2 OUT
Port
F
SAI1_ QUADSPI EVENT
PF8 - - - - - SPI5_MISO - - TIM13_CH1 - - - -
SCK_B _BK1_IO0 OUT

SAI1_ QUADSPI EVENT

PF9 - - - - - SPI5_MOSI - - TIM14_CH1 - - - -
FS_B _BK1_IO1 OUT

QUADSPI_ EVENT
PF10 - - - - - - - - - - - DCMI_D11 LCD_DE
CLK OUT

FMC_SDN EVENT
PF11 - - - - - SPI5_MOSI - - - - - - DCMI_D12 -
RAS OUT

EVENT
PF12 - - - - - - - - - - - - FMC_A6 - -
OUT

EVENT
PF13 - - - - - - - - - - - - FMC_A7 - -
OUT

EVENT
PF14 - - - - - - - - - - - - FMC_A8 - -
OUT

STM32F469xx
EVENT
PF15 - - - - - - - - - - - - FMC_A9 - -
‘OUT
 Table 12. Alternate function (continued)

STM32F469xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

USAR CAN1/2/ QUAD FMC/

Port SPI2/3/ T6/ TIM12/ SPI/OT DCMI/
TIM3/4/ TIM8/9/ SPI1/2/3 SPI2/3/ SDIO/
SYS TIM1/2 I2C1/2/3 USART UART 13/14/ G2_HS ETH DSI LCD SYS
5 10/11 /4/5/6 SAI1 OTG2_
1/2/3 4/5/7/ QUAD /OTG1 HOST
FS
8 SPI/LCD _FS
EVENT
PG0 - - - - - - - - - - - - FMC_A10 - -
OUT

EVENT
PG1 - - - - - - - - - - - - FMC_A11 - - OUT

EVENT
PG2 - - - - - - - - - - - - FMC_A12 - - OUT

EVENT
PG3 - - - - - - - - - - - - FMC_A13 - - OUT

FMC_A14/F EVENT
PG4 - - - - - - - - - - - -
MC_BA0 - - OUT

FMC_A15/F EVENT
- -
DS11189 Rev 8

PG5 - - - - - - - - - - - -
MC_BA1 OUT

EVENT
PG6 - - - - - - - - - - - - DCMI_D12 LCD_R7
OUT

SAI1 USART6 EVENT

PG7 - - - - - - - - FMC_INT DCMI_D13 LCD_CLK
_MCLK_A _CK OUT

USART6 ETH_PPS_OU FMC_SDCL EVENT

PG8 - - - - - SPI6_NSS - - - - LCD_G7
_RTS T K OUT
Port
G
USART6 QUADSPI_ FMC_NE2/ DCMI_VS EVENT
PG9 - - - - - - - - - -
_RX BK2_IO2 FMC_NCE YNC OUT

EVENT
PG10 - - - - - - - - LCD_G3 - - FMC_NE3 DCMI_D2 LCD_B2
OUT

ETH_MII

Pinouts and pin description

_TX_EN / EVENT
PG11 - - - - - - - - - - - - DCMI_D3 LCD_B3
ETH_RMII OUT
_TX_EN

USART6 EVENT
PG12 - - - - - SPI6_MISO - - LCD_B4 - - FMC_NE4 - LCD_B1
_RTS OUT

ETH_MII
TRACE USART6 _TXD0 / EVENT
PG13 - - - - SPI6_SCK - - - - FMC_A24 - LCD_R0
D0 _CTS ETH_RMII OUT
_TXD0

ETH_MII
TRACE USART6 QUADSPI_ _TXD1 / EVENT
PG14 - - - - SPI6_MOSI - - - FMC_A25 - LCD_B0
D1 _TX BK2_IO3 ETH_RMII OUT
79/225

_TXD1

USART6 FMC_ EVENT

PG15 - - - - - - - - - - - DCMI_D13 -
_CTS SDNCAS ‘OUT
 Table 12. Alternate function (continued)
80/225

Pinouts and pin description

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

USAR CAN1/2/ QUAD FMC/

Port SPI2/3/ T6/ TIM12/ SPI/OT DCMI/
TIM3/4/ TIM8/9/ SPI1/2/3 SPI2/3/ SDIO/
SYS TIM1/2 I2C1/2/3 USART UART 13/14/ G2_HS ETH DSI LCD SYS
5 10/11 /4/5/6 SAI1 OTG2_
1/2/3 4/5/7/ QUAD /OTG1 HOST
FS
8 SPI/LCD _FS
EVENT
PH0 - - - - - - - - - - - - - - -
OUT

EVENT
PH1 - - - - - - - - - - - - - -
OUT

QUADSPI_ FMC_SDC EVENT

PH2 - - - - - - - - - - ETH_MII_CRS - LCD_R0
BK2_IO0 KE0 OUT

QUADSPI_ FMC_SDN EVENT

PH3 - - - - - - - - - - ETH_MII_COL - LCD_R1
BK2_IO1 E0 OUT

OTG_HS
EVENT
PH4 - - - - I2C2_SCL - - - - LCD_G5 _ULPI_N - - - LCD_G4
OUT
XT
DS11189 Rev 8

FMC_SDN EVENT
PH5 - - - - I2C2_SDA SPI5_NSS - - - - - - - -
WE OUT

ETH_MII_RXD FMC_SDN EVENT

PH6 - - - - I2C2_SMBA SPI5_SCK - - - TIM12_CH1 - - -
2 E1 OUT

ETH_MII_RXD FMC_SDC EVENT

PH7 - - - - I2C3_SCL SPI5_MISO - - - - - DCMI_D9 -
Port 3 KE1 OUT
H
DCMI_HS EVENT
PH8 - - - - I2C3_SDA - - - - - - - FMC_D16 LCD_R2
YNC OUT

EVENT
PH9 - - - - I2C3_SMBA - - - - TIM12_CH2 - - FMC_D17 DCMI_D0 LCD_R3
OUT

EVENT
PH10 - - TIM5_CH1 - - - - - - - - - FMC_D18 DCMI_D1 LCD_R4
OUT

EVENT
PH11 - - TIM5_CH2 - - - - - - - - - FMC_D19 DCMI_D2 LCD_R5
OUT

EVENT
PH12 - - TIM5_CH3 - - - - - - - - - FMC_D20 DCMI_D3 LCD_R6
OUT

TIM8_CH1 EVENT
PH13 - - - - - - - - CAN1_TX - - FMC_D21 - LCD_G2
N OUT

TIM8_CH2 EVENT

STM32F469xx
PH14 - - - - - - - - - - - FMC_D22 DCMI_D4 LCD_G3
N OUT

TIM8_CH3 EVENT
PH15 - - - - - - - - - - - FMC_D23 DCMI_D11 LCD_G4
N ‘OUT
 Table 12. Alternate function (continued)

STM32F469xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

USAR CAN1/2/ QUAD FMC/

Port SPI2/3/ T6/ TIM12/ SPI/OT DCMI/
TIM3/4/ TIM8/9/ SPI1/2/3 SPI2/3/ SDIO/
SYS TIM1/2 I2C1/2/3 USART UART 13/14/ G2_HS ETH DSI LCD SYS
5 10/11 /4/5/6 SAI1 OTG2_
1/2/3 4/5/7/ QUAD /OTG1 HOST
FS
8 SPI/LCD _FS
SPI2_NSS/I EVENT
PI0 - - TIM5_CH4 - - - - - - - - FMC_D24 DCMI_D13 LCD_G5
2S2_WS OUT

SPI2_SCK/I EVENT
PI1 - - - - - - - - - - - FMC_D25 DCMI_D8 LCD_G6
2S2_CK OUT

I2S2ext_S EVENT
PI2 - - - TIM8_CH4 - SPI2_MISO - - - - - FMC_D26 DCMI_D9 LCD_G7
D OUT

SPI2_MOSI EVENT
PI3 - - - TIM8_ETR - - - - - - - FMC_D27 DCMI_D10
/I2S2_SD OUT

TIM8_BKI EVENT
PI4 - - - - - - - - - - - FMC_NBL2 DCMI_D5 LCD_B4
N OUT

DCMI_VS EVENT
DS11189 Rev 8

PI5 - - - TIM8_CH1 - - - - - - - - FMC_NBL3 LCD_B5

YNC OUT

EVENT
PI6 - - - TIM8_CH2 - - - - - - - - FMC_D28 DCMI_D6 LCD_B6
OUT

EVENT
PI7 - - - TIM8_CH3 - - - - - - - - FMC_D29 DCMI_D7 LCD_B7
OUT
Port I
EVENT
PI8 - - - - - - - - - - - - - -
OUT

LCD_VSY EVENT
PI9 - - - - - - - - - CAN1_RX - - FMC_D30 -
NC OUT

ETH_MII_RX_ LCD_HSY EVENT

PI10 - - - - - - - - - - - FMC_D31 -
ER NC OUT

OTG_HS
EVENT

Pinouts and pin description

PI11 - - - - - - - - - LCD_G6 _ULPI - - - -
OUT
_DIR

LCD_HSY EVENT
PI12 - - - - - - - - - - - - - -
NC OUT

LCD_VSY EVENT
PI13 - - - - - - - - - - - - - -
NC OUT

EVENT
PI14 - - - - - - - - - - - - - - LCD_CLK
OUT

EVENT
PI15 - - - - - - - - - LCD_G2 - - - - LCD_R0
‘OUT
81/225
 Table 12. Alternate function (continued)
82/225

Pinouts and pin description

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

USAR CAN1/2/ QUAD FMC/

Port SPI2/3/ T6/ TIM12/ SPI/OT DCMI/
TIM3/4/ TIM8/9/ SPI1/2/3 SPI2/3/ SDIO/
SYS TIM1/2 I2C1/2/3 USART UART 13/14/ G2_HS ETH DSI LCD SYS
5 10/11 /4/5/6 SAI1 OTG2_
1/2/3 4/5/7/ QUAD /OTG1 HOST
FS
8 SPI/LCD _FS
EVENT
PJ0 - - - - - - - - - LCD_R7 - - - - LCD_R1
OUT

EVENT
PJ1 - - - - - - - - - - - - - - LCD_R2
OUT

DSIHOST EVENT
PJ2 - - - - - - - - - - - - - LCD_R3
_TE OUT

EVENT
PJ3 - - - - - - - - - - - - - - LCD_R4
OUT

EVENT
PJ4 - - - - - - - - - - - - - - LCD_R5
OUT
Port
J
EVENT
DS11189 Rev 8

PJ5 - - - - - - - - - - - - - - LCD_R6
OUT

EVENT
PJ12 - - - - - - - - - LCD_G3 - - - - LCD_B0
OUT

EVENT
PJ13 - - - - - - - - - LCD_G4 - - - - LCD_B1
OUT

EVENT
PJ14 - - - - - - - - - - - - - - LCD_B2
OUT

EVENT
PJ15 - - - - - - - - - - - - - - LCD_B3
OUT

EVENT
PK3 - - - - - - - - - - - - - - LCD_B4
OUT

EVENT
PK4 - - - - - - - - - - - - - - LCD_B5
OUT

Port EVENT
PK5 - - - - - - - - - - - - - - LCD_B6
K OUT

EVENT
PK6 - - - - - - - - - - - - - - LCD_B7
OUT

EVENT
PK7 - - - - - - - - - - - - - - LCD_DE
OUT

STM32F469xx
STM32F469xx Memory mapping

4 Memory mapping

The memory map is shown in Figure 21.

Figure 21. Memory map

Reserved 0xE010 0000 - 0xFFFF FFFF

Cortex®-M4
internal peripheral 0xE000 0000 - 0xE00F FFFF

AHB3 0x6000 0000 - 0xDFFF FFFF

Reserved 0x5006 0C00 - 0x5FFF FFFF

0x5006 0BFF

0xFFFF FFFF 512-Mbyte AHB2

Block 7
Cortex®-4 0x5000 0000
Internal Reserved 0x4008 0000 - 0x4FFF FFFF
peripherals 0x4007 FFFF
0xE000 0000
0xDFFF FFFF
512-Mbyte
Block 6
FMC

0xD000 0000
0xCFFF FFFF AHB1
512-Mbyte
Block 5
FMC and
QUADSPI
0xA000 0000
0x9FFF FFFF
512-Mbyte
Block 4 0x4002 0000
FMC bank3 and Reserved 0x4001 7400 - 0x4001 FFFF
QUADSPI bank
0x4001 73FF
0x8000 0000
0x7FFF FFFF
512-Mbyte
Block 3
FMC bank1 to
QUADSPI bank 2
0x6000 0000
0x5FFF FFFF
512-Mbyte APB2
Block 2
Peripherals

0x4000 0000
0x3FFF FFFF
512-Mbyte
Block 1
SRAM Reserved 0x2005 0000 - 0x3FFF FFFF
0x4001 0000
0x2000 0000 SRAM3
(128 KB aliased by bit-banding) 0x2003 0000 - 0x2004 FFFF Reserved 0x4000 8000 - 0x4000 FFFF
0x1FFF FFFF
SRAM2 0x4000 7FFF
512-Mbyte 0x2002 8000 - 0x2002 FFFF
Block 0 (32 KB aliased by bit-banding)
SRAM SRAM1 0x2000 0000 - 0x2002 7FFF
(160 KB aliased by bit-banding)
0x0000 0000
Reserved 0x1FFF C008 - 0x1FFF FFFF
Option Bytes 0x1FFF C000 - 0x1FFF C00 F
Reserved 0x1FFF 7A10 - 0x1FFF 7FFF
System memory 0x1FFF 0000 - 0x1FFF 7A0F
Reserved 0x1FFE C008 - 0x1FFE FFFF APB1
Option bytes 0x1FFE C000 - 0x1FFE C00 F
Reserved 0x1001 0000 - 0x1FFE BFFF
CCM data RAM 0x1000 0000 - 0x1000 FFFF
(64 KB data SRAM)
Reserved 0x0820 0000 - 0x0FFF FFFF
Flash memory 0x0800 0000 - 0x081F FFFF
Reserved 0x0020 0000 - 0x07FF FFFF
Aliased to Flash, system 0x4000 0000
memory or SRAM depending 0x0000 0000 - 0x001F FFFF
on the BOOT pins

MSv33863V2

DS11189 Rev 8 83/225

87
Memory mapping STM32F469xx

Table 13. STM32F469xx register boundary addresses(1)

Bus Boundary address Peripheral

- 0xE00F FFFF - 0xFFFF FFFF Reserved

®
Cortex -M4 0xE000 0000 - 0xE00F FFFF Cortex®-M4 internal peripherals
0xD000 0000 - 0xDFFF FFFF FMC bank 6
0xC000 0000 - 0xCFFF FFFF FMC bank 5
0xA000 1000 - 0xA0001FFF Quad-SPI control register
0xA000 2000 - 0xBFFF FFFF Reserved
AHB3 0xA000 0000- 0xA000 0FFF FMC control register
0x9000 0000 - 0x9FFF FFFF Quad-SPI bank
0x8000 0000 - 0x8FFF FFFF FMC bank 3
0x7000 0000 - 0x7FFF FFFF FMC bank 2 (reserved)
0x6000 0000 - 0x6FFF FFFF FMC bank 1
- 0x5006 0C00- 0x5FFF FFFF Reserved
0x5006 0800 - 0x5006 0BFF RNG
0x5005 0400 - 0x5006 07FF Reserved
AHB2 0x5005 0000 - 0x5005 03FF DCMI
0x5004 0000- 0x5004 FFFF Reserved
0x5000 0000 - 0x5003 FFFF USB OTG FS

84/225 DS11189 Rev 8

STM32F469xx Memory mapping

Table 13. STM32F469xx register boundary addresses(1) (continued)

Bus Boundary address Peripheral

- 0x4008 0000- 0x4FFF FFFF Reserved

0x4004 0000 - 0x4007 FFFF USB OTG HS
0x4002 BC00- 0x4003 FFFF Reserved
0x4002 B000 - 0x4002 BBFF Chrom (DMA2D)
0x4002 9400 - 0x4002 AFFF Reserved
0x4002 9000 - 0x4002 93FF
0x4002 8C00 - 0x4002 8FFF
0x4002 8800 - 0x4002 8BFF ETHERNET MAC
0x4002 8400 - 0x4002 87FF
0x4002 8000 - 0x4002 83FF
0x4002 6800 - 0x4002 7FFF Reserved
0x4002 6400 - 0x4002 67FF DMA2
0x4002 6000 - 0x4002 63FF DMA1
0x4002 5000 - 0x4002 5FFF Reserved
0x4002 4000 - 0x4002 4FFF BKPSRAM
0x4002 3C00 - 0x4002 3FFF Flash interface register
AHB1
0x4002 3800 - 0x4002 3BFF RCC
0x4002 3400 - 0x4002 37FF Reserved
0x4002 3000 - 0x4002 33FF CRC
0x4002 2C00 - 0x4002 2FFF Reserved
0x4002 2800 - 0x4002 2BFF GPIOK
0x4002 2400 - 0x4002 27FF GPIOJ
0x4002 2000 - 0x4002 23FF GPIOI
0x4002 1C00 - 0x4002 1FFF GPIOH
0x4002 1800 - 0x4002 1BFF GPIOG
0x4002 1400 - 0x4002 17FF GPIOF
0x4002 1000 - 0x4002 13FF GPIOE
0x4002 0C00 - 0x4002 0FFF GPIOD
0x4002 0800 - 0x4002 0BFF GPIOC
0x4002 0400 - 0x4002 07FF GPIOB
0x4002 0000 - 0x4002 03FF GPIOA

DS11189 Rev 8 85/225

87
Memory mapping STM32F469xx

Table 13. STM32F469xx register boundary addresses(1) (continued)

Bus Boundary address Peripheral

0x4001 7400 - 0x4001 FFFF Reserved

0x4001 6C00 - 0x4001 73FF DSI Host
0x4001 6800 - 0x4001 6BFF LCD-TFT
0x4001 5C00 - 0x4001 67FF Reserved
0x4001 5800 - 0x4001 5BFF SAI1
0x4001 5400 - 0x4001 57FF SPI6
0x4001 5000 - 0x4001 53FF SPI5
0x4001 4C00 - 0x4001 4FFF Reserved
0x4001 4800 - 0x4001 4BFF TIM11
0x4001 4400 - 0x4001 47FF TIM10
0x4001 4000 - 0x4001 43FF TIM9
0x4001 3C00 - 0x4001 3FFF EXTI
APB2
0x4001 3800 - 0x4001 3BFF SYSCFG
0x4001 3400 - 0x4001 37FF SPI4
0x4001 3000 - 0x4001 33FF SPI1
0x4001 2C00 - 0x4001 2FFF SDIO
0x4001 2400 - 0x4001 2BFF Reserved
0x4001 2000 - 0x4001 23FF ADC1 - ADC2 - ADC3
0x4001 1800 - 0x4001 1FFF Reserved
0x4001 1400 - 0x4001 17FF USART6
0x4001 1000 - 0x4001 13FF USART1
0x4001 0800 - 0x4001 0FFF Reserved
0x4001 0400 - 0x4001 07FF TIM8
0x4001 0000 - 0x4001 03FF TIM1

86/225 DS11189 Rev 8

STM32F469xx Memory mapping

Table 13. STM32F469xx register boundary addresses(1) (continued)

Bus Boundary address Peripheral

- 0x4000 8000- 0x4000 FFFF Reserved

0x4000 7C00 - 0x4000 7FFF UART8
0x4000 7800 - 0x4000 7BFF UART7
0x4000 7400 - 0x4000 77FF DAC
0x4000 7000 - 0x4000 73FF PWR
0x4000 6C00 - 0x4000 6FFF Reserved
0x4000 6800 - 0x4000 6BFF CAN2
0x4000 6400 - 0x4000 67FF CAN1
0x4000 6000 - 0x4000 63FF Reserved
0x4000 5C00 - 0x4000 5FFF I2C3
0x4000 5800 - 0x4000 5BFF I2C2
0x4000 5400 - 0x4000 57FF I2C1
0x4000 5000 - 0x4000 53FF UART5
0x4000 4C00 - 0x4000 4FFF UART4
0x4000 4800 - 0x4000 4BFF USART3
0x4000 4400 - 0x4000 47FF USART2
0x4000 4000 - 0x4000 43FF I2S3ext
APB1
0x4000 3C00 - 0x4000 3FFF SPI3 / I2S3
0x4000 3800 - 0x4000 3BFF SPI2 / I2S2
0x4000 3400 - 0x4000 37FF I2S2ext
0x4000 3000 - 0x4000 33FF IWDG
0x4000 2C00 - 0x4000 2FFF WWDG
0x4000 2800 - 0x4000 2BFF RTC & BKP Registers
0x4000 2400 - 0x4000 27FF Reserved
0x4000 2000 - 0x4000 23FF TIM14
0x4000 1C00 - 0x4000 1FFF TIM13
0x4000 1800 - 0x4000 1BFF TIM12
0x4000 1400 - 0x4000 17FF TIM7
0x4000 1000 - 0x4000 13FF TIM6
0x4000 0C00 - 0x4000 0FFF TIM5
0x4000 0800 - 0x4000 0BFF TIM4
0x4000 0400 - 0x4000 07FF TIM3
0x4000 0000 - 0x4000 03FF TIM2
1. The reserved boundary addresses are shown in grayed cells.

DS11189 Rev 8 87/225

87
Electrical characteristics STM32F469xx

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

5.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25°C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).

5.1.2 Typical values

Unless otherwise specified, typical data is based on TA = 25°C, VDD = 3.3 V (for the
1.7 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 22.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 23.

Figure 22. Pin loading conditions Figure 23. Pin input voltage

MCU pin MCU pin

C = 50 pF VIN

MS19011V2 MS19010V2

88/225 DS11189 Rev 8

STM32F469xx Electrical characteristics

5.1.6 Power supply scheme

Figure 24. Power supply scheme

VBAT
Backup circuitry
Power (OSC32K,RTC,
VBAT = 1.65 to 3.6 V Wakeup logic
switch
Backup registers,
backup RAM)

Level shifter
OUT
IO
GPIOs
IN Logic

VCAP_1 Kernel logic

2 × 2.2 μF VCAP_2 (CPU, digital
& RAM)
VDD VDD
1/2/...19/20 Voltage
20 × 100 nF VSS regulator
+ 1 × 4.7 μF 1/2/...19/20

VDDUSB BYPASS_REG Flash memory

VDDUSB OTG-FS
PHY
100 nF
VDDDSI
DSI
Voltage
VCAPDSI regulator

VDD12DSI DSI
PHY
2.2 μF VSSDSI

Reset
PDR_ON controller
VDD
VDDA
VREF
VREF+
Analog:
100 nF 100 nF VREF- ADC RCs, PLL,..
+ 1 μF + 1 μF
VSSA

MS38256V1

1. To connect BYPASS_REG and PDR_ON pins, refer to Section 2.19 and Section 2.20.
2. The two 2.2 µF ceramic capacitors on VCAP_1 and VCAP_2 should be replaced by two 100 nF decoupling
capacitors when the voltage regulator is OFF.
3. The 4.7 µF ceramic capacitor must be connected to one of the VDD pins.
4. VDDA and VSSA must be connected to VDD and VSS, respectively.
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.

DS11189 Rev 8 89/225

191
Electrical characteristics STM32F469xx

5.1.7 Current consumption measurement

Figure 25. Current consumption measurement scheme

IDD_VBAT
VBAT

IDD
VDD

VDDA

ai14126

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 14, Table 15, and Table 16
may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

Table 14. Voltage characteristics

Symbol Ratings Min Max Unit

External main supply voltage

VDD–VSS − 0.3 4.0
(including VDDA, VDD, VDDUSB, VDDDSI and VBAT)(1)
Input voltage on FT pins(2) VSS − 0.3 VDD+4.0
V
Input voltage on TTa pins VSS − 0.3 4.0
VIN
Input voltage on any other pin VSS − 0.3 4.0
Input voltage on BOOT pin VSS 9.0
|∆VDDx| Variations between different VDD power pins - 50
mV
|VSSX –VSS| Variations between all the different ground pins(3) - 50
VESD(HBM) Electrostatic discharge voltage (human body model) see Section 5.3.18
1. All main power (VDD, VDDA, VDDUSB, VDDDSI) and ground (VSS, VSSA) pins must always be connected to
the external power supply, in the permitted range.
2. VIN maximum value must always be respected. Refer to Table 15 for the values of the maximum allowed
injected current.
3. Including VREF- pin

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Table 15. Current characteristics

Symbol Ratings Max. Unit

∑IVDD Total current into sum of all VDD_x power lines (source)(1) 290
(1)
∑IVSS Total current out of sum of all VSS_x ground lines (sink) − 290
∑IVDDUSB Total current into VDDUSB power line (source) 25
IVDD Maximum current into each VDD_x power line (source)(1) 100
(1)
IVSS Maximum current out of each VSS_x ground line (sink) − 100
Output current sunk by any I/O and control pin 25
IIO
Output current sourced by any I/Os and control pin − 25
mA
Total output current sunk by sum of all I/O and control pins (2) 120
∑IIO Total output current sunk by sum of all USB I/Os 25
Total output current sourced by sum of all I/Os and control pins(2) − 120
(4)
Injected current on FT pins
− 5/+0
IINJ(PIN) (3) Injected current on NRST and BOOT0 pins (4)

Injected current on TTa pins(5) ±5

∑IINJ(PIN)(5) Total injected current (sum of all I/O and control pins)(6) ±25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.24.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
5. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 14 for the values of the maximum allowed input voltage.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).

Table 16. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range − 65 to +150 °C

TJ Maximum junction temperature 125 °C

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5.3 Operating conditions

5.3.1 General operating conditions

Table 17. General operating conditions

Symbol Parameter Conditions(1) Min Typ Max Unit

Power Scale 3 (VOS[1:0] bits in PWR_CR

register = 0x01), 0 - 120
Regulator ON, over-drive OFF
Over-drive
Power Scale 2 (VOS[1:0] bits - 144
OFF
in PWR_CR register = 0x10), 0
fHCLK Internal AHB clock frequency Regulator ON Over-drive
- 168
ON
Over-drive
Power Scale 1 (VOS[1:0] bits - 168 MHz
OFF
in PWR_CR register= 0x11), 0
Regulator ON Over-drive
- 180
ON
Over-drive OFF 0 - 42
fPCLK1 Internal APB1 clock frequency
Over-drive ON 0 - 45
Over-drive OFF 0 - 84
fPCLK2 Internal APB2 clock frequency
Over-drive ON 0 - 90
VDD Standard operating voltage - 1.7(2) - 3.6
Analog operating voltage
1.7(2) - 2.4
(ADC limited to 1.2 M samples)
VDDA(3)(4) Must be the same potential as VDD(5)
Analog operating voltage
2.4 - 3.6
(ADC limited to 2.4 M samples)
V
USB supply voltage USB not used 0 3.3 3.6
VDDUSB (supply voltage for PA11, PA12,
PB14 and PB15 pins) USB used 3.0 - 3.6

VDDDSI DSI system operating voltage - 1.7(2) - 3.6

VBAT Backup operating voltage - 1.65 - 3.6

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Table 17. General operating conditions (continued)

Symbol Parameter Conditions(1) Min Typ Max Unit

Power Scale 3 ((VOS[1:0] bits in

PWR_CR register = 0x01), 120 MHz 1.08 1.14 1.20
HCLK max frequency
Power Scale 2 ((VOS[1:0] bits in
PWR_CR register = 0x10), 144 MHz
Regulator ON: 1.2 V internal 1.20 1.26 1.32
HCLK max frequency with over-drive OFF
voltage on VCAP_1/VCAP_2 pins
or 168 MHz with over-drive ON
V12 Power Scale 1 ((VOS[1:0] bits in V
PWR_CR register = 0x11), 168 MHz
1.26 1.32 1.40
HCLK max frequency with over-drive OFF
or 180 MHz with over-drive ON
Regulator OFF: 1.2 V external Max frequency 120 MHz 1.10 1.14 1.20
voltage must be supplied from
Max frequency 144 MHz 1.20 1.26 1.32
external regulator on
VCAP_1/VCAP_2 pins(6) Max frequency 168 MHz 1.26 1.32 1.38

Input voltage on RST and FT 2 V ≤ VDD ≤ 3.6 V − 0.3 - 5.5

pins(7) VDD ≤ 2 V − 0.3 - 5.2
VIN VDDA V
Input voltage on TTa pins - − 0.3 -
+0.3
Input voltage on BOOT0 pin - 0 - 9
LQFP100 - - 465
LQFP144 - - 500
WLCSP168 - - 645
Power dissipation UFBGA169 - - 385
PD at TA = 85 °C for suffix 6 mW
or TA = 105 °C for suffix 7(8) LQFP176 - - 526
UFBGA176 - - 513
LQFP208 - - 1053
TFBGA216 - - 690

Ambient temperature for 6 Maximum power dissipation − 40 - 85

suffix version Low power dissipation (9) − 40 - 105
TA
Ambient temperature for 7 Maximum power dissipation − 40 - 105
°C
suffix version Low power dissipation(9) − 40 - 125
6 suffix version − 40 - 105
TJ Junction temperature range
7 suffix version − 40 - 125
1. The overdrive mode is not supported at the voltage ranges from 1.7 to 2.1 V.
2. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).
3. When the ADC is used, refer to Table 77.
4. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
5. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and power-down operation.
6. The overdrive mode is not supported when the internal regulator is OFF.

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7. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled.
8. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
9. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.

Table 18. Limitations depending on the operating power supply range

Maximum Flash Maximum HCLK
Operating memory access frequency Possible Flash
ADC
power frequency with vs. I/O operation memory
operation
supply range no wait states Flash memory wait operations
(fFlashmax) states (1)(2)

168 MHz 8-bit erase

VDD =
20 MHz(4) with 8 wait states and program
1.7 to 2.1 V(3)
Conversion time and over-drive OFF No I/O operations only
up to 1.2 Msps 180 MHz compensation 16-bit erase
VDD =
22 MHz with 8 wait states and program
2.1 to 2.4 V
and over-drive ON operations
180 MHz 16-bit erase
VDD =
24 MHz with 7 wait states and program
2.4 to 2.7 V
Conversion time and over-drive ON I/O compensation operations
up to 2.4 Msps 180 MHz works 32-bit erase
VDD =
30 MHz with 5 wait states and program
2.7 to 3.6 V(5)
and over-drive ON operations
1. Applicable only when the code is executed from flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART Accelerator and the 128-bit flash memory, the number of wait states given here does not impact the
execution speed from flash memory since the ART Accelerator allows to achieve a performance equivalent to 0 wait state
program execution.
3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).
4. Prefetch is not available.
5. When VDDUSB is connected to VDD, the voltage range for USB full speed PHYs can drop down to 2.7 V. However, the
electrical characteristics of D- and D+ pins are degraded between 2.7 and 3 V.

5.3.2 VCAP1/VCAP2 external capacitor

Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to
the VCAP1/VCAP2 pins. CEXT is specified in Table 19.

Figure 26. External capacitor CEXT

ESR

R Leak
MS19044V2

1. Legend: ESR is the equivalent series resistance.

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Table 19. VCAP1/VCAP2 operating conditions(1)

Symbol Parameter Conditions

CEXT Capacitance of external capacitor 2.2 µF

ESR ESR of external capacitor <2Ω
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.

5.3.3 Operating conditions at power-up / power-down (regulator ON)

Subject to general operating conditions for TA.

Table 20. Operating conditions at power-up / power-down (regulator ON)

Symbol Parameter Min Max Unit

VDD rise time rate 20 ∞

tVDD µs/V
VDD fall time rate 20 ∞

5.3.4 Operating conditions at power-up / power-down (regulator OFF)

Subject to general operating conditions for TA.

Table 21. Operating conditions at power-up / power-down (regulator OFF)(1)

Symbol Parameter Conditions Min Max Unit

VDD rise time rate Power-up 20 ∞

tVDD
VDD fall time rate Power-down 20 ∞
µs/V
VCAP_1 and VCAP_2 rise time rate Power-up 20 ∞
tVCAP
VCAP_1 and VCAP_2 fall time rate Power-down 20 ∞
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reaches below
1.08 V.

5.3.5 Reset and power control block characteristics

The parameters given in Table 22 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 17.

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Table 22. Reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

PLS[2:0]=000 (rising edge) 2.09 2.14 2.19

PLS[2:0]=000 (falling edge) 1.98 2.04 2.08
PLS[2:0]=001 (rising edge) 2.23 2.30 2.37
PLS[2:0]=001 (falling edge) 2.13 2.19 2.25
PLS[2:0]=010 (rising edge) 2.39 2.45 2.51
PLS[2:0]=010 (falling edge) 2.29 2.35 2.39
PLS[2:0]=011 (rising edge) 2.54 2.60 2.65

Programmable voltage PLS[2:0]=011 (falling edge) 2.44 2.51 2.56

VPVD V
detector level selection PLS[2:0]=100 (rising edge) 2.70 2.76 2.82
PLS[2:0]=100 (falling edge) 2.59 2.66 2.71
PLS[2:0]=101 (rising edge) 2.86 2.93 2.99
PLS[2:0]=101 (falling edge) 2.75 2.84 2.92
PLS[2:0]=110 (rising edge) 2.96 3.03 3.10
PLS[2:0]=110 (falling edge) 2.85 2.93 2.99
PLS[2:0]=111 (rising edge) 3.07 3.14 3.21
PLS[2:0]=111 (falling edge) 2.95 3.03 3.09
(1)
VPVDhyst PVD hysteresis - - 100 - mV

Power-on/power-down Falling edge 1.60 1.68 1.76

VPOR/PDR V
reset threshold Rising edge 1.64 1.72 1.80
VPDRhyst(1) PDR hysteresis - - 40 - mV
Falling edge 2.13 2.19 2.24
VBOR1 Brownout level 1 threshold
Rising edge 2.23 2.29 2.33
Falling edge 2.44 2.50 2.56
VBOR2 Brownout level 2 threshold V
Rising edge 2.53 2.59 2.63
Falling edge 2.75 2.83 2.88
VBOR3 Brownout level 3 threshold
Rising edge 2.85 2.92 2.97
VBORhyst (1) BOR hysteresis - - 100 - mV
TRSTTEMPO(1)(2) POR reset temporization - 0.5 1.5 3.0 ms
InRush current on voltage
IRUSH(1) regulator power-on (POR or - - 160 200 mA
wakeup from Standby)
InRush energy on voltage VDD = 1.7 V, TA = 105 °C,
ERUSH(1) regulator power-on (POR or - - 5.4 µC
IRUSH = 171 mA for 31 µs
wakeup from Standby)
1. Guaranteed by design.
2. The reset temporization is measured from the power-on (POR reset or wake-up from VBAT) to the instant when first
instruction is read by the user application code.

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5.3.6 Overdrive switching characteristics

When the overdrive mode switches from enabled to disabled, or disabled to enabled, the
system clock is stalled during the internal voltage set-up.
The overdrive switching characteristics are given in Table 23. They are subject to general
operating conditions for TA.

Table 23. Over-drive switching characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

HSI - 45 -
HSE max for 4 MHz
Over_drive switch 45 - 100
Tod_swen and min for 26 MHz
enable time
External HSE
- 40 -
50 MHz
µs
HSI - 20 -
HSE max for 4 MHz
Over_drive switch 20 - 80
Tod_swdis and min for 26 MHz.
disable time
External HSE
- 15 -
50 MHz
1. Guaranteed by design.

5.3.7 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 25.
All the run mode current consumption measurements given in this section are performed
with a reduced code that gives a consumption equivalent to the CoreMark® code.

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Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in input mode with a static value at VDD or VSS (no load).
• All peripherals are disabled except if it is explicitly mentioned.
• The flash memory access time is adjusted both to fHCLK frequency and VDD range (see
Table 18: Limitations depending on the operating power supply range).
• When the regulator is OFF, the V12 is provided externally, as described in Table 17:
General operating conditions.
• The voltage scaling and overdrive mode are adjusted to fHCLK frequency as follows:
– Scale 3 for fHCLK ≤ 120 MHz
– Scale 2 for 120 MHz < fHCLK ≤ 144 MHz
– Scale 1 for 144 MHz < fHCLK ≤180 MHz. The overdrive is only ON at 180 MHz.
• The system clock is HCLK, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2.
• External clock frequency is 25 MHz and PLL is ON when fHCLK is higher than 25 MHz.
• The typical current consumption values are obtained for 1.7 V≤ VDD ≤ 3.6 V voltage
range and for ambient temperature TA= 25 °C unless otherwise specified.
• The maximum values are obtained for 1.7 V≤ VDD ≤ 3.6 V voltage range and a
maximum ambient temperature (TA), unless otherwise specified.
• For the voltage range 1.7 V≤ VDD ≤ 2.1 V the maximum frequency is 168 MHz.

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Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled except prefetch) or RAM,
regulator ON
Max(1)
Symbol Parameter Conditions fHCLK (MHz) Typ Unit
TA = TA = TA =
25 °C 85 °C 105 °C

180 103 109(4) 142 175(4)

168 94 99 124 149
150 84 89 114 140
144 77 81 104 127
120 57 60 79 98
90 43 46 64 84
All
peripherals 60 30 33 51 70
enabled(2)(3)
30 16 19 37 57
25 14 16 34 54
16 7 10 28 48
8 4 7 26 46
4 3 6 24 44
Supply 2 3 5 23 43
IDD current in mA
Run mode 180 50 56(4) 89 124(4)
168 45 51 75 102
150 41 46 70 97
144 37 42 63 88
120 28 31 49 69
90 21 24 42 63
All
peripherals 60 15 17 36 56
disabled(2)
30 9 11 29 49
25 7 10 28 48
16 4 7 25 45
8 3 6 22 44
4 3 5 23 43
2 2 5 23 43
1. Guaranteed based on test during characterization.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC
for the analog part.
4. Guaranteed by test in production.

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Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled), regulator ON
Max(1)
fHCLK
Symbol Parameter Conditions Typ Unit
(MHz) TA = TA = TA =
25 °C 85 °C 105 °C

168 97 102 128 154

150 87 92 118 143
144 80 84 108 131

All peripherals 120 65 68 88 108

enabled(2)(3) 90 51 54 73 93
60 37 41 59 79
30 21 23 42 62

Supply current in 25 18 20 39 59
IDD mA
Run mode 168 49 55 79 105
150 44 49 44 100
144 40 45 68 92

All peripherals 120 36 39 58 78

disabled 90 29 32 51 71
60 22 25 44 64
30 13 15 34 54
25 11 13 32 52
1. Guaranteed based on test during characterization.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC
for the analog part.

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Table 26. Typical and maximum current consumption in Run mode, code with data
processing running from Flash memory (ART accelerator enabled except prefetch),
regulator OFF
Typ Max(1)
fHCLK
Symbol Parameter Conditions TA = 25 °C TA = 85 °C TA = 105 °C Unit
(MHz)
IDD12 IDD
IDD12 IDD IDD12 IDD IDD12 IDD

168 93 1 98 1 123 1 148 1

150 83 1 88 1 113 1 138 1
144 76 1 80 1 103 1 126 1

All peripherals 120 56 1 59 1 78 1 97 1

enabled(2) (3) 90 43 1 45 1 64 1 83 1
60 29 1 32 1 50 1 70 1
30 15 1 18 1 36 1 56 1
Supply current
in Run mode 25 13 1 15 1 34 1 53 1
IDD12 / IDD mA
from V12 and 168 44 1 50 1 72 1 94 1
VDD supply
150 40 1 45 1 68 1 90 1
144 36 1 40 1 62 1 82 1

All peripherals 120 27 1 30 1 48 1 66 1

disabled 90 20 1 23 1 41 1 60 1
60 14 1 16 1 35 1 53 1
30 8 1 10 1 28 1 47 1
25 7 1 9 1 27 1 46 1
1. Guaranteed based on test during characterization.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, DSI regulator, an additional power
consumption should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC
for the analog part.

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Table 27. Typical and maximum current consumption in Sleep mode, regulator ON
Max(1)(2)(3)
Symbol Parameter Conditions fHCLK (MHz) Typ Unit
TA = 25 °C TA = 85 °C TA = 105 °C

180 78 88(4) 118 151(4)

168 71 76 101 127
150 64 71 94 119
144 58 62 85 109
120 43 46 65 85
90 33 37 54 74
All
peripherals 60 23 25 44 63
enabled
30 13 15 34 53
25 11 13 32 52
16 5 8 27 47
8 4 7 25 45
4 3 5 24 44
Supply 2 2 5 23 43
IDD current in mA
(4)
Sleep mode 180 23 29 63 96(4)
168 21 25 50 76
150 19 23 48 74
144 17 31 43 67
120 13 16 34 54
90 10 13 31 51
All
peripherals 60 7 10 28 48
disabled
30 5 7 25 45
25 4 7 25 45
16 2 5 23 43
8 2 5 23 43
4 2 5 23 43
2 2 4 23 42
1. Guaranteed based on test during characterization.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC
for the analog part.
4. Guaranteed by test in production.

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Table 28. Typical and maximum current consumption in Sleep mode, regulator OFF
Typ Max(1)
fHCLK
Symbol Parameter Conditions TA = 25 °C TA = 85 °C TA = 105 °C Unit
(MHz)
IDD12 IDD
IDD12 IDD IDD12 IDD IDD12 IDD

168 70 1 75 1 100 1 126 1

150 63 1 70 1 93 1 118 1
144 57 1 61 1 84 1 108 1
All 120 42 1 45 1 64 1 84 1
peripherals
enabled 90 32 1 36 1 53 1 73 1
60 22 1 24 1 43 1 63 1
30 12 1 14 1 33 1 53 1
Supply current
in Run mode 25 10 1 12 1 31 1 51 1
IDD12 / IDD mA
from V12 and 168 20 1 24 1 49 1 75 1
VDD supply
150 18 1 22 1 47 1 73 1
144 16 1 19 1 42 1 66 1
All 120 12 1 14 1 33 1 53 1
peripherals
disabled 90 10 1 12 1 30 1 50 1
60 7 1 9 1 27 1 47 1
30 4 1 6 1 24 1 44 1
25 4 1 6 1 24 1 44 1
1. Guaranteed based on test during characterization.

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Table 29. Typical and maximum current consumption in Stop mode

Max(1)
Symbol Parameter Conditions Typ Unit
TA = TA = TA =
25 °C 85 °C 105 °C
Flash memory in Stop mode, all
Supply current in Stop oscillators OFF, no independent 0.63 3 17 33
mode with voltage watchdog
regulator in main Flash memory in Deep power
regulator mode down mode, all oscillators OFF, 0.58 3 17 33
IDD_STOP_NM no independent watchdog
(normal mode) Flash memory in Stop mode, all
Supply current in Stop oscillators OFF, no independent 0.50 2 15 28
mode with voltage watchdog
regulator in Low Power Flash memory in Deep power
regulator mode down mode, all oscillators OFF, 0.44 2 15 28 mA
no independent watchdog
Supply current in Stop
Flash memory in Deep power
mode with voltage
down mode, main regulator in
regulator in main 0.21 1 6 12
under-drive mode, all oscillators
regulator and under-
IDD_STOP_UDM drive mode OFF, no independent watchdog
(under-drive
mode) Supply current in Stop Flash memory in Deep power
mode with voltage down mode, Low Power regulator
regulator in Low Power in under-drive mode, all 0.14 1 6 13
regulator and under- oscillators OFF, no independent
drive mode watchdog
1. Data based on characterization, tested in production.

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Table 30. Typical and maximum current consumption in Standby mode

Typ(1) Max(2)

TA = TA = TA =
TA = 25 °C
Symbol Parameter Conditions 25 °C 85 °C 105 °C Unit

VDD = VDD= VDD =

VDD = 3.3 V
1.7 V 2.4 V 3.3 V

Backup SRAM ON, RTC and

1.7 2.5 2.9 6(3) 18 35(3)
LSE oscillator OFF
Backup SRAM OFF, RTC and
1.0 1.8 2.20 5(3) 15 30(3)
LSE oscillator OFF
Backup SRAM OFF, RTC ON
and LSE oscillator in Power 1.7 2.7 3.2 7 20 39
Drive mode
Supply current
IDD_STBY in Standby Backup SRAM ON, RTC ON µA
mode and LSE oscillator in Power 2.4 3.4 4.0 8 25 48
Drive mode
Backup SRAM ON, RTC ON
and LSE oscillator in High 3.2 4.2 4.8 10 29 57
Drive mode
Backup SRAM OFF, RTC ON
and LSE oscillator in High 2.5 3.5 4.1 8 25 48
Drive mode
1. PDR is off for VDD=1.7 V. When the PDR is OFF (internal reset OFF), the typical current consumption is reduced by
additional 1.2 μA.
2. Based on characterization, not tested in production unless otherwise specified.
3. Based on characterization, tested in production.

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Table 31. Typical and maximum current consumption in VBAT mode

Typ Max(2)

TA = TA = TA =
TA = 25 °C
Symbol Parameter Conditions(1) 25 °C 85 °C 105 °C Unit

VBAT = VBAT= VBAT =

VBAT = 3.3 V
1.7 V 2.4 V 3.3 V

Backup SRAM ON, RTC ON

and LSE oscillator in Low 1.431 1.577 1.825 1.9 12.0 24.0
Power mode
Backup SRAM OFF, RTC ON
and LSE oscillator in Low 0.720 0.849 1.060 1.1 7.0 13.9
Power mode
Backup SRAM ON, RTC ON
Backup and LSE oscillator in High 2.212 2.368 2.630 2.80 17.3 34.6
IDD_VBAT domain supply Drive mode µA
current
Backup SRAM OFF, RTC ON
and LSE oscillator in High 1.499 1.637 1.862 2.0 12.3 24.5
Drive mode
Backup SRAM ON, RTC and
0.710 0.720 0.760 0.8(3) 5.0 10.0(3)
LSE OFF
Backup SRAM OFF, RTC and
0.018 0.020 0.024 0.2(3) 2.0 4.0(3)
LSE OFF
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Based on characterization, tested in production.
3. Based on test during characterization.

Figure 27. Typical VBAT current consumption

(RTC ON / backup SRAM ON and LSE in Low drive mode)

6
1.65V

5 1.70V

1.80V
4
IDD_VBAT (μA)

2.00V
3 2.40V

2 2.70V

3.00V
1
3.30V

0 3.60V
0 20 40 60 80 100
Temperature (°C)

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Figure 28. Typical VBAT current consumption

(RTC ON / backup SRAM ON and LSE in High drive mode)

7
1.65V
6 1.70V

5 1.80V
IDD_VBAT (μA)

2.00V
4
2.40V
3
2.70V
2 3.00V

1 3.30V

3.60V
0
0 20 40 60 80 100
Temperature (°C)

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull resistors generate current consumption when the pin is
externally held to the opposite level. The value of this current consumption can be simply
computed by using the pull-up/pull-down resistors values given in Table 59: I/O static
characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins, which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption (see Table 33), the I/Os used by
an application also contribute to the current consumption. When an I/O pin switches, it uses

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Electrical characteristics STM32F469xx

the current from the MCU supply voltage to supply the I/O pin circuitry and to
charge/discharge the capacitive load internal or external connected to the pin:

I SW = V DD × f SW × C

where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load.
VDD is the MCU supply voltage.
fSW is the I/O switching frequency.
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.

Table 32. Switching output I/O current consumption(1)

I/O toggling
Symbol Parameter Conditions frequency Typ Unit
(fsw)

2 MHz 0.0
8 MHz 0.2
25 MHz 0.6
VDD = 3.3 V
50 MHz 1.1
C= CINT(2)
60 MHz 1.3
84 MHz 1.8

I/O switching 90 MHz 1.9

IDDIO mA
Current 2 MHz 0.1
8 MHz 0.4

VDD = 3.3 V 25 MHz 1.23

CEXT = 0 pF 50 MHz 2.43
C = CINT + CEXT + CS 60 MHz 2.93
84 MHz 3.86
90 MHz 4.07

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Table 32. Switching output I/O current consumption(1) (continued)

I/O toggling
Symbol Parameter Conditions frequency Typ Unit
(fsw)

2 MHz 0.18
8 MHz 0.67

VDD = 3.3 V 25 MHz 2.09

CEXT = 10 pF 50 MHz 3.6
C = CINT + CEXT + CS 60 MHz 4.5
84 MHz 7.8
90 MHz 9.8

I/O switching 2 MHz 0.26

IDDIO mA
Current 8 MHz 1.01
VDD = 3.3 V
CEXT = 22 pF 25 MHz 3.14
C = CINT + CEXT + CS 50 MHz 6.39
60 MHz 10.68
2 MHz 0.33
VDD = 3.3 V 8 MHz 1.29
CEXT = 33 pF
25 MHz 4.23
C = CINT + Cext + CS
50 MHz 11.02
1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value).
2. This test is performed by cutting the LQFP176 package pin (pad removal).

On-chip peripheral current consumption

The MCU is placed under the following conditions:
• At startup, all I/O pins are in analog input configuration.
• All peripherals are disabled unless otherwise mentioned.
• I/O compensation cell enabled.
• The ART Accelerator is ON.
• Scale 1 mode selected, internal digital voltage V12 = 1.32 V.
• HCLK is the system clock. fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2.
The given value is calculated by measuring the difference of current consumption:
– with all peripherals clocked off
– with only one peripheral clocked on
– fHCLK = 180 MHz (Scale1 + overdrive ON), fHCLK = 144 MHz (Scale 2),
fHCLK = 120 MHz (Scale 3)
• Ambient operating temperature is 25 °C and VDD=3.3 V.

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Table 33. Peripheral current consumption

IDD(Typ)(1)
Peripheral Unit
Scale 1 Scale 2 Scale 3

GPIOA 3.16 3.00 2.58

GPIOB 2.67 2.62 2.25
GPIOC 2.42 2.31 2.10
GPIOD 2.22 2.10 1.79
GPIOE 2.60 2.48 2.23
GPIOF 2.39 2.27 2.08
GPIOG 2.27 2.13 1.98
GPIOH 2.34 2.20 2.02
GPIOI 2.52 2.37 2.17
AHB1 GPIOJ 2.16 2.03 1.86
(up to µA/MHz
GPIOK 2.20 2.06 1.89
180 MHz)
OTG_HS+ULPI 36.49 33.89 29.90
CRC 0.62 0.55 0.50
BKPSRAM 0.83 0.74 0.63
DMA1(2) 3.3 x N + 6.8 3 x N + 6.3 2.7 x N + 5.5
DMA2(2) 3.4 x N + 5.7 3.1 x N + 5.3 2.8 x N + 4.6
DMA2D 33.33 30.66 26.98
ETH_MAC
ETH_MAC_TX
22.30 20.69 18.19
ETH_MAC_RX
ETH_MAC_PTP
USB_OTG_FS 34.33 31.96 28.35
AHB2
(up to DVCMI 3.61 3.35 2.98 µA/MHz
180 MHz)
RNG 1.94 1.82 1.61
AHB3 QUADSPI 16.83 15.57 13.83
(up to µA/MHz
180 MHz) FMC 17.22 15.92 14.00

Bus matrix(3) 12.17 11.19 9.97 µA/MHz

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Table 33. Peripheral current consumption (continued)

IDD(Typ)(1)
Peripheral Unit
Scale 1 Scale 2 Scale 3

TIM2 19.11 17.56 15.33

TIM3 15.62 14.22 12.17
TIM4 16.22 14.64 12.83
TIM5 18.44 16.72 14.00
TIM6 3.18 2.69 2.17
TIM7 3.11 2.56 2.00
TIM12 8.67 7.56 6.50
TIM13 6.11 5.33 4.43
TIM14 6.44 5.61 4.67
PWR 17.44 15.61 13.53
USART2 5.44 4.64 3.93
USART3 5.51 4.72 4.00
APB1
(up to UART4 5.22 4.64 3.83 µA/MHz
45 MHz)
UART5 5.33 4.64 3.83
UART7 5.56 4.78 4.10
UART8 5.24 4.64 3.93
I2C1 4.78 4.08 3.43
I2C2 5.11 4.50 3.73
I2C3 4.78 4.08 3.43
SPI2/I2S2(4) 4.11 3.53 3.00
SPI3/I2S3(4) 4.33 3.67 3.17
CAN1 8.89 7.83 6.87
CAN2 7.22 6.44 5.50
DAC(5) 2.89 2.69 2.40
WWDG 1.73 1.44 1.00

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Table 33. Peripheral current consumption (continued)

IDD(Typ)(1)
Peripheral Unit
Scale 1 Scale 2 Scale 3

SDIO 7.94 7.18 6.37

TIM1 19.44 17.81 15.80
TIM8 19.44 17.81 15.80
TIM9 8.44 7.60 6.77
TIM10 5.67 5.03 4.50
TIM11 5.72 5.10 4.55
ADC1(6) 5.06 4.54 4.05
ADC2(6) 5.00 4.47 3.97
ADC3(6) 5.26 4.75 4.17
APB2
(up to USART1 4.83 4.33 3.83 µA/MHz
90 MHz)
USART6 4.83 4.33 3.83
SPI1 2.11 1.76 1.60
SPI4 2.11 1.69 1.60
SPI5 2.11 1.76 1.60
SPI6 2.11 1.76 1.60
SYSCFG 1.72 1.35 1.22
LTDC 37.61 34.53 30.60
SAI1 3.44 3.01 2.72
DSI 32.98 30.32 26.87
1. When the I/O compensation cell is ON, IDD typical value increases by 0.22 mA.
2. DMA1/DMA2 current consumption is calculated by the equation. N: is the number of streams enabled,
N= [1..8]
3. The BusMatrix is automatically active when at least one master is ON.
4. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register.
5. When the DAC is ON and EN1/2 bits are set in DAC_CR register, add an additional power consumption of
0.8 mA per DAC channel for the analog part.
6. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of
1.6 mA per ADC for the analog part.

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5.3.8 Wake-up time from low-power modes

The wake up times given in Table 34 are measured starting from the wake-up event trigger
up to the first instruction executed by the CPU:
• for Stop or Sleep modes the wake-up event is WFE
• WKUP (PA0) pin is used to wake up from Standby, Stop, and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD = 3.3 V.

Table 34. Low-power mode wakeup timings

Symbol Parameter Conditions Typ(1) Max(1) Unit

CPU clock
tWUSLEEP(2) Wakeup from Sleep - 5 6
cycles
Main regulator is ON 12.9 15.0

Main regulator is ON and Flash

105 120
memory in Deep power down mode
Wakeup from Stop mode
tWUSTOP(2) with MR/LP regulator in
normal mode Low power regulator is ON 22 28

Low power regulator is ON and Flash

114 130 µs
memory in Deep power down mode

Main regulator in under-drive mode

(Flash memory in Deep power-down 107 114
Wakeup from Stop mode mode)
tWUSTOP(2) with MR/LP regulator in
Under-drive mode Low power regulator in under-drive
mode (Flash memory in Deep 115 121
power-down mode)

tWUSTDBY (2)(3) Wakeup from Standby mode - 318 371

1. Based on test during characterization.
2. The wake-up times are measured from the wake-up event to the point in which the application code reads the first
3. tWUSTDBY maximum value is given at –40 °C.

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5.3.9 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 59. However, the recommended clock input
waveform is shown in Figure 29.
The characteristics given in Table 35 result from tests performed using a high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 17.

Table 35. High-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

External user clock source

fHSE_ext 1 - 50 MHz
frequency(1)
VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD
V
VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD
-
tw(HSE)
OSC_IN high or low time(1) 5 - -
tw(HSE)
ns
tr(HSE)
OSC_IN rise or fall time(1) - - 10
tf(HSE)
Cin(HSE) OSC_IN input capacitance(1) - - 5 - pF
DuCy(HSE) Duty cycle - 45 - 55 %
IL OSC_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 µA
1. Guaranteed by design.

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 59: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 30.
The characteristics given in Table 36 result from tests performed using a low-speed external
clock source, and under ambient temperature and supply voltage conditions summarized in
Table 17.

Table 36. Low-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

fLSE_ext User External clock source frequency(1) - 32.768 1000 kHz

VLSEH OSC32_IN input pin high level voltage 0.7VDD - VDD
V
VLSEL OSC32_IN input pin low level voltage VSS - 0.3VDD
-
tw(LSE)
OSC32_IN high or low time(1) 450 - -
tf(LSE)
ns
tr(LSE)
OSC32_IN rise or fall time(1) - - 50
tf(LSE)

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Table 36. Low-speed external user clock characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit
(1)
Cin(LSE) OSC32_IN input capacitance - - 5 - pF
DuCy(LSE) Duty cycle - 30 - 70 %
IL OSC32_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 µA
1. Guaranteed by design.

Figure 29. High-speed external clock source AC timing diagram

VHSEH
90 %
10 %
VHSEL
tr(HSE) tf(HSE) tW(HSE) tW(HSE) t

THSE

External fHSE_ext
IL
clock source OSC_IN
STM32F

ai17528

Figure 30. Low-speed external clock source AC timing diagram

VLSEH
90%
10%
VLSEL
tr(LSE) tf(LSE) tW(LSE) tW(LSE) t

TLSE

External fLSE_ext
OSC32_IN IL
clock source
STM32F

ai17529

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph is based on characterization
results obtained with typical external components specified in Table 37. In the application,
the resonator and the load capacitors have to be placed as close as possible to the
oscillator pins tortion and startup stabilization time. Refer to the crystal resonator

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Electrical characteristics STM32F469xx

manufacturer for more details on the resonator characteristics (frequency, package,

accuracy).

Table 37. HSE 4-26 MHz oscillator characteristics (1)

Symbol Parameter Conditions Min Typ Max Unit

fOSC_IN Oscillator frequency - 4 - 26 MHz

RF Feedback resistor - - 200 - kΩ
VDD=3.3 V,
ESR= 30 Ω, - 450 -
CL=5 pF@25 MHz
IDD HSE current consumption µA
VDD=3.3 V,
ESR= 30 Ω, - 530 -
CL=10 pF@25 MHz
ACCHSE(2) HSE accuracy - − 500 - 500 ppm
Gm_crit_max Maximum critical crystal gm Startup - - 1 mA/V
tSU(HSE) (3) Startup time VDD is stabilized - 2 - ms
1. Guaranteed by design.
2. This parameter depends on the crystal used in the application. The minimum and maximum values must
be respected to comply with USB standard specifications.
3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is based on characterization and not tested in production. It is measured
for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 31). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance, which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from www.st.com.

Figure 31. Typical application with an 8 MHz crystal

Resonator with
integrated capacitors
CL1
OSC_IN fHSE
Bias
8 MHz RF controlled
resonator
gain

REXT(1) OSC_OU T STM32F

CL2
ai17530

1. REXT value depends on the crystal characteristics.

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Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph is based on characterization
results obtained with typical external components specified in Table 38.
In the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins to minimize output distortion and startup stabilization time.
Refer to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).

Table 38. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

Symbol Parameter Conditions Min Typ Max Unit

RF Feedback resistor - - 18.4 - MΩ

Low power mode(2) - - 1
IDD LSE current consumption µA
(2)
High drive mode - - 3
ACCLSE(3) LSE accuracy - − 500 - 500 ppm
Low power mode(2) - - 0.56
Gm_crit_max Maximum critical crystal gm µA/V
(2)
High drive mode - - 1.5
tSU(LSE)(4) Startup time VDD is stabilized - 2 - s
1. Guaranteed by design.
2. LSE mode cannot be changed “on the fly” otherwise, a glitch can be generated on OSCIN pin.
3. This parameter depends on the crystal used in the application. Refer to application note AN2867.
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is based on characterization and not tested in production. It is
measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from www.st.com.

Figure 32. Typical application with a 32.768 kHz crystal

Resonator with
integrated capacitors
CL1
OSC32_IN fLSE
Bias
32.768 kH z RF controlled
resonator
gain
OSC32_OU T STM32F
CL2
ai17531

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5.3.10 Internal clock source characteristics

The parameters given in Table 39 and Table 40 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 17.

High-speed internal (HSI) RC oscillator

Table 39. HSI oscillator characteristics (1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI Frequency - - 16 - MHz

HSI user trimming step(2) - - - 1 %
(3)
TA = –40 to 105 °C −8 - 4.5 %
ACCHSI
HSI oscillator accuracy TA = –10 to 85 °C(3) −4 - 4 %
TA = 25 °C(4) −1 - 1 %
tsu(HSI)(2) HSI oscillator startup time - - 2.2 4 µs
IDD(HSI)(2) HSI oscillator power consumption - - 60 80 µA
1. VDD = 3.3 V, PLL OFF, TA = –40 to 125 °C unless otherwise specified.
2. Guaranteed by design.
3. Based on test during characterization.
4. Factory calibrated, parts not soldered.

Figure 33. ACCHSI vs. temperature

2
ACCHSI(%)

0
-40 0 25 55 85 105 125
TA ( °C)
-2

-4

Min Max Typical

-6

-8

MSv41055V1

1. Based on test during characterization.

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Low-speed internal (LSI) RC oscillator

Table 40. LSI oscillator characteristics (1)

Symbol Parameter Min Typ Max Unit

fLSI(2) Frequency 17 32 47 kHz

tsu(LSI)(3) Startup time - 15 40 µs
IDD(LSI)(3) Power consumption - 0.4 0.6 µA
1. VDD = 3 V, TA = –40 to 105°C unless otherwise specified.
2. Based on test during characterization.
3. Guaranteed by design.

Figure 34. ACCLSI versus temperature

50
max
40 avg
min
30
Normalized deviati on (%)

20

10

-10

-20

-30

-40
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Temperat ure (°C)

MS19013V1

5.3.11 PLL characteristics

The parameters given in Table 41 and Table 42 are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 17.

Table 41. Main PLL characteristics

Symbol Parameter Conditions Min Typ Max Unit

fPLL_IN PLL input clock(1) - 0.95(2) 1 2.10

fPLL_OUT PLL multiplier output clock - 24 - 180
MHz
fPLL48_OUT 48 MHz PLL multiplier output clock - - 48 75
fVCO_OUT PLL VCO output - 192 - 432

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Table 41. Main PLL characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

VCO frequency = 192 MHz 75 - 200

tLOCK PLL lock time µs
VCO frequency = 432 MHz 100 - 300
RMS - 25 -
Cycle-to-cycle jitter
System clock peak to peak - ±150 -
120 MHz RMS - 15 -
Period jitter
peak to peak - ±200 -
(3)
Jitter Main clock output (MCO) for RMII Cycle to cycle at 50 MHz on ps
- 32 -
Ethernet 1000 samples
Main clock output (MCO) for MII Cycle to cycle at 25 MHz on
- 40 -
Ethernet 1000 samples
Cycle to cycle at 1 MHz on
Bit time CAN jitter - 330 -
1000 samples
VCO frequency = 192 MHz 0.15 0.40
IDD(PLL)(4) PLL power consumption on VDD -
VCO frequency = 432 MHz 0.45 0.75
mA
VCO frequency = 192 MHz 0.30 0.40
IDDA(PLL)(4) PLL power consumption on VDDA -
VCO frequency = 432 MHz 0.55 0.85
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design.
3. The use of two PLLs in parallel can degrade the jitter up to +30%.
4. Based on test during characterization.

Table 42. PLLI2S (audio PLL) characteristics

Symbol Parameter Conditions Min Typ Max Unit

fPLLI2S_IN PLLI2S input clock(1) - 0.95(2) 1 2.10

PLLI2S multiplier output
fPLLI2S_OUT - - - 216 MHz
clock
fVCO_OUT PLLI2S VCO output - 192 - 432
VCO frequency = 192 MHz 75 - 200
tLOCK PLLI2S lock time µs
VCO frequency = 432 MHz 100 - 300
Cycle to cycle at RMS - 90 - -
12.288 MHz on 48KHz
period, N=432, R=5 peak to peak - ±280 - ps
Master I2S clock jitter
Average frequency of 12.288 MHz,
Jitter(3) N=432, R=5 - 90 - ps
on 1000 samples
Cycle to cycle at 48 KHz
WS I2S clock jitter - 400 - ps
on 1000 samples

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Table 42. PLLI2S (audio PLL) characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

PLLI2S power consumption VCO frequency = 192 MHz 0.15 0.40

IDD(PLLI2S)(4) -
on VDD VCO frequency = 432 MHz 0.45 0.75
mA
PLLI2S power consumption VCO frequency = 192 MHz 0.30 0.40
IDDA(PLLI2S)(4) -
on VDDA VCO frequency = 432 MHz 0.55 0.85
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Based on test during characterization.

Table 43. PLLSAI (audio and LCD-TFT PLL) characteristics

Symbol Parameter Conditions Min Typ Max Unit

fPLLSAI_IN PLLSAI input clock(1) - 0.95(2) 1 2.10

fPLLSAI_OUT PLLSAI multiplier output clock - - - 216 MHz
fVCO_OUT PLLSAI VCO output - 192 - 432
VCO frequency = 192 MHz 75 - 200
tLOCK PLLSAI lock time µs
VCO frequency = 432 MHz 100 - 300

Cycle to cycle at RMS - 90 -

12.288 MHz on peak
48 KHz period, to - ±280 - ps
N=432, R=5 peak
Main SAI clock jitter
(3) Average frequency of
Jitter
12.288 MHz
- 90 - ps
N = 432, R = 5
on 1000 samples
Cycle to cycle at 48 KHz
FS clock jitter - 400 - ps
on 1000 samples
PLLSAI power consumption on VCO frequency = 192 MHz 0.15 0.40
IDD(PLLSAI)(4) -
VDD VCO frequency = 432 MHz 0.45 0.75
mA
PLLSAI power consumption on VCO frequency = 192 MHz 0.30 0.40
IDDA(PLLSAI)(4) -
VDDA VCO frequency = 432 MHz 0.55 0.85
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Based on test during characterization.

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5.3.12 PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences (see Table 54). It is available only on the main PLL.

Table 44. SSCG parameters constraint

Symbol Parameter Min Typ Max(1) Unit

fMod Modulation frequency - - 10 KHz

md Peak modulation depth 0.25 - 2 %
MODEPER * INCSTEP - - - 215 −1 -
1. Guaranteed by design.

Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER = round [ fPLL_IN ⁄ ( 4 × f Mod ) ]

fPLL_IN and fMod must be expressed in Hz.

As an example:
If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by
equation 1:
6 3
MODEPER = round [ 10 ⁄ ( 4 × 10 ) ] = 250

Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
15
INCSTEP = round [ ( ( 2 – 1 ) × md × PLLN ) ⁄ ( 100 × 5 × MODEPER ) ]

fVCO_OUT must be expressed in MHz.

With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):
15
INCSTEP = round [ ( ( 2 – 1 ) × 2 × 240 ) ⁄ ( 100 × 5 × 250 ) ] = 126md(quantitazed)%

An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
15
md quantized % = ( MODEPER × INCSTEP × 100 × 5 ) ⁄ ( ( 2 – 1 ) × PLLN )

As a result:
15
md quantized % = ( 250 × 126 × 100 × 5 ) ⁄ ( ( 2 – 1 ) × 240 ) = 2.002%(peak)

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Figure 35 and Figure 36 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is fPLL_OUT nominal.
Tmode is the modulation period.
md is the modulation depth.

Figure 35. PLL output clock waveforms in center spread mode

Frequency
(PLL_OUT)

md

F0
md

Time
tmode 2x tmode
MS39983V1

Figure 36. PLL output clock waveforms in down spread mode

Frequency
(PLL_OUT)

F0

2x md

Time
tmode 2x tmode
MS39982V1

5.3.13 MIPI D-PHY characteristics

The parameters given in Table 45 and Table 46 are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 17.

Table 45. MIPI D-PHY characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Hi-Speed Input/Output characteristics

UINST UI instantaneous - 2 - 12.5 ns

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Table 45. MIPI D-PHY characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

HS transmit common mode

VCMTX - 150 200 250
voltage
VCMTX mismatch when output
|∆VCMTX| - - - 5
is Differential-1 or Differential-0
mV
|VOD| HS transmit differential voltage - 140 200 270
VOD mismatch when output is
|∆VOD| - - - 14
Differential-1 or Differential-0
VOHHS HS output high voltage - - - 360
Single ended output
ZOS - 40 50 62.5 Ω
impedance
Single ended output
∆ZOS - - - 10 %
impedance mismatch
tHSr & tHSf 20% - 80% rise and fall time - 100 - 0.35*UI ps
LP receiver input characteristics
Logic 0 input voltage (not in
VIL - - - 550
ULP State)
Logic 0 input voltage in ULP
VIL-ULPS - - - 300 mV
State
VIH Input high level voltage - 880 - -
Vhys Voltage hysteresis - 25 - -
LP emitter output characteristics
VIL Output low level voltage - 1.1 1.2 1.2 V
VIL-ULPS Output high level voltage - -50 - 50 mV
Output impedance of LP
VIH - 110 - - Ω
transmitter
Vhys 15%-85% rise and fall time - - - 25 ns
LP contention detector characteristics
VILCD Logic 0 contention threshold - - - 200
mV
VIHCD Logic 0 contention threshold - 450 - -
1. Guaranteed based on test during characterization.

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Table 46. MIPI D-PHY AC characteristics LP mode and HS/LP transitions(1)

Symbol Parameter Conditions Min Typ Max Unit

Transmitted length of any Low-

TLPX - 50 - -
Power state period
Time that the transmitter drives
the Clock Lane LP-00 Line
TCLK-PREPARE state immediately before the - 38 - 95
ns
HS-0 Line state starting the HS
transmission.
TCLK-PREPARE Time that the transmitter drives
+ the HS-0 state prior to starting - 300 - -
TCLK-ZERO the clock.
Time that the HS clock shall be
driven by the transmitter prior to
TCLK-PRE any associated Data Lane - 8 - - UI
beginning the transition from
LP to HS mode.
Time that the transmitter
continues to send HS clock
TCLK-POST after the last associated Data - 62+52*UI - -
Lane has transitioned to LP
Mode.
Time that the transmitter drives
the HS-0 state after the last
TCLK-TRAIL - 60 - -
payload clock bit of an HS
transmission burst.
Time that the transmitter drives
the Data Lane LP-00 Line state
THS-PREPARE immediately before the HS-0 - 40+4*UI - 85+6*UI
Line state starting the HS
transmission.
THS-PREPARE+ Time that the
THS-PREPARE
transmitter drives the HS-0 ns
+ - 145+10*UI - -
state prior to transmitting the
THS-ZERO
Sync sequence.
Time that the transmitter drives
Max
the flipped differential state
THS-TRAIL - (n*8*UI, - -
after last payload data bit of a
60+n*4*UI)
HS transmission burst.
Time that the transmitter drives
THS-EXIT - 100 - -
LP-11 following a HS burst.
30% - 85% rise time and fall
TREOT - - - 35
time
Transmitted time interval from
the start of THS-TRAIL or
105+
TEOT TCLK-TRAIL, to the start of the - - -
n*12UI
LP-11 state following a HS
burst.
1. Guaranteed based on test during characterization.

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Figure 37. MIPI D-PHY HS/LP clock lane transition timing diagram

TCLK-POST TEOT

Clock VIL
Lane

TCLK-TRAIL THS-EXIT TLPX TCLK-PREPARE TCLK-ZERO TCLK-PRE TLPX THS-PREPARE

Data VIL
Lane

MS38282V1

Figure 38. MIPI D-PHY HS/LP data lane transition timing diagram

Clock
Lane
TLPX THS-PREPARE THS-ZERO

Data
VIL
Lane
TREOT
LP-11 LP-01 LP-00 TEOT

THS-TRAIL THS-EXIT

MS38283V1

5.3.14 MIPI D-PHY PLL characteristics

The parameters given in Table 47 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 17.

Table 47. DSI-PLL characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fPLL_IN PLL input clock - 4 - 100

fPLL_INFIN PFD input clock - 4 - 25
MHz
fPLL_OUT PLL multiplier output clock - 31.25 - 500
fVCO_OUT PLL VCO output - 500 - 1000
tLOCK PLL lock time - - - 200 µs

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Table 47. DSI-PLL characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

fVCO_OUT = 500 MHz - 0.55 0.70

IDD(PLL) PLL power consumption on VDD12 fVCO_OUT = 600 MHz - 0.65 0.80 mA
fVCO_OUT = 1000 MHz - 0.95 1.20
1. Based on test during characterization.

5.3.15 MIPI D-PHY regulator characteristics

The parameters given in Table 48 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 17.

Table 48. DSI regulator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDD12DSI 1.2 V internal voltage on VDD12DSI - 1.15 1.20 1.30 V

CEXT External capacitor on VCAPDSI - 1.1 2.2 3.3 μF
ESR External Serial Resistor - 0 25 600 mΩ
IDDDSIREG Regulator power consumption - 100 120 125 µA
Ultra Low Power Mode
- 290 600
DSI system (regulator, PLL and (Reg. ON + PLL OFF)
IDDDSI µA
D-PHY) current consumption on VDDDSI Stop State
- 290 600
(Reg. ON + PLL OFF)
10 MHz escape clock
- 4.3 5.0
DSI system current consumption on (Reg. ON + PLL OFF)
IDDDSILP mA
VDDDSI in LP mode communication(2) 20 MHz escape clock
- 4.3 5.0
(Reg. ON + PLL OFF)
300 Mbps - 1 data lane
- 8.0 8.8
(Reg. ON + PLL ON)
300 Mbps - 2data lane
DSI system (regulator, PLL and - 11.4 12.5
(Reg. ON + PLL ON)
D-PHY) current consumption on VDDDSI
in HS mode communication(3) 500 Mbps - 1 data lane
- 13.5 14.7
IDDDSIHS (Reg. ON + PLL ON) mA
500 Mbps - 2data lane
- 18.0 19.6
(Reg. ON + PLL ON)
DSI system (regulator, PLL and
500 Mbps - 2data lane
D-PHY) current consumption on VDDDSI - 21.4 23.3
(Reg. ON + PLL ON)
in HS mode with CLK like payload
CEXT = 2.2 µF - 110 -
tWAKEUP Startup delay µs
CEXT = 3.3 µF - - 160
IINRUSH Inrush current on VDDDSI External capacitor load at start - 60 200 mA
1. Based on test during characterization.
2. Values based on an average traffic in LP Command Mode.
3. Values based on an average traffic (3/4 HS traffic & 1/4 LP) in Video Mode.

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5.3.16 Memory characteristics

Flash memory
The characteristics are given at TA = –40 to 105°C unless otherwise specified.
The devices are shipped to customers with the flash memory erased.

Table 49. Flash memory characteristics

Symbol Parameter Conditions Min Typ Max Unit

Write / Erase 8-bit mode, VDD = 1.7 V - 5 -

IDD Supply current Write / Erase 16-bit mode, VDD = 2.1 V - 8 - mA
Write / Erase 32-bit mode, VDD = 3.3 V - 12 -

Table 50. Flash memory programming

Symbol Parameter Conditions Min(1) Typ Max(1) Unit

Program/erase parallelism
tprog Word programming time - 16 100(2) µs
(PSIZE) = x 8/16/32
Program/erase parallelism
- 400 800
(PSIZE) = x 8
Program/erase parallelism
tERASE16KB Sector (16 KB) erase time - 300 600 ms
(PSIZE) = x 16
Program/erase parallelism
- 250 500
(PSIZE) = x 32
Program/erase parallelism
- 1200 2400
(PSIZE) = x 8
Program/erase parallelism
tERASE64KB Sector (64 KB) erase time - 700 1400 ms
(PSIZE) = x 16
Program/erase parallelism
- 550 1100
(PSIZE) = x 32
Program/erase parallelism
- 2 4
(PSIZE) = x 8
Program/erase parallelism
tERASE128KB Sector (128 KB) erase time - 1.3 2.6 s
(PSIZE) = x 16
Program/erase parallelism
- 1 2
(PSIZE) = x 32

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Table 50. Flash memory programming (continued)

Symbol Parameter Conditions Min(1) Typ Max(1) Unit

Program/erase parallelism
- 16 32
(PSIZE) = x 8
Program/erase parallelism
tME Mass erase time - 11 22
(PSIZE) = x 16
Program/erase parallelism
- 8 16
(PSIZE) = x 32
s
Program/erase parallelism
- 16 32
(PSIZE) = x 8
Program/erase parallelism
tBE Bank erase time - 11 22
(PSIZE) = x 16
Program/erase parallelism
- 8 16
(PSIZE) = x 32
32-bit program operation 2.7 - 3.6
Vprog Programming voltage 16-bit program operation 2.1 - 3.6 V
8-bit program operation 1.7 - 3.6
1. Based on test during characterization.
2. The maximum programming time is measured after 100 K erase operations.

Table 51. Flash memory programming with VPP

Symbol Parameter Conditions Min(1) Typ Max(1) Unit

tprog Double word programming - 16 100(2) µs

tERASE16KB Sector (16 KB) erase time TA = 0 to +40 °C - 230 -
tERASE64KB Sector (64 KB) erase time VDD = 3.3 V - 490 - ms
tERASE128KB Sector (128 KB) erase time VPP = 8.5 V - 875 -
tME Mass erase time - 6.9 - s
tBE Bank erase time - - 6.9 - s
Vprog Programming voltage - 2.7 - 3.6
V
VPP VPP voltage range - 7 - 9
Minimum current sunk on
IPP - 10 - - mA
the VPP pin
Cumulative time during
tVPP(3) - - - 1 hour
which VPP is applied
1. Guaranteed by design.
2. The maximum programming time is measured after 100K erase operations.
3. VPP should only be connected during programming/erasing.

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Table 52. Flash memory endurance and data retention

Value
Symbol Parameter Conditions Unit
Min(1)

TA = –40 to +85 °C (6 suffix versions)

NEND Endurance 10 kcycles
TA = –40 to +105 °C (7 suffix versions)
1 kcycle(2) at TA = 85 °C 30
tRET (2)
Data retention 1 kcycle at TA = 105 °C 10 Years
(2)
10 kcycles at TA = 55 °C 20
1. Based on test during characterization.
2. Cycling performed over the whole temperature range.

5.3.17 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 53. They are based on the EMS levels and classes
defined in application note AN1709.

Table 53. EMS characteristics

Symbol Parameter Conditions Level/Class

VDD = 3.3 V, TFBGA216,

Voltage limits to be applied on any I/O pin
VFESD TA = +25 °C, fHCLK = 168 MHz, 2B
to induce a functional disturbance
conforming to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, TFBGA216,
VEFTB applied through 100 pF on VDD and VSS TA = +25 °C, fHCLK = 168 MHz, 4A
pins to induce a functional disturbance conforming to IEC 61000-4-2

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore, it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.

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Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application,
executing EEMBC? code, is running. This emission test is compliant with SAE IEC61967-2
standard, which specifies the test board and the pin loading.

Table 54. EMI characteristics for fHSE=8 MHz and fCPU=168 MHz
Max vs.
Monitored [fHSE/fCPU]
Symbol Parameter Conditions Unit
frequency band
8/168 MHz

0.1 to 30 MHz 2
VDD = 3.3 V, TA = 25 °C, TFBGA216
Peak(1) package, conforming to SAE J1752/3 30 to 130 MHz 4 dBµV
EEMBC, ART ON, all peripheral clocks 130 MHz to 1GHz 10
enabled, clock dithering disabled.
Level(2) 0.1 MHz to 1 GHz 3 -
SEMI
0.1 to 30 MHz 5
(1)
VDD = 3.3 V, TA = 25 °C, TFBGA216
Peak package, conforming to SAE J1752/3 30 to 130 MHz 3 dBµV
EEMBC, ART ON, all peripheral clocks 130 MHz to 1GHz 8
enabled, clock dithering enabled
Level(2) 0.1 MHz to 1 GHz 2 -

1. Refer to AN1709 “EMI radiated test” chapter.

2. Refer to AN1709 “EMI level classification” chapter.

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Table 55. EMI characteristics for fHSE=8 MHz and fCPU=180 MHz

Max vs.
Monitored [fHSE/fCPU]
Symbol Parameter Conditions Unit
frequency band
8/180 MHz

0.1 to 30 MHz 2
(1) VDD = 3.3 V, TA = 25 °C, TFBGA216
Peak package, conforming to SAE J1752/3 30 to 130 MHz 1 dBµV
EEMBC, ART ON, all peripheral clocks 130 MHz to 1GHz 10
enabled, clock dithering disabled.
Level(2) 0.1 MHz to 1 GHz 3 -
SEMI
0.1 to 30 MHz -10
VDD = 3.3 V, TA = 25 °C, TFBGA216
Peak(1) package, conforming to SAE J1752/3 30 to 130 MHz -15 dBµV
EEMBC, ART ON, all peripheral clocks 130 MHz to 1GHz 0
enabled, clock dithering enabled
Level(2) 0.1 MHz to 1 GHz 2 -

1. Refer to AN1709 “EMI radiated test” chapter.

2. Refer to AN1709 “EMI level classification” chapter.

5.3.18 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESD S5.3.1 standards.

Table 56. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)

Electrostatic discharge
TA = +25 °C
VESD(HBM) voltage 2 2000
conforming to ANSI/ESDA/JEDEC JS-001
(human body model)
TA = +25 °C conforming to ANSI/ESD S5.3.1, V
Electrostatic discharge
LQFP100, LQFP144, LQFP176, LQFP208,
VESD(CDM) voltage C3 250
UFBGA169, UFBGA176, TFBGA216 and
(charge device model)
WLCSP148 packages
1. Guaranteed based on test during characterization.

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Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output, and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latchup standard.

Table 57. Electrical sensitivities(1)

Symbol Parameter Conditions Class

LU Static latch-up class TA = +105 °C conforming to JESD78A II level A

1. MSV on PA4 and PA5 is 5 V, versus 5.4 V on all IOs.

5.3.19 I/O current injection characteristics

Generally, current injection to the I/O pins, due to external voltage below VSS or above VDD
(for standard, 3 V-capable I/O pins) should be avoided during normal product operation.
However, to give an indication of the robustness of the microcontroller in cases when
abnormal injection accidentally happens, susceptibility tests are performed on a sample
basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –
5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current by positive injection.
The test results are given in Table 58.

Table 58. I/O current injection susceptibility

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection

Injected current on BOOT0 and NRST pins −0 NA(1)

Injected current on DSIHOST_D0P,
DSIHOST_D0N, DSIHOST_D1P, DSIHOST_D0N, −0 0
DSIHOST_CKP, DSIHOST_CKN pins
IINJ mA
Injected current on PA0 and PC0 pins −0 NA(1)
Injected current on any other FT pin −5 NA(1)
Injected current on any other pin −5 +5

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1. Injection is not possible.

Note: It is recommended to add a Schottky diode (pin to ground) to analog pins, which may
potentially inject negative currents.

5.3.20 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 59 are derived from tests
performed under the conditions summarized in Table 17. All I/Os are CMOS and TTL
compliant.
Note: For information on GPIO configuration, refer to the application note AN4899 “STM32 GPIO
configuration for hardware settings and low-power consumption” available from
www.st.com.

Table 59. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

FT, TTa and NRST I/O input low 0.35VDD − 0.04(1)

1.7 V ≤ VDD ≤ 3.6 V - -
level voltage 0.3VDD(2)

VIL 1.75 V≤VDD ≤3.6 V,

- -
BOOT0 I/O input low level –40 °C≤TA ≤105 °C
0.1VDD+0.1(1)
voltage 1.7 V≤ VDD ≤ 3.6 V,
- -
0°C ≤ TA ≤ 105°C
V
FT, TTa and NRST I/O input 0.45VDD+0.3(1)
1.7 V ≤ VDD ≤ 3.6 V - -
high level voltage(5) 0.7VDD(2)

VIH 1.75 V≤ VDD ≤ 3.6 V,

BOOT0 I/O input high level –40 °C ≤ TA ≤105 °C
0.17VDD+0.7(1) - -
voltage 1.7 V≤ VDD ≤ 3.6 V,
0 °C ≤ TA ≤ 105 °C
FT, TTa and NRST I/O input
1.7 V ≤ VDD ≤ 3.6 V 10%VDD(3) - -
hysteresis
1.75 V≤ VDD ≤ 3.6 V,
VHYS V
–40 °C≤ TA ≤ 105 °C
BOOT0 I/O input hysteresis 0.1 - -
1.7 V ≤ VDD ≤ 3.6 V,
0 °C≤ TA ≤105 °C
I/O input leakage current (4) VSS ≤ VIN ≤ VDD - - ±1
Ilkg µA
(5)
I/O FT input leakage current VIN = 5 V - - 3

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Table 59. I/O static characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

All pins
except for
PA10/PB12 30 40 50
Weak pull-up (OTG_FS_ID,
RPU equivalent OTG_HS_ID) VIN = VSS
resistor(6)
PA10/PB12
(OTG_FS_ID, 7 10 14
OTG_HS_ID)
kΩ
All pins
except for
Weak pull- PA10/PB12 30 40 50
down (OTG_FS_ID,
RPD OTG_HS_ID) VIN = VDD
equivalent
resistor(7) PA10/PB12
(OTG_FS_ID, 7 10 14
OTG_HS_ID)
CIO(8) I/O pin capacitance - - 5 - pF
1. Guaranteed by design.
2. Tested in production.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, refer to Table 58
5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 58
6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the
series resistance is minimum (~10%).
7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the
series resistance is minimum (~10%).
8. Hysteresis voltage between Schmitt trigger switching levels. Based on test during characterization.

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Electrical characteristics STM32F469xx

All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 39.

Figure 39. FT I/O input characteristics

VIL/VIH (V)

2.52 DD
7V
0.
=
in
I Hm
tV
en
m
ire
qu TTL requirement
re VIHmin = 2V
2.0 OS .3
1.92 - CM +0
DD
tio
n
. 4 5V
1.7 uc in =0
od IHm
pr ,V
in s
te
d tion
s ula
Te sim
n
esig
1.22 nD Area not
1.19 e do -0.0
4
as determined VDD
1.065
B
x= 0.35
I Lma
ns, V
sim ulatio
0.8 sign
n De
ed o
TTL requirement VILmax
Bas
0.55 = 0.8V
0.51
Tested in production - CMOS requirement VILmax = 0.3VDD

VDD (V)
1.7 2.0 2.4 2.7 3.3 3.6
MS33746V1

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14, PC15, and PI8, which
can sink or source up to ±3 mA. When using the PC13 to PC15 and PI8 GPIOs in output
mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins, which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2. In particular:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
∑IVDD (see Table 15).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
∑IVSS (see Table 15).

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Output voltage levels

Unless otherwise specified, the parameters given in Table 60 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 17. All I/Os are CMOS and TTL compliant.

Table 60. Output voltage characteristics

Symbol Parameter Conditions Min Max Unit

VOL(1) Output low level voltage for an I/O pin CMOS port (2)
- 0.4
IIO = +8 mA
VOH(3) Output high level voltage for an I/O pin
2.7 V ≤ VDD ≤ 3.6 V
VDD − 0.4 -

VOL (1) Output low level voltage for an I/O pin TTL port(2) - 0.4
IIO =+ 8mA
VOH (3) Output high level voltage for an I/O pin 2.4 -
2.7 V ≤ VDD ≤ 3.6 V
VOL(1) Output low level voltage for an I/O pin IIO = +20 mA - 1.3(4) V
VOH(3) Output high level voltage for an I/O pin 2.7 V ≤ VDD ≤ 3.6 V VDD −1.3(4) -
VOL(1) Output low level voltage for an I/O pin IIO = +6 mA - 0.4(4)
VOH(3) Output high level voltage for an I/O pin 1.8 V ≤ VDD ≤ 3.6 V VDD −0.4(4) -
VOL(1) Output low level voltage for an I/O pin IIO = +4 mA - 0.4(5)
VOH(3) Output high level voltage for an I/O pin 1.7 V ≤ VDD ≤ 3.6V VDD −0.4(5) -
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 15.
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 15 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Based on characterization data.
5. Guaranteed by design.

Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 40 and
Table 61, respectively.
Unless otherwise specified, the parameters given in Table 61 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 17.

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Table 61. I/O AC characteristics(1)(2)

OSPEEDRy
[1:0] bit Symbol Parameter Conditions Min Typ Max Unit
value(1)

CL = 50 pF, VDD ≥ 2.7 V - - 4

CL = 50 pF, VDD ≥ 1.7 V - - 2
fmax(IO)out (3)
Maximum frequency CL = 10 pF, VDD ≥ 2.7 V - - 8 MHz

00 CL = 10 pF, VDD ≥ 1.8 V - - 4

CL = 10 pF, VDD ≥ 1.7 V - - 3
Output high to low level fall
tf(IO)out/ CL = 50 pF, VDD = 1.7 V to
time and output low to high - - 100 ns
tr(IO)out 3.6 V
level rise time
CL = 50 pF, VDD≥ 2.7 V - - 25
CL = 50 pF, VDD≥ 1.8 V - - 12.5
CL = 50 pF, VDD≥ 1.7 V - - 10
fmax(IO)out Maximum frequency(3) MHz
CL = 10 pF, VDD ≥ 2.7 V - - 50
CL = 10 pF, VDD≥ 1.8 V - - 20
01
CL = 10 pF, VDD≥ 1.7 V - - 12.5
CL = 50 pF, VDD ≥ 2.7 V - - 10
Output high to low level fall CL = 10 pF, VDD ≥ 2.7 V - - 6
tf(IO)out/
time and output low to high ns
tr(IO)out CL = 50 pF, VDD ≥ 1.7 V - - 20
level rise time
CL = 10 pF, VDD ≥ 1.7 V - - 10
CL = 40 pF, VDD ≥ 2.7 V - - 50(4)
CL = 10 pF, VDD ≥ 2.7 V - - 100(4)
fmax(IO)out Maximum frequency(3) CL = 40 pF, VDD ≥ 1.7 V - - 25 MHz
CL = 10 pF, VDD ≥ 1.8 V - - 50
10 CL = 10 pF, VDD ≥ 1.7 V - - 42.5
CL = 40 pF, VDD ≥2.7 V - - 6
Output high to low level fall CL = 10 pF, VDD ≥ 2.7 V - - 4
tf(IO)out/
time and output low to high ns
tr(IO)out CL = 40 pF, VDD ≥ 1.7 V - - 10
level rise time
CL = 10 pF, VDD ≥ 1.7 V - - 6

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Table 61. I/O AC characteristics(1)(2) (continued)

OSPEEDRy
[1:0] bit Symbol Parameter Conditions Min Typ Max Unit
value(1)

CL = 30 pF, VDD ≥ 2.7 V - - 100(4)

CL = 30 pF, VDD ≥ 1.8 V - - 50
CL = 30 pF, VDD ≥ 1.7 V - - 42.5
fmax(IO)out Maximum frequency(3) MHz
CL = 10 pF, VDD≥ 2.7 V - - 180(4)
CL = 10 pF, VDD ≥ 1.8 V - - 100
CL = 10 pF, VDD ≥ 1.7 V - - 72.5
11
CL = 30 pF, VDD ≥ 2.7 V - - 4
CL = 30 pF, VDD ≥1.8 V - - 6
Output high to low level fall CL = 30 pF, VDD ≥1.7 V - - 7
tf(IO)out/
time and output low to high ns
tr(IO)out CL = 10 pF, VDD ≥ 2.7 V - - 2.5
level rise time
CL = 10 pF, VDD ≥1.8 V - - 3.5
CL = 10 pF, VDD ≥1.7 V - - 4
Pulse width of external signals
- tEXTIpw detected by the EXTI - 10 - - ns
controller
1. Guaranteed by design.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of
the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 40.
4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used.

Figure 40. I/O AC characteristics definition

90% 10%

50% 50%

10% 90%

t r(IO)out t f(IO)out

Maximum frequency is achieved with a duty cycle at (45 - 55%) when loaded by the
specified capacitance.

MS32132V4

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5.3.21 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 59).
Unless otherwise specified, the parameters given in Table 62 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 17.

Table 62. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

RPU Weak pull-up equivalent resistor(1) VIN = VSS 30 40 50 kΩ

VF(NRST) (2) NRST Input filtered pulse - - - 100
ns
VNF(NRST)(2) NRST Input not filtered pulse VDD > 2.7 V 300 - -
TNRST_OUT Generated reset pulse duration Internal Reset source 20 - - µs
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10%).
2. Guaranteed by design.

Figure 41. Recommended NRST pin protection

VDD
External
reset circuit (1)
RPU
NRST (2) Internal Reset
Filter

0.1 μF

STM32F

ai14132c

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 59. Otherwise, the reset is not taken into account by the device.

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5.3.22 TIM timer characteristics

The parameters given in Table 63 are guaranteed by design. Refer to Section 5.3.20 for
details on the input/output alternate function characteristics (output compare, input capture,
external clock, PWM output).

Table 63. TIMx characteristics(1)(2)

Symbol Parameter Conditions(3) Min Max Unit

AHB/APBx prescaler =
1 or 2 or 4, 1 - tTIMxCLK
tres(TIM) fTIMxCLK = 180 MHz
Timer resolution time
AHB/APBx prescaler > 4,
1 - tTIMxCLK
fTIMxCLK = 90 MHz

Timer external clock

fEXT 0 fTIMxCLK/2 MHz
frequency on CH1 to CH4 f
TIMxCLK = 180 MHz
ResTIM Timer resolution - 16/32 bit
Maximum possible count 65536 ×
tMAX_COUNT - - tTIMxCLK
with 32-bit counter 65536
1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 180 MHz, by setting the TIMPRE bit in the
RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise TIMxCLK =
4x PCLKx.

5.3.23 Communications interfaces

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): bit rate up to 100 Kbit/s
• Fast-mode (Fm): bit rate up to 400 Kbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0386 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDD is disabled, but is still present. Refer to
Section 5.3.20 for more details on the I2C I/O characteristics.
All I2C SDA and SCL I/Os embed an analog filter, whose characteristics are detailed in
Table 64.

Table 64. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit

Maximum pulse width of spikes

tAF 50(2) 150(3) ns
suppressed by the analog filter
1. Guaranteed based on test during characterization.

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2. Spikes with widths below tAF(min) are filtered.

3. Spikes with widths above tAF(max) are not filtered.

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 65 for the SPI interface are
derived from tests performed under the ambient temperature, fPCLKx frequency, and VDD
supply voltage conditions summarized in Table 17, with the following configuration:
• output speed set to OSPEEDRy[1:0] = 10
• capacitive load C = 30 pF
• measurement points at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output alternate function characteristics
(NSS, SCK, MOSI, MISO for SPI).

Table 65. SPI dynamic characteristics(1)

Symbol Parameter Conditions Min Typ Max(2) Unit

Master mode,
2.7 V ≤ VDD ≤ 3.6 V, - - 45
SPI1,4,5,6,
Master mode,
1.71 V ≤ VDD ≤ 3.6 V, - - 22.5
SPI1,4,5,6
Master transmitter mode,
1.7 V ≤ VDD ≤ 3.6 V, - - 45
SPI1,4,5,6

fSCK Slave full duplex mode,

SPI clock frequency 2.7 V ≤ VDD ≤ 3.6 V, - - 45 MHz
1/tc(SCK)
SPI1,4,5,6
Slave transmitter mode,
1.71 V ≤ VDD ≤ 3.6 V, - - 33
SPI1,4,5,6
Slave transmitter mode,
2.7 V ≤ VDD ≤ 3.6 V, - - 45
SPI1,4,5,6
Slave mode,
1.71 V ≤ VDD ≤ 3.6 V, - - 22.5
SPI2,3
Duty cycle of SPI
Duty(SCK) Slave mode 30 50 70 %
clock frequency

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Table 65. SPI dynamic characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max(2) Unit

tw(SCKH)
SCK high and low time Master mode, SPI presc = 2 TPCLK−1.5 TPCLK TPCLK+1.5
tw(SCKL)
tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4 TPCLK
- -
th(NSS) NSS hold time Slave mode, SPI presc = 2 2 TPCLK
tsu(MI) Master mode 2 - -
Data input setup time
tsu(SI) Slave mode 3 - -
th(MI) Master mode 4 - -
Data input hold time
th(SI) Slave mode 2 - -
ta(SO) Data output access time Slave mode, SPI presc = 2 7 - 21 ns

tdis(SO) Data output disable time Slave mode 5 - 12

Slave mode,
- 11 15
2.7 V ≤ VDD ≤ 3.6 V
tv(SO) Data output valid time
Slave mode,
- 11 11.5
1.71 V ≤ VDD ≤ 3.6 V
th(SO) Data output hold time Slave mode 6 - -
tv(MO) Data output valid time Master mode - 4.5 5
th(MO) Data output hold time Master mode 2 - -
1. Guaranteed based on test during characterization.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI), which has to fit into SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%

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Figure 42. SPI timing diagram - slave mode and CPHA = 0

NSS input

tc(SCK) th(NSS)

tsu(NSS) tw(SCKH)
CPHA=0
SCK input

CPOL=0

CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V2

Figure 43. SPI timing diagram - slave mode and CPHA = 1

NSS input

tc(SCK) th(NSS)
tsu(NSS) tw(SCKH)
CPHA=1
SCK input

CPOL=0

CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41659V2

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Figure 44. SPI timing diagram - master mode

High

NSS input
tc(SCK)
tw(SCKH)
CPHA=0
SCK output

CPOL=0

CPHA=0
CPOL=1
tw(SCKL)
CPHA=1
SCK output

CPOL=0

CPHA=1
CPOL=1
tsu(MI) th(MI)

MISO input First bit IN Next bits IN Last bit IN

MOSI output First bit OUT Next bits OUT Last bit OUT

tv(MO) th(MO)
MSv72626V1

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I2S interface characteristics

Unless otherwise specified, the parameters given in Table 66 for the I2S interface are
derived from tests performed under the ambient temperature, fPCLKx frequency, and VDD
supply voltage conditions summarized in Table 17, with the following configuration:
• output speed set to OSPEEDRy[1:0] = 10
• capacitive load C = 30 pF
• measurement points at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output alternate function characteristics
(CK, SD, WS).

Table 66. I2S dynamic characteristics(1)

Symbol Parameter Conditions Min Max Unit

fMCK I2S main clock output - 256x8K 256xFs(2)

Master data - 64xFs MHz
fCK I2S clock frequency
Slave data - 64xFs
DCK I2S clock frequency duty cycle Slave receiver 30 70 %
tv(WS) WS valid time Master mode 0 5
th(WS) WS hold time Master mode 0 -
Slave mode 3.5 -
tsu(WS) WS setup time Slave mode
3.5 -
PCM short pulse mode(3)
Slave mode 0.5 -
th(WS) WS hold time Slave mode
1 -
PCM short pulse mode(3)
tsu(SD_MR) Master receiver 5 - ns
Data input setup time
tsu(SD_SR) Slave receiver 1.5 -
th(SD_MR) Master receiver 5 -
Data input hold time
th(SD_SR) Slave receiver 1.5 -
tv(SD_ST) Slave transmitter (after enable edge) - 19
Data output valid time
tv(SD_MT) Master transmitter (after enable edge) - 2.50
th(SD_ST) Slave transmitter (after enable edge) 5 -
Data output hold time
th(SD_MT) Master transmitter (after enable edge) 0 -
1. Guaranteed based on test during characterization.
2. 128xFs maximum is 24.756 MHz (APB1 Maximum frequency).
3. Measurement done with respect to I2S_CK rising edge.

Note: Refer to the I2S section of RM0386 reference manual for more details on the sampling
frequency (FS).
fMCK, fCK, and DCK values reflect only the digital peripheral behavior, source clock precision
might slightly change the values. The values of these parameters might be slightly impacted
by the source clock precision. DCK depends mainly on the value of ODD bit. The digital

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contribution leads to a minimum value of (I2SDIV/(2*I2SDIV+ODD) and a maximum value of

(I2SDIV+ODD)/(2*I2SDIV+ODD). FS maximum value is supported for each mode/condition.

Figure 45. I2S slave timing diagram (Philips protocol)(1)

tc(CK)

CPOL = 0
CK Input

CPOL = 1

tw(CKH) tw(CKL) th(WS)

WS input

tsu(WS) tv(SD_ST) th(SD_ST)

SDtransmit
LSB transmit(2) MSB transmit Bitn transmit LSB transmit

tsu(SD_SR) th(SD_SR)

SDreceive LSB receive(2) MSB receive Bitn receive LSB receive

ai14881b

1. .LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

Figure 46. I2S master timing diagram (Philips protocol)(1)

tf(CK) tr(CK)

tc(CK)
CK output

CPOL = 0
tw(CKH)

CPOL = 1
tv(WS) tw(CKL) th(WS)

WS output

tv(SD_MT) th(SD_MT)

SDtransmit LSB transmit(2) MSB transmit Bitn transmit LSB transmit

tsu(SD_MR) th(SD_MR)

SDreceive LSB receive(2) MSB receive Bitn receive LSB receive

ai14884b

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

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SAI characteristics
Unless otherwise specified, the parameters given in Table 67 for SAI are derived from tests
performed under the ambient temperature, fPCLKx frequency, and VDD supply voltage
conditions summarized in Table 17, with the following configuration:
• output speed set to OSPEEDRy[1:0] = 10
• capacitive load C=30 pF
• measurement points at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output alternate function
characteristics (SCK, SD, WS).

Table 67. SAI characteristics(1)

Symbol Parameter Conditions Min Max Unit

fMCKL SAI main clock output - 256 x 8K 256xFs

Master data: 32 bits - 128xFs(3) MHz
fCK SAI clock frequency(2)
Slave data: 32 bits - 128xFs
Master mode,
- 17
2.7 V ≤ VDD ≤ 3.6 V
tv(FS) FS valid time
Master mode,
- 23
1.71 V ≤ VDD ≤ 3.6 V
tsu(FS) FS setup time Slave mode 10 -
th(FS) FS hold time Slave mode 0 -
tsu(SD_MR) Master receiver 1 -
Data input setup time
tsu(SD_SR) Slave receiver 2 -
th(SD_MR) Master receiver 6 -
Data input hold time
th(SD_SR) Slave receiver 1 - ns
Slave transmitter (after enable edge),
- 14
2.7 V ≤ VDD ≤ 3.6 V
th(SD_B_ST) Data output valid time
Slave transmitter (after enable edge),
- 23
1.71 V ≤ VDD ≤ 3.6 V
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 9 -
Master transmitter (after enable edge),
- 20
2.7 V ≤ VDD ≤ 3.6 V
tv(SD_A_MT) Data output valid time
Master transmitter (after enable edge),
- 26
1.71 V ≤ VDD ≤ 3.6 V
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 10 -
1. Guaranteed based on test during characterization.
2. APB clock frequency must be at least twice SAI clock frequency.
3. With Fs = 192 kHz.

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Figure 47. SAI master timing waveforms

1/fSCK

SAI_SCK_X
th(FS)

SAI_FS_X
(output) tv(FS) tv(SD_MT) th(SD_MT)

SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_MR) th(SD_MR)

SAI_SD_X Slot n
(receive)
MS32771V1

Figure 48. SAI slave timing waveforms

1/fSCK

SAI_SCK_X
tw(CKH_X) tw(CKL_X) th(FS)

SAI_FS_X
(input) tsu(FS) tv(SD_ST) th(SD_ST)

SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_SR) th(SD_SR)

SAI_SD_X Slot n
(receive)
MS32772V1

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USB OTG full speed (FS) characteristics

This interface is present in both the USB OTG HS and USB OTG FS controllers.

Table 68. USB OTG full speed startup time

Symbol Parameter Max Unit

tSTARTUP(1) USB OTG full speed transceiver startup time 1 µs

1. Guaranteed by design.

Table 69. USB OTG full speed DC electrical characteristics

Symbol Parameter Conditions Min.(1) Typ. Max.(1) Unit

USB OTG full speed

VDD transceiver operating - 3.0(2) - 3.6
voltage
I(USB_FS_DP/DM,
Input VDI(3) Differential input sensitivity 0.2 - -
USB_HS_DP/DM)
levels
Differential common mode V
VCM(3) Includes VDI range 0.8 - 2.5
range
Single ended receiver
VSE(3) - 1.3 - 2.0
threshold

Output VOL Static output level low RL of 1.5 kΩ to 3.6 V(4) - - 0.3
levels VOH Static output level high RL of 15 kΩ to VSS(4) 2.8 - 3.6
PA11, PA12, PB14, PB15
(USB_FS_DP/DM, 17 21 24
USB_HS_DP/DM)
RPD VIN = VDD
PA9, PB13
(OTG_FS_VBUS, 0.65 1.1 2.0
OTG_HS_VBUS) kΩ
PA12, PB15 (USB_FS_DP,
VIN = VSS 1.5 1.8 2.1
USB_HS_DP)
RPU PA9, PB13
(OTG_FS_VBUS, VIN = VSS 0.25 0.37 0.55
OTG_HS_VBUS)
1. All the voltages are measured from the local ground potential.
2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed
electrical characteristics, which are degraded in the 2.7 to 3.0 V VDD voltage range.
3. Guaranteed by design.
4. RL is the load connected on the USB OTG full speed drivers.

Note: When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state
(floating input), not as alternate function. A typical 200 µA current consumption of the
sensing block (current to voltage conversion to determine the different sessions) can be
observed on PA9 and PB13 when the feature is enabled.

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Figure 49. USB OTG full speed timings: definition of data signal rise and fall time
Cross over
points
Differential
data lines

VCRS

VSS

tf tr
ai14137b

Table 70. USB OTG full speed electrical characteristics(1)

Driver characteristics

Symbol Parameter Conditions Min Max Unit

tr Rise time(2) CL = 50 pF 4 20
ns
tf Fall time(2) CL = 50 pF 4 20
trfm Rise/ fall time matching t r / tf 90 110 %
VCRS Output signal crossover voltage - 1.3 2.0 V
Driving
ZDRV Output driver impedance(3) 28 44 Ω
high or low
1. Guaranteed by design.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching
impedance is included in the embedded driver.

USB high speed (HS) characteristics

Unless otherwise specified, the parameters given in Table 73 for ULPI are derived from
tests performed under the ambient temperature, fHCLK frequency summarized in Table 72
and VDD supply voltage conditions summarized in Table 71, with the following configuration:
• output speed set to OSPEEDRy[1:0] = 11, unless otherwise specified
• capacitive load C = 20 pF / 15 pF, unless otherwise specified
• measurement points at CMOS levels: 0.5 VDD.
Refer to Section 5.3.20 for more details on the input/output characteristics.

Table 71. USB HS DC electrical characteristics

Symbol Parameter Min.(1) Max.(1) Unit

Input level VDD USB OTG HS operating voltage 1.7 3.6 V

1. All the voltages are measured from the local ground potential.

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Table 72. USB HS clock timing parameters(1)

Symbol Parameter Min Typ Max Unit

fHCLK value to guarantee proper operation of

- 30 - -
USB HS interface
MHz
FSTART_8BIT Frequency (first transition) 8-bit ±10% 54 60 66
FSTEADY Frequency (steady state) ±500 ppm 59.97 60 60.03
DSTART_8BIT Duty cycle (first transition) 8-bit ±10% 40 50 60
%
DSTEADY Duty cycle (steady state) ±500 ppm 49.975 50 50.025
Time to reach the steady state frequency and
tSTEADY - - 1.4 ms
duty cycle after the first transition
tSTART_DEV Clock startup time after the Peripheral - - 5.6
ms
tSTART_HOST de-assertion of SuspendM Host - - -
PHY preparation time after the first transition
tPREP - - - µs
of the input clock
1. Guaranteed by design.

Figure 50. ULPI timing diagram

Clock

tSC tHC
Control In
(ULPI_DIR,
ULPI_NXT) tSD tHD
data In
(8-bit)

tDC tDC
Control out
(ULPI_STP)
tDD
data out
(8-bit)
ai17361c

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Table 73. Dynamic characteristics: USB ULPI(1)

Symbol Parameter Conditions Min. Typ. Max. Unit

Control in (ULPI_DIR, ULPI_NXT)

tSC - 2.0 - -
setup time
Control in (ULPI_DIR, ULPI_NXT)
tHC - 1.5 - -
hold time
tSD Data in setup time - 1.0 - -
tHD Data in hold time - 1.0 - -
2.7 V < VDD < 3.6 V, ns
- 7.5 9.0
CL = 20 pF
2.7 V < VDD < 3.6 V,
CL = 15 pF and - 7.5 12.0
tDC/tDD Data/control output delay
-40 < T < 125°C
1.7 V < VDD < 3.6 V,
CL = 15 pF and - 7.5 11.5
-40 < T < 90°C
1. Guaranteed based on test during characterization.

Ethernet characteristics
Unless otherwise specified, the parameters given in Table 74, Table 75 and Table 76 for
SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK
frequency, and VDD supply voltage conditions summarized in Table 17, with the following
configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD.
Refer to Section 5.3.20 for more details on the input/output characteristics.
Table 74 gives the list of Ethernet MAC signals for the SMI (station management interface)
and Figure 51 shows the corresponding timing diagram.

Figure 51. Ethernet SMI timing diagram

tMDC

ETH_MDC

td(MDIO)

ETH_MDIO(O)

tsu(MDIO) th(MDIO)

ETH_MDIO(I)

MS31384V1

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Table 74. Dynamics characteristics: Ethernet MAC signals for SMI(1)

Symbol Parameter Min Typ Max Unit

tMDC MDC cycle time(2.38 MHz) 400 400 403

Td(MDIO) Write data valid time THCLK - 1 THCLK THCLK + 1.5
ns
tsu(MDIO) Read data setup time 12.5 - -
th(MDIO) Read data hold time 0 - -
1. Guaranteed based on test during characterization.

Table 75 gives the list of Ethernet MAC signals for the RMII and Figure 52 shows the
corresponding timing diagram.

Figure 52. Ethernet RMII timing diagram

RMII_REF_CLK

td(TXEN)
td(TXD)

RMII_TX_EN
RMII_TXD[1:0]
tsu(RXD) tih(RXD)
tsu(CRS) tih(CRS)

RMII_RXD[1:0]
RMII_CRS_DV

ai15667

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Table 75. Dynamics characteristics: Ethernet MAC signals for RMII(1)

Symbol Parameter Min Typ Max Unit

tsu(RXD) Receive data setup time 2.5 - -

tih(RXD) Receive data hold time 2.0 - -
tsu(CRS) Carrier sense setup time 0.5 - -
ns
tih(CRS) Carrier sense hold time 1.5 - -
td(TXEN) Transmit enable valid delay time 5.5 6.5 11
td(TXD) Transmit data valid delay time 6.0 6.5 11
1. Guaranteed based on test during characterization.

Table 76 gives the list of Ethernet MAC signals for MII and Figure 52 shows the
corresponding timing diagram.

Figure 53. Ethernet MII timing diagram

MII_RX_CLK
tsu(RXD) tih(RXD)
tsu(ER) tih(ER)
tsu(DV) tih(DV)
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER

MII_TX_CLK

td(TXEN)
td(TXD)

MII_TX_EN
MII_TXD[3:0]

ai15668

Table 76. Dynamics characteristics: Ethernet MAC signals for MII(1)

Symbol Parameter Min Typ Max Unit

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Table 76. Dynamics characteristics: Ethernet MAC signals for MII(1)

tsu(RXD) Receive data setup time 1 - -
tih(RXD) Receive data hold time 3 - -
tsu(DV) Data valid setup time 0 - -
tih(DV) Data valid hold time 2.5 - -
ns
tsu(ER) Error setup time 0 - -
tih(ER) Error hold time 2 - -
td(TXEN) Transmit enable valid delay time 0 7 13
td(TXD) Transmit data valid delay time 0 7 13
1. Guaranteed based on test during characterization.

CAN (controller area network) interface

Refer to Section 5.3.20 for more details on the input/output alternate function characteristics
(CANx_TX and CANx_RX).

5.3.24 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 77 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 17.

Table 77. ADC characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDDA Power supply 1.7(1) - 3.6

VREF+ Positive reference voltage VDDA - VREF+ < 1.2 V 1.7(1) - VDDA V
VREF- Negative reference voltage - 0 -
VDDA = 1.7(1) to 2.4 V 0.6 15 18
fADC ADC clock frequency MHz
VDDA = 2.4 to 3.6 V 0.6 30 36
fADC = 30 MHz,
- - 1764 kHz
fTRIG(2) External trigger frequency 12-bit resolution
- - - 17 1/fADC
0
VAIN Conversion voltage range(3) - (VSSA or VREF- - VREF+ V
tied to ground)
RAIN(2) External input impedance Details in Equation 1 - - 50 kΩ
RADC (2)(4)
Sampling switch resistance - - - 6 kΩ
Internal sample and hold
CADC(2) - - 4 7 pF
capacitor

Injection trigger conversion fADC = 30 MHz - - 0.100 µs

tlat(2)
latency - - - 3(5) 1/fADC

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Table 77. ADC characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

Regular trigger conversion fADC = 30 MHz - - 0.067 µs

tlatr(2)
latency - - 2(5) 1/fADC
fADC = 30 MHz 0.100 - 16 µs
tS(2) Sampling time
- 3 - 480 1/fADC
tSTAB(2) Power-up time - - 2 3 µs
fADC = 30 MHz
0.50 - 16.40
12-bit resolution
fADC = 30 MHz
0.43 - 16.34
10-bit resolution
µs
Total conversion time fADC = 30 MHz
tCONV(2) 0.37 - 16.27
(including sampling time) 8-bit resolution
fADC = 30 MHz
0.30 - 16.20
6-bit resolution
9 to 492
1/fADC
(tS for sampling +n-bit resolution for successive approximation)
12-bit resolution
- - 2
Single ADC

Sampling rate 12-bit resolution

Interleave Dual ADC - - 3.75
fS(2) (fADC = 30 MHz, and Msps
mode
tS = 3 ADC cycles)
12-bit resolution
Interleave Triple ADC - - 6
mode
ADC VREF
IVREF+(2) DC current consumption in - - 300 500 µA
conversion mode
ADC VDDA
IVDDA(2) DC current consumption in - - 1.6 1.8 mA
conversion mode
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).
2. Based on test during characterization.
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.
5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 77.

Equation 1: RAIN max formula

( k – 0.5 )
R AIN = ---------------------------------------------------------------------------- – R ADC
N+2
f ADC × C ADC × ln ( 2 )

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191
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The above formula (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.

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Table 78. ADC static accuracy at fADC = 18 MHz(1)

Symbol Parameter Test conditions Typ Max(2) Unit

ET Total unadjusted error ±3 ±4

fADC =18 MHz
EO Offset error ±2 ±3
VDDA = 1.7 to 3.6 V
LSB
EG Gain error VREF = 1.7 to 3.6 V ±1 ±3
ED Differential linearity error VDDA - VREF < 1.2 V ±1 ±2
EL Integral linearity error ±2 ±3
1. Better performance could be achieved in restricted VDD, frequency, and temperature ranges.
2. Based on test during characterization.

Table 79. ADC static accuracy at fADC = 30 MHz(1)

a

Symbol Parameter Test conditions Typ Max(2) Unit

ET Total unadjusted error ±2 ±5

fADC = 30 MHz,
EO Offset error ±1.5 ±2.5
RAIN < 10 kΩ
EG Gain error VDDA = 2.4 to 3.6 V, ±1.5 ±3 LSB
VREF = 1.7 to 3.6 V,
ED Differential linearity error ±1 ±2
VDDA - VREF < 1.2 V
EL Integral linearity error ±1.5 ±3
1. Better performance could be achieved in restricted VDD, frequency, and temperature ranges.
2. Based on test during characterization.

Table 80. ADC static accuracy at fADC = 36 MHz(1)

Symbol Parameter Test conditions Typ Max(2) Unit

ET Total unadjusted error ±4 ±7

EO Offset error fADC =36 MHz, ±2 ±3

VDDA = 2.4 to 3.6 V,
EG Gain error ±3 ±6 LSB
VREF = 1.7 to 3.6 V
ED Differential linearity error VDDA - VREF < 1.2 V ±2 ±3
EL Integral linearity error ±3 ±6
1. Better performance could be achieved in restricted VDD, frequency, and temperature ranges.
2. Based on test during characterization.

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Table 81. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1)
Symbol Parameter Test conditions Min Typ Max Unit

ENOB Effective number of bits 10.3 10.4 - bits

fADC =18 MHz
SINAD Signal-to-noise and distortion ratio VDDA = VREF+= 1.7 V 64 64.2 -
SNR Signal-to-noise ratio Input Frequency = 20 KHz 64 65 - dB
Temperature = 25 °C
THD Total harmonic distortion − 67 − 72 -
1. Guaranteed based on test during characterization.

Table 82. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1)
Symbol Parameter Test conditions Min Typ Max Unit

ENOB Effective number of bits 10.6 10.8 - bits

fADC =36 MHz
SINAD Signal-to noise and distortion ratio VDDA = VREF+ = 3.3 V 66 67 -
SNR Signal-to noise ratio Input Frequency = 20 KHz 64 68 - dB
Temperature = 25 °C
THD Total harmonic distortion − 70 − 72 -
1. Guaranteed based on test during characterization.

Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins, which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ∑IINJ(PIN) in
Section 5.3.20 does not affect the ADC accuracy.

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Figure 54. ADC accuracy characteristics

V REF+ V DDA
[1LSB IDEAL = (or depending on package)]
4096 4096
EG
4095
4094
4093

(2)
ET
7 (3)
(1)
6
5
EO EL
4
3
ED
2
1L SBIDEAL
1

0
1 2 3 456 7 4093 4094 4095 4096
V SSA VDDA
ai14395c

1. See also Table 79.

2. Example of an actual transfer curve.
3. Ideal transfer curve.
4. End point correlation line.
5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.

Figure 55. Typical connection diagram using the ADC with FT/TT pins featuring

VDDA(4) VREF+(4)

I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter
(2)
Cparasitic Ilkg(3) CADC
VAIN Sampling
switch with
multiplexing

VSS VSS VSSA

MSv67871V3

analog switch funcion

1. Refer to Table 77 for the values of RAIN, RADC, and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 59: I/O static characteristics). A high Cparasitic value downgrades
conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 59: I/O static characteristics for the value of llkg.
4. Refer to Table 24: Power supply scheme.

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General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 56 or Figure 57,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 56. Power supply and reference decoupling (VREF+ not connected to VDDA)

STM32F

VREF+(1)

1 μF // 10 nF
VDDA

1 μF // 10 nF

VSSA/VREF+(1)

MS38278V1

1. VREF+ and VREF– inputs are both available on UFBGA176 and TFBGA216. VREF+ is also available on
LQFP100, LQFP144, LQFP176, and LQFP208. When VREF+ and VREF– are not available, they are
internally connected to VDDA and VSSA.

Figure 57. Power supply and reference decoupling (VREF+ connected to VDDA)

STM32F

VREF+/VDDA(1)

1 μF // 10 nF

VREF-/VDDA(1)

MS38279V1

1. VREF+ and VREF– inputs are both available on UFBGA176 and TFBGA216. VREF+ is also available on
LQFP100, LQFP144, LQFP176, and LQFP208. When VREF+ and VREF– are not available, they are
internally connected to VDDA and VSSA.

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5.3.25 Temperature sensor characteristics

Table 83. Temperature sensor characteristics

Symbol Parameter Min Typ Max Unit

TL(1) VSENSE linearity with temperature - ±1 ±2 °C

(1)
Avg_Slope Average slope - 2.5 - mV/°C
V25(1) Voltage at 25 °C - 0.76 - V
tSTART(2) Startup time - 6 10
µs
TS_temp(2) ADC sampling time when reading the temperature (1 °C accuracy) 10 - -
1. Based on test during characterization.
2. Guaranteed by design.

Table 84. Temperature sensor calibration values

Symbol Parameter Memory address

TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D
TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F

5.3.26 VBAT monitoring characteristics

Table 85. VBAT monitoring characteristics

Symbol Parameter Min Typ Max Unit

R Resistor bridge for VBAT - 50 - KΩ

Q Ratio on VBAT measurement - 4 -
Er(1) Error on Q –1 - +1 %
ADC sampling time when reading the VBAT
TS_vbat(2)(2) 5 - - µs
1 mV accuracy
1. Guaranteed by design.
2. Shortest sampling time can be determined in the application by multiple iterations.

5.3.27 Reference voltage

The parameters given in Table 86 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 17.

Table 86. internal reference voltage

Symbol Parameter Conditions Min Typ Max Unit

VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.18 1.21 1.24 V
ADC sampling time when reading the
TS_vrefint(1) 10 - - µs
internal reference voltage
Internal reference voltage spread over the
VRERINT_s(2) VDD = 3V ± 10mV - 3 5 mV
temperature range

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Table 86. internal reference voltage (continued)

Symbol Parameter Conditions Min Typ Max Unit

TCoeff(2) Temperature coefficient - 30 50 ppm/°C

tSTART(2) Startup time - 6 10 µs
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design

Table 87. Internal reference voltage calibration values

Symbol Parameter Memory address

VREFIN_CAL Raw data acquired at temperature of 30 °C VDDA = 3.3 V 0x1FFF 7A2A - 0x1FFF 7A2B

5.3.28 DAC electrical characteristics

Table 88. DAC characteristics

Symbol Parameter Min Typ Max Unit Comments

VDDA Analog supply voltage 1.7(1) - 3.6 V -

VREF+ Reference supply voltage 1.7(1) - 3.6 V VREF+≤ VDDA

VSSA Ground 0 - 0 V -
RLOAD(2) Resistive load with buffer ON 5 - - kΩ -
When the buffer is OFF, the Minimum
Impedance output with buffer
RO(2) - - 15 kΩ resistive load between DAC_OUT and
OFF
VSS to have a 1% accuracy is 1.5 MΩ
Maximum capacitive load at DAC_OUT
CLOAD(2) Capacitive load - - 50 pF
pin (when the buffer is ON).

DAC_OUT Lower DAC_OUT voltage It gives the maximum output excursion of

0.2 - - V the DAC.
min(2) with buffer ON
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VREF+ = 3.6 V and
DAC_OUT Higher DAC_OUT voltage VDDA −
- - V (0x1C7) to (0xE38) at VREF+ = 1.7 V
max(2) with buffer ON 0.2
DAC_OUT Lower DAC_OUT voltage
- 0.5 - mV
min(2) with buffer OFF It gives the maximum output excursion of
DAC_OUT Higher DAC_OUT voltage VREF+ − the DAC.
- - V
max(2) with buffer OFF 1LSB
With no load, worst code (0x800) at
- 170 240 VREF+ = 3.6 V in terms of DC
DAC DC VREF current consumption on the inputs
IVREF+(4) consumption in quiescent µA
mode (Standby mode) With no load, worst code (0xF1C) at
- 50 75 VREF+ = 3.6 V in terms of DC
consumption on the inputs

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Table 88. DAC characteristics (continued)

Symbol Parameter Min Typ Max Unit Comments

With no load, middle code (0x800) on the

- 280 380 µA
DAC DC VDDA current inputs
IDDA(4) consumption in quiescent With no load, worst code (0xF1C) at
mode(3) - 475 625 µA VREF+ = 3.6 V in terms of DC
consumption on the inputs

Differential non linearity - - ±0.5 LSB Given for the DAC in 10-bit configuration.
DNL(4) Difference between two
consecutive code-1LSB)
- - ±2 LSB Given for the DAC in 12-bit configuration.
Integral non linearity - - ±1 LSB Given for the DAC in 10-bit configuration.
(difference between
measured value at Code i
INL(4)
and the value at Code i on a - - ±4 LSB Given for the DAC in 12-bit configuration.
line drawn between Code 0
and last Code 1023)
- - ±10 mV Given for the DAC in 12-bit configuration
Offset error
(difference between Given for the DAC in 10-bit at VREF+ =
- - ±3 LSB
Offset(4) measured value at Code 3.6 V
(0x800) and the ideal value =
Given for the DAC in 12-bit at VREF+ =
VREF+/2) - - ±12 LSB
3.6 V
Gain
Gain error - - ±0.5 % Given for the DAC in 12-bit configuration
error(4)
Settling time (full scale: for a
10-bit input code transition
(4) between the lowest and the CLOAD ≤ 50 pF,
tSETTLING - 3 6 µs
highest input codes when RLOAD ≥ 5 kΩ
DAC_OUT reaches final
value ±4LSB
Total Harmonic Distortion CLOAD ≤ 50 pF,
THD(4) - - - dB
Buffer ON RLOAD ≥ 5 kΩ

Max frequency for a correct

Update DAC_OUT change when CLOAD ≤ 50 pF,
- - 1 MS/s
rate(2) small variation in the input RLOAD ≥ 5 kΩ
code (from code i to i+1LSB)
Wakeup time from off state CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
tWAKEUP(4) (Setting the ENx bit in the - 6.5 10 µs input code between lowest and highest
DAC Control register) possible ones.
Power supply rejection ratio
PSRR+ (2) (to VDDA) (static DC - –67 –40 dB No RLOAD, CLOAD = 50 pF
measurement)
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).
2. Guaranteed by design.
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
4. Guaranteed based on test during characterization.

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Figure 58. 12-bit buffered/non-buffered DAC

Buffered/Non-buffered DAC

Buffer(1)
RL
12-bit DAC_OUTx
digital to
analog
converter

CL

ai17157V2

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.

5.3.29 FMC characteristics

Unless otherwise specified, the parameters given in tables 89 to 102 for the FMC interface
are derived from tests performed under the ambient temperature, fHCLK frequency, and VDD
supply voltage conditions summarized in Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5 VDD

Refer to Section 5.3.20 for more details on the input/output characteristics.

Asynchronous waveforms and timings

Figures 59 through 62 represent asynchronous waveforms, and tables 89 through 96
provide the corresponding timings. The results shown in these tables are obtained with the
following FMC configuration:
• AddressSetupTime = 0x1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
• BusTurnAroundDuration = 0x0
• Capacitive load CL = 30 pF

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Figure 59. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

tw(NE)

FMC_NE

tv(NOE_NE) t w(NOE) t h(NE_NOE)

FMC_NOE

FMC_NWE

tv(A_NE) t h(A_NOE)

FMC_A[25:0] Address
tv(BL_NE) t h(BL_NOE)

FMC_NBL[1:0]

t h(Data_NE)

t su(Data_NOE) th(Data_NOE)

t su(Data_NE)

FMC_D[15:0] Data

t v(NADV_NE)

tw(NADV)

FMC_NADV (1)

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)

MS32753V1

1. Mode 2/B, C, and D only. In Mode 1, FMC_NADV is not used.

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Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR - read timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 2THCLK − 0.5 2 THCLK+0.5

tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 1
tw(NOE) FMC_NOE low time 2THCLK 2THCLK+ 0.5
th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 -
tv(A_NE) FMC_NEx low to FMC_A valid - 2
th(A_NOE) Address hold time after FMC_NOE high 0 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 2
ns
th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 -
tsu(Data_NE) Data to FMC_NEx high setup time THCLK + 2.5 -
tsu(Data_NOE) Data to FMC_NOEx high setup time THCLK +2 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0
tw(NADV) FMC_NADV low time - THCLK +1
1. Based on test during characterization.

Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT

timings(1)
Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 7THCLK+0.5 7THCLK+1

tw(NOE) FMC_NWE low time 5THCLK − 1.5 5THCLK +2 ns

tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK+1.5 -
FMC_NEx hold time after FMC_NWAIT
th(NE_NWAIT) 4THCLK+1 -
invalid
1. Based on test during characterization.

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STM32F469xx Electrical characteristics

Figure 60. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

tw(NE)

FMC_NEx

FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)

FMC_NWE

tv(A_NE) th(A_NWE)

FMC_A[25:0] Address
tv(BL_NE) th(BL_NWE)

FMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)

FMC_D[15:0] Data
t v(NADV_NE)

tw(NADV)
FMC_NADV (1)

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)
MS32754V1

1. Mode 2/B, C, and D only. In Mode 1, FMC_NADV is not used.

Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)

Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 3THCLK 3THCLK+1
tv(NWE_NE) FMC_NEx low to FMC_NWE low THCLK − 0.5 THCLK+ 0.5
tw(NWE) FMC_NWE low time THCLK THCLK+ 0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time THCLK +1.5 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0
th(A_NWE) Address hold time after FMC_NWE high THCLK+0.5 -
ns
tv(BL_NE) FMC_NEx low to FMC_BL valid - 1.5
th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK+0.5 -
tv(Data_NE) Data to FMC_NEx low to Data valid - THCLK+ 2
th(Data_NWE) Data hold time after FMC_NWE high THCLK+0.5 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0.5
tw(NADV) FMC_NADV low time - THCLK+ 0.5
1. Based on test during characterization.

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Electrical characteristics STM32F469xx

Table 92. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT

timings(1)
Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8THCLK+1 8THCLK+2

tw(NWE) FMC_NWE low time 6THCLK − 1 6THCLK+2

ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK+1.5 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+1 -
1. Based on test during characterization.

Figure 61. Asynchronous multiplexed PSRAM/NOR read waveforms

tw(NE)

FMC_ NE
tv(NOE_NE) t h(NE_NOE)

FMC_NOE

t w(NOE)

FMC_NWE

tv(A_NE) th(A_NOE)

FMC_ A[25:16] Address

tv(BL_NE) th(BL_NOE)

FMC_ NBL[1:0] NBL

th(Data_NE)
tsu(Data_NE)
t v(A_NE) tsu(Data_NOE) th(Data_NOE)

FMC_ AD[15:0] Address Data

t v(NADV_NE) th(AD_NADV)
tw(NADV)

FMC_NADV

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)

MS32755V1

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Table 93. Asynchronous multiplexed PSRAM/NOR read timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 3THCLK − 1 3THCLK+0.5

tv(NOE_NE) FMC_NEx low to FMC_NOE low 2THCLK − 0.5 2THCLK
ttw(NOE) FMC_NOE low time THCLK − 1 THCLK+1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time 1 -
tv(A_NE) FMC_NEx low to FMC_A valid - 2
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 2
tw(NADV) FMC_NADV low time THCLK − 0.5 THCLK+0.5
FMC_AD(address) valid hold time after
th(AD_NADV) 0 - ns
FMC_NADV high)
th(A_NOE) Address hold time after FMC_NOE high THCLK − 0.5 -
th(BL_NOE) FMC_BL time after FMC_NOE high 0 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 2
tsu(Data_NE) Data to FMC_NEx high setup time THCLK+1.5 -
tsu(Data_NOE) Data to FMC_NOE high setup time THCLK+1 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
1. Based on test during characterization.

Table 94. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8THCLK+0.5 8THCLK+2

tw(NOE) FMC_NWE low time 5THCLK − 1 5THCLK +1.5 ns

tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK +1.5 -

th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+1 -
1. Based on test during characterization.

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Figure 62. Asynchronous multiplexed PSRAM/NOR write waveforms

tw(NE)

FMC_ NEx

FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)

FMC_NWE

tv(A_NE) th(A_NWE)

FMC_ A[25:16] Address

tv(BL_NE) th(BL_NWE)

FMC_ NBL[1:0] NBL

t v(A_NE) t v(Data_NADV) th(Data_NWE)

FMC_ AD[15:0] Address Data

t v(NADV_NE) th(AD_NADV)

tw(NADV)

FMC_NADV

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)
MS32756V1

Table 95. Asynchronous multiplexed PSRAM/NOR write timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 4THCLK 4THCLK+0.5

tv(NWE_NE) FMC_NEx low to FMC_NWE low THCLK − 1 THCLK+0.5
tw(NWE) FMC_NWE low time 2THCLK 2THCLK+0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time THCLK -
tv(A_NE) FMC_NEx low to FMC_A valid - 0
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0.5 1
tw(NADV) FMC_NADV low time THCLK − 0.5 THCLK+ 0.5
ns
FMC_AD (address) valid hold time
th(AD_NADV) THCLK − 2 -
after FMC_NADV high
th(A_NWE) Address hold time after FMC_NWE high THCLK -
th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK − 2 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 2
tv(Data_NADV) FMC_NADV high to Data valid - THCLK +1.5
th(Data_NWE) Data hold time after FMC_NWE high THCLK +0.5 -
1. Based on test during characterization.

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Table 96. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 9THCLK 9THCLK+0.5

tw(NWE) FMC_NWE low time 7THCLK 7THCLK+2

ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK+1.5 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK–1 -
1. Based on test during characterization.

Synchronous waveforms and timings

Figures 63 through 66 represent synchronous waveforms and Table 97 through Table 100
provide the corresponding timings. The results shown in these tables are obtained with the
following FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable;
• MemoryType = FMC_MemoryType_CRAM;
• WriteBurst = FMC_WriteBurst_Enable;
• CLKDivision = 1;
• DataLatency = 1 for NOR flash; DataLatency = 0 for PSRAM
• CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise
specified.
In all timing tables, the THCLK is the HCLK clock period:
• For 2.7 V≤ VDD≤ 3.6 V, maximum FMC_CLK = 90 MHz at CL = 30 pF (on FMC_CLK).
• For 1.71 V≤ VDD<1.9 V, maximum FMC_CLK = 60 MHz at CL = 10 pF (on FMC_CLK).

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Figure 63. Synchronous multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK

Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx
t d(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV
td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16]

td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE
td(CLKL-ADIV) th(CLKH-ADV)
t d(CLKL-ADV) tsu(ADV-CLKH) tsu(ADV-CLKH) th(CLKH-ADV)

FMC_AD[15:0] AD[15:0] D1 D2
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32757V1

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Table 97. Synchronous multiplexed NOR/PSRAM read timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period 2THCLK − 1 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 0
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 0
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) 0 -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - THCLK+0.5 ns
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high THCLK − 0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 0.5
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 5 -
th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 0 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 -
1. Based on test during characterization.

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Figure 64. Synchronous multiplexed PSRAM write timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK

Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV
td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16]

td(CLKL-NWEL) td(CLKH-NWEH)

FMC_NWE
td(CLKL-ADIV) td(CLKL-Data)
td(CLKL-ADV) td(CLKL-Data)

FMC_AD[15:0] AD[15:0] D1 D2

FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

td(CLKH-NBLH)

FMC_NBL

MS32758V1

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Table 98. Synchronous multiplexed PSRAM write timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period, VDD range= 2.7 to 3.6 V 2THCLK − 1 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0…2) - 1.5
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 0
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 0
ns
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high THCLK −0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 3
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 0 -
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK −0.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 -
1. Based on test during characterization.

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Figure 65. Synchronous non-multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK)

FMC_CLK
td(CLKL-NExL) td(CLKH-NExH)
Data latency = 0
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV
td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0]

td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)

FMC_D[15:0] D1 D2

tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) t h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32759V1

Table 99. Synchronous non-multiplexed NOR/PSRAM read timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period 2THCLK − 1 -

t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0…2) - 0.5
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 0
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK − 0.5 - ns
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - THCLK+2
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high THCLK − 0.5 -
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 5 -
th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 0 -
t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 -
1. Based on test during characterization.

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Figure 66. Synchronous non-multiplexed PSRAM write timings

tw(CLK) tw(CLK)

FMC_CLK

td(CLKL-NExL) td(CLKH-NExH)
Data latency = 0
FMC_NEx

td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV

td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0]

td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NWE

td(CLKL-Data) td(CLKL-Data)

FMC_D[15:0] D1 D2

FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH)
th(CLKH-NWAITV)
FMC_NBL

MS32760V1

Table 100. Synchronous non-multiplexed PSRAM write timings(1)

Symbol Parameter Min Max Unit

t(CLK) FMC_CLK period 2THCLK − 1 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0…2) - 0.5
t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 0
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) 0 -
ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 0
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high THCLK −0.5 -
td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 2.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 0 -
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK −0.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 -
1. Based on test during characterization.

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NAND controller waveforms and timings

Figures 67 through Figure 69 represent synchronous waveforms, and Table 101 and
Table 102 provide the corresponding timings. The results shown in this table are obtained
with the following FMC configuration:
• COM.FMC_SetupTime = 0x01;
• COM.FMC_WaitSetupTime = 0x03;
• COM.FMC_HoldSetupTime = 0x02;
• COM.FMC_HiZSetupTime = 0x01;
• ATT.FMC_SetupTime = 0x01;
• ATT.FMC_WaitSetupTime = 0x03;
• ATT.FMC_HoldSetupTime = 0x02;
• ATT.FMC_HiZSetupTime = 0x01;
• Bank = FMC_Bank_NAND;
• MemoryDataWidth = FMC_MemoryDataWidth_16b;
• ECC = FMC_ECC_Enable;
• ECCPageSize = FMC_ECCPageSize_512Bytes;
• TCLRSetupTime = 0;
• TARSetupTime = 0;
• Capacitive load CL = 30 pF.
In all timing tables, the THCLK is the HCLK clock period.

Figure 67. NAND controller waveforms for read access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) th(NOE-ALE)

FMC_NWE

tw(NOE)

FMC_NOE (NRE)

tsu(D-NOE) th(NOE-D)

FMC_D[y:0]

MSv73150V1

1. y = 7 or 15 depending on the NAND flash memory interface.

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Figure 68. NAND controller waveforms for write access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NWE) tw(NWE) th(NWE-ALE)

FMC_NWE

FMC_NOE (NRE)

td(D-NWE)

tv(NWE-D) th(NWE-D)

FMC_D[y:0]

MSv73151V1

1. y = 7 or 15 depending on the NAND flash memory interface.

Table 101. Switching characteristics for NAND Flash read cycles

Symbol Parameter Min Max Unit

tw(N0E) FMC_NOE low width 4THCLK − 0.5 4THCLK+0.5

tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 9 -
th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - ns
td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3THCLK − 0.5
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 3THCLK − 2 -

Table 102. Switching characteristics for NAND Flash write cycles

Symbol Parameter Min Max Unit

tw(NWE) FMC_NWE low width 4THCLK 4THCLK+1

tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 0 -
th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 3THCLK − 1 -
ns
td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5THCLK − 3 -
td(ALE-NWE) FMC_ALE valid before FMC_NWE low - 3THCLK −0.5
th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 3THCLK − 1 -

SDRAM waveforms and timings

• CL = 30 pF on data and address lines.
• CL = 10 pF on FMC_SDCLK unless otherwise specified.

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In all timing tables, the THCLK is the HCLK clock period.

• For 2.7 V ≤ VDD ≤ 3.6 V, maximum FMC_SDCLK = 90 MHz, at CL = 30 pF (on
FMC_SDCLK).
• For 1.71 V≤ VDD <1.9 V, maximum FMC_SDCLK = 75 MHz when CAS Latency = 3 and
60 MHz for CAS latency 1 or 2. CL = 10 pF (on FMC_SDCLK).

Figure 69. SDRAM read access waveforms (CL = 1)

FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR) th(SDCLKL_AddR)

FMC_A[12:0] Row n Col1 Col2 Coli Coln

th(SDCLKL_AddC)

td(SDCLKL_SNDE) th(SDCLKL_SNDE)

FMC_SDNE[1:0]
td(SDCLKL_NRAS) th(SDCLKL_NRAS)

FMC_SDNRAS

td(SDCLKL_NCAS) th(SDCLKL_NCAS)

FMC_SDNCAS

FMC_SDNWE
tsu(SDCLKH_Data) th(SDCLKH_Data)

FMC_D[31:0] Data1 Data2 Datai Datan

MS32751V2

Table 103. SDRAM read timings(1)

Symbol Parameter Min Max Unit

tw(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK+0.5

tsu(SDCLKH _Data) Data input setup time 2 -
th(SDCLKH_Data) Data input hold time 0 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL- SDNE) Chip select valid time - 0.5
ns
th(SDCLKL_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 0.5
th(SDCLKL_SDNRAS) SDNRAS hold time 0 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 0.5
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
1. Guaranteed based on test during characterization.

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Table 104. LPSDR SDRAM read timings(1)

Symbol Parameter Min Max Unit

tW(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK+0.5

tsu(SDCLKH_Data) Data input setup time 2.5 -

th(SDCLKH_Data) Data input hold time 0 -

td(SDCLKL_Add) Address valid time - 1
td(SDCLKL_SDNE) Chip select valid time - 1
ns
th(SDCLKL_SDNE) Chip select hold time 1 -
td(SDCLKL_SDNRAS SDNRAS valid time - 1
th(SDCLKL_SDNRAS) SDNRAS hold time 1 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 1
th(SDCLKL_SDNCAS) SDNCAS hold time 1 -
1. Guaranteed based on test during characterization.

Figure 70. SDRAM write access waveforms

FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR) th(SDCLKL_AddR)

FMC_A[12:0] Row n Col1 Col2 Coli Coln

th(SDCLKL_AddC)

td(SDCLKL_SNDE) th(SDCLKL_SNDE)

FMC_SDNE[1:0]
td(SDCLKL_NRAS) th(SDCLKL_NRAS)

FMC_SDNRAS

td(SDCLKL_NCAS) th(SDCLKL_NCAS)

FMC_SDNCAS
td(SDCLKL_NWE) th(SDCLKL_NWE)

FMC_SDNWE
td(SDCLKL_Data)

FMC_D[31:0] Data1 Data2 Datai Datan

td(SDCLKL_NBL) th(SDCLKL_Data)

FMC_NBL[3:0]
MS32752V2

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Table 105. SDRAM write timings(1)

Symbol Parameter Min Max Unit

tw(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK+0.5

td(SDCLKL _Data) Data output valid time - 2.5
th(SDCLKL _Data) Data output hold time 3.5 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL_SDNWE) SDNWE valid time - 1
th(SDCLKL_SDNWE) SDNWE hold time 0 -
td(SDCLKL_ SDNE) Chip select valid time - 0.5
ns
th(SDCLKL-_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 2
th(SDCLKL_SDNRAS) SDNRAS hold time 0 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 0.5
td(SDCLKL_SDNCAS) SDNCAS hold time 0 -
td(SDCLKL_NBL) NBL valid time - 0.5
th(SDCLKL_NBL) NBL output time 0 -
1. Guaranteed based on test during characterization.

Table 106. LPSDR SDRAM write timings(1)

Symbol Parameter Min Max Unit

tw(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK+0.5

td(SDCLKL _Data) Data output valid time - 5
th(SDCLKL _Data) Data output hold time 2 -
td(SDCLKL_Add) Address valid time - 2.8
td(SDCLKL-SDNWE) SDNWE valid time - 2
th(SDCLKL-SDNWE) SDNWE hold time 1 -
td(SDCLKL- SDNE) Chip select valid time - 1.5
ns
th(SDCLKL- SDNE) Chip select hold time 1 -
td(SDCLKL-SDNRAS) SDNRAS valid time - 1.5
th(SDCLKL-SDNRAS) SDNRAS hold time 1.5 -
td(SDCLKL-SDNCAS) SDNCAS valid time - 1.5
td(SDCLKL-SDNCAS) SDNCAS hold time 1.5 -
td(SDCLKL_NBL) NBL valid time - 1.5
th(SDCLKL-NBL) NBL output time 1.5 -
1. Guaranteed based on test during characterization.

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5.3.30 Quad-SPI interface characteristics

Unless otherwise specified, the parameters given in Table 107 and Table 108 for Quad-SPI
are derived from tests performed under the ambient temperature, fAHB frequency, and VDD
supply voltage conditions summarized in Table xx, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output alternate function
characteristics.

Table 107. Quad-SPI characteristics in SDR mode(1)

Symbol Parameter Test conditions Min Typ Max Unit

2.7 V ≤ VDD ≤ 3.6 V, CL = 20 pF - - 90

Fck
Quad-SPI clock frequency MHz
1/t(CK) 1.71 V ≤ VDD ≤ 3.6 V, CL = 15 pF - - 84

tw(CKH) Quad-SPI clock high time - t(CK)/2-1 - t(CK)/2

tw(CKL) Quad-SPI clock low time - t(CK)/2 - t(CK)/2+1

ts(IN) Data input set-up time - 0.5 - -

ns
th(IN) Data input hold time - 3 - -

tv(OUT) Data output valid time - - 3 4

th(OUT) Data output hold time - 2.5 - -

1. Guaranteed based on test during characterization.

Figure 71. Quad-SPI SDR timing diagram

tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK)

Clock
tv(OUT) th(OUT)

Data output D0 D1 D2

ts(IN) th(IN)

Data input D0 D1 D2
MSv36878V1

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Table 108. Quad-SPI characteristics in DDR mode(1)

Symbol Parameter Test conditions Min Typ Max Unit

2.7 V ≤ VDD ≤ 3.6 V,

- - 80
CL = 20 pF
Fck
Quad-SPI clock frequency MHz
1/t(CK) 1.71 V ≤ VDD ≤ 3.6 V,
- - 70
CL = 15 pF

tw(CKH) Quad-SPI clock high time - t(CK)/2-1 - t(CK)/2

tw(CKL) Quad-SPI clock low time - t(CK)/2 - t(CK)/2+1

tsr(IN) 2.7 V ≤ VDD ≤ 3.6 V 2 - -

Data input set-up time
tsf(IN) 1.71 V ≤ VDD ≤ 3.6 V 0.5 - -

thr(IN) 2.7 V ≤ VDD ≤ 3.6 V 3 - -

Data input hold time
thf(IN) 1.71 V ≤ VDD ≤ 3.6 V 4.5 - - ns
DHHC=0 - 8 10.5
tvr(OUT)
Data output valid time DHHC=1
tvf(OUT) - Thclk/2+2 Thclk/2+2.5
Pres=1,2…
DHHC=0 7 - -
th(OUT)
Data output hold time DHHC=1
tf(OUT) Thclk/2+0.5 - -
Pres=1,2…
1. Guaranteed based on test during characterization.

Figure 72. Quad-SPI DDR timing diagram

tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK)

Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)

Data output D0 D1 D2 D3 D4 D5

tsf(IN) thf(IN) tsr(IN) thr(IN)

Data input D0 D1 D2 D3 D4 D5
MSv36879V1

5.3.31 Camera interface (DCMI) timing specifications

Unless otherwise specified, the parameters given in Table 109 for DCMI are derived
from tests performed under the ambient temperature, fHCLK frequency, and VDD supply
voltage summarized in Table 17, with the following configuration:
• DCMI_PIXCLK polarity: falling
• DCMI_VSYNC and DCMI_HSYNC polarity: high
• Data formats: 14 bits
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD

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Table 109. DCMI characteristics(1)

Symbol Parameter Min Max Unit

- Frequency ratio DCMI_PIXCLK/fHCLK - 0.4 -

DCMI_PIXCLK Pixel clock input - 54 MHz
DPixel Pixel clock input duty cycle 30 70 %
tsu(DATA) Data input setup time 4 -
th(DATA) Data input hold time 1 -
tsu(HSYNC) ns
DCMI_HSYNC/DCMI_VSYNC input setup time 3.5 -
tsu(VSYNC)
th(HSYNC)
DCMI_HSYNC/DCMI_VSYNC input hold time 0 -
th(VSYNC)
1. 1.Guaranteed based on test during characterization.

Figure 73. DCMI timing diagram

1/DCMI_PIXCLK

DCMI_PIXCLK

tsu(HSYNC) th(HSYNC)

DCMI_HSYNC

tsu(VSYNC) th(HSYNC)

DCMI_VSYNC
tsu(DATA) th(DATA)

DATA[0:13]

MS32414V2

5.3.32 LCD-TFT controller (LTDC) characteristics

Unless otherwise specified, the parameters given in Table 110 for LCD-TFT are derived
from tests performed under the ambient temperature, fHCLK frequency, and VDD supply
voltage summarized in Table 17, with the following configuration:
• LCD_CLK polarity: high
• LCD_DE polarity: low
• LCD_VSYNC and LCD_HSYNC polarity: high
• Pixel formats: 24 bits
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load CL = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD

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Table 110. LTDC characteristics(1)

Symbol Parameter Min Max Unit

fCLK LTDC clock output frequency - 83 MHz

DCLK LTDC clock output duty cycle 45 55 %
tw(CLKH)
Clock high time, low time tw(CLK) / 2 - 0.5 tw(CLK) / 2 + 0.5
tw(CLKL)
tv(DATA) Data output valid time - 1.5
th(DATA) Data output hold time 0 -
tv(HSYNC)
ns
tv(VSYNC) HSYNC/VSYNC/DE output valid time - 0.5
tv(DE)
th(HSYNC)
th(VSYNC) HSYNC/VSYNC/DE output hold time 0 -
th(DE)
1. Based on test during characterization.

Figure 74. LCD-TFT horizontal timing diagram

tCLK

LCD_CLK

LCD_VSYNC

tv(HSYNC) tv(HSYNC)

LCD_HSYNC
tv(DE) th(DE)

LCD_DE
tv(DATA)
LCD_R[0:7]
LCD_G[0:7] Pixel Pixel Pixel
1 2 N
LCD_B[0:7]
th(DATA)

HSYNC Horizontal Active width Horizontal

width back porch back porch

One line
MS32749V1

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Figure 75. LCD-TFT vertical timing diagram

tCLK

LCD_CLK

tv(VSYNC) tv(VSYNC)

LCD_VSYNC

LCD_R[0:7]
LCD_G[0:7] M lines data
LCD_B[0:7]

VSYNC Vertical Active width Vertical

width back porch back porch

One frame
MS32750V1

5.3.33 SD/SDIO MMC card host interface (SDIO) characteristics

Unless otherwise specified, the parameters given in Table 111 for the SDIO/MMC interface
are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD
supply voltage conditions summarized in Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output characteristics.

Figure 76. SDIO high-speed mode

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Figure 77. SD default mode

CK
tOVD tOHD
D, CMD
(output)

ai14888

Table 111. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V(1)
Symbol Parameter Conditions Min Typ Max Unit

fPP Clock frequency in data transfer mode - 0 - 50 MHz

- SDIO_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time 9.5 10.5 -
fpp =50 MHz ns
tW(CKH) Clock high time 8.5 9.5 -

CMD, D inputs (referenced to CK) in MMC and SD HS mode

tISU Input setup time HS 2.0 - -

fpp =50 MHz ns
tIH Input hold time HS 2.0 - -

CMD, D outputs (referenced to CK) in MMC and SD HS mode

tOV Output valid time HS - 13 13.5

fpp =50 MHz ns
tOH Output hold time HS 12.5 - -

CMD, D inputs (referenced to CK) in SD default mode

tISUD Input setup time SD 2.0 - -

fpp =25 MHz ns
tIHD Input hold time SD 2.5 - -

CMD, D outputs (referenced to CK) in SD default mode

tOVD Output valid default time SD - 1.5 2.0

fpp =25 MHz ns
tOHD Output hold default time SD 1.0 - -

1. Guaranteed based on test during characterization.

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Table 112. Dynamic characteristics: SD / MMC characteristics, VDD = 1.71 to 1.9 V(1)(2)
Symbol Parameter Conditions Min Typ Max Unit

fPP Clock frequency in data transfer mode - 0 - 50 MHz

- SDIO_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time 9.5 10.5 -
fpp =50 MHz ns
tW(CKH) Clock high time 8.5 9.5 -

CMD, D inputs (referenced to CK) in eMMC mode

tISU Input setup time HS 0.5 - -

fpp =50 MHz ns
tIH Input hold time HS 3.5 - -

CMD, D outputs (referenced to CK) in eMMC mode

tOV Output valid time HS - 13.5 14.5

fpp =50 MHz ns
tOH Output hold time HS 13.0 - -
1. Guaranteed based on test during characterization.
2. Cload = 20 pF.

5.3.34 RTC characteristics

Table 113. RTC characteristics

Symbol Parameter Conditions Min Max

- fPCLK1/RTCCLK frequency ratio Any read/write operation from/to an RTC register 4 -

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6 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

6.1 Device marking

Refer to technical note “Reference device marking schematics for STM32 microcontrollers
and microprocessors” (TN1433 ) available on www.st.com, for the location of pin 1 / ball A1
as well as the location and orientation of the marking areas versus pin 1 / ball A1.
Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are
not yet qualified and therefore not approved for use in production. ST is not responsible for
any consequences resulting from such use. In no event will ST be liable for the customer
using any of these engineering samples in production. ST’s Quality department must be
contacted prior to any decision to use these engineering samples to run a qualification
activity.
A WLCSP simplified marking example (if any) is provided in the corresponding package
information subsection.

6.2 LQFP100 package information (1L)

This LQFP is 100 lead, 14 x 14 mm low-profile quad flat package.
Note: See list of notes in the notes section.

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Figure 78. LQFP100 - Outline(15)

ș2 ș
(2)
R1

H
R2

B
B-
N
O
(6)

TI
C
SE
D1/4 B GAUGE PLANE

S
E1/4
B ș
4x N/4 TIPS
ș L
4x (L1)
aaa C A-B D
bbb H A-B D (1) (11)

BOTTOM VIEW SECTION A-A

(N-4) x e (13)

C
A (9) (11)
0.05
ccc C b WITH PLATING
A2 A1 b aaa C A-BD
(12)

SIDE VIEW

D (4)
(11) c
(2) (5) D1 c1 (11)

D (3)
(10) (4)
N

b1 BASE METAL
1 (11)
2
3 E1/4 SECTION B-B

D1/4 (6) (2)

A B
(5)

E1 E

SECTION A-A

A A

TOP VIEW 1L_LQFP100_ME_V3

Table 114. LQFP100 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

A - 1.50 1.60 - 0.0590 0.0630

A1(12) 0.05 - 0.15 0.0019 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570

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Table 114. LQFP100 - Mechanical data (continued)

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

b(9)(11) 0.17 0.22 0.27 0.0067 0.0087 0.0106

b1(11) 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
(11)
c1 0.09 - 0.16 0.0035 - 0.0063
D(4) 16.00 BSC 0.6299 BSC
(2)(5)
D1 14.00 BSC 0.5512 BSC
(4)
E 16.00 BSC 0.6299 BSC
E1(2)(5) 14.00 BSC 0.5512 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.177 0.0236 0.0295
(1)(11)
L1 1.00 - 0.0394 -
(13)
N 100
θ 0° 3.5° 7° 0° 3.5° 7°

θ1 0° - - 0° - -

θ2 10° 12° 14° 10° 12° 14°

θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
(1)
aaa 0.20 0.0079
bbb(1) 0.20 0.0079
(1)
ccc 0.08 0.0031
ddd(1) 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 79. LQFP100 - Footprint example

75 51

76 50
0.5

0.3

16.7 14.3

100 26

1.2
1 25

12.3

16.7

1L_LQFP100_FP_V1

1. Dimensions are expressed in millimeters.

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6.3 LQFP144 package information (1A)

This LQFP is a 144-pin, 20 x 20 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 80. LQFP144 - Outline(15)

BOTTOM VIEW

2 1
(2)
R1

H
R2

B
B-
N
O
TI
C
SE
(6) B GAUGE PLANE

0.25
D 1/4
S
B
L
3
E 1/4 (L1)
(1) (11)
4x N/4 TIPS
aaa C A-B D SECTION A-A
bbb H A-B D 4x

(N-4)x e
C
A
0.05 (12) ddd C A-B D
A2 A1 b ccc C

D (4)
D1 (2) (5)
(10) (3) D (9) (11)
N (4)
b WITH PLATING

1
2
3 E 1/4

(11) (11)
c c1
(6)
D 1/4 (2)
(3) A B (3) (5)

E1 E b1 BASE METAL
(11)

SECTION B-B

A A
(Section A-A)

TOP VIEW
1A_LQFP144_ME_V2

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Table 115. LQFP144 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 22.00 BSC 0.8661 BSC
(2)(5)
D1 20.00 BSC 0.7874 BSC
E(4) 22.00 BSC 0.8661 BSC
E1(2)(5) 20.00 BSC 0.7874 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 144
θ 0° 3.5° 7° 0° 3.5° 7°

θ1 0° - - 0° - -

θ2 10° 12° 14° 10° 12° 14°

θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa 0.20 0.0079
bbb 0.20 0.0079
ccc 0.08 0.0031
ddd 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

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Figure 81. LQFP144 - Footprint example

108 73
1.35

109 0.35 72

0.50

19.90 17.85
22.60

144 37

1 36

19.90
22.60
1A_LQFP144_FP

1. Dimensions are expressed in millimeters.

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6.4 WLCSP168 package information

Figure 82. WLCSP168 - 168-ball, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip
scale
package outline

A1 ball location
e1 bbb Z
F

Detail A

e2

A3
e A2
Bottom view
Bump side A
Side view
X
Y
D

Bump A3

eee Z A1
E
b
ccc Z XY Seating Z
A1 orientation plane
ddd Z
reference
Detail A
Rotated 90°
aaa
Top view
Wafer back side (4X)

A02S_ME_V2

1. Drawing is not to scale.

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Table 116. WLCSP168 - 168-ball, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip
scale
package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.525 0.555 0.585 0.0207 0.0219 0.0230

A1 - 0.170 - - 0.0067 -
A2 - 0.380 - - 0.0150 -
(2)
A3 - 0.025 - - 0.0010 -
(3)
b 0.220 0.250 0.280 0.0087 0.0098 0.0110
D 4.856 4.891 4.926 0.1912 0.1926 0.1939
E 5.657 5.692 5.727 0.2227 0.2241 0.2255
e - 0.400 - - 0.0157 -
e1 - 4.400 - - 0.1732 -
e2 - 5.200 - - 0.2047 -
F - 0.2455 - - 0.0097 -
G - 0.246 - - 0.0097 -
aaa - - 0.100 - - 0.0039
bbb - - 0.100 - - 0.0039
ccc - - 0.100 - - 0.0039
ddd - - 0.050 - - 0.0020
eee - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating.
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

Figure 83. WLCSP168 - 168-ball, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip
scale
package recommended footprint

Dpad

Dsm MS18965V2

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Table 117. WLCSP168 recommended PCB design rules

Dimension Recommended values

Pitch 0.4 mm
260 µm max. (circular)
Dpad
220 µm recommended
Dsm 300 µm min. (for 260 µm diameter pad)
PCB pad design Non-solder mask defined via underbump allowed

6.5 UFBGA169 package information (A0YV)

This UFBGA is a 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.

Figure 84. UFBGA169 - Outline

Z Seating plane
A2 A4
ddd Z
A
A3 A1
b
SIDE VIEW A1 ball A1 ball
identifier index area X
E
E1
e F

A
F

D1 D

e
Y
N
13 1

BOTTOM VIEW Øb (169 balls) TOP VIEW

Ø eee M Z X Y
Ø fff M Z
A0YV_ME_V2

1. Drawing is not to scale.

Table 118. UFBGA169 - Mechanical data

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

A 0.460 0.530 0.600 0.0181 0.0209 0.0236

A1 0.050 0.080 0.110 0.0020 0.0031 0.0043

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Table 118. UFBGA169 - Mechanical data (continued)

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

A2 0.400 0.450 0.500 0.0157 0.0177 0.0197

A3 - 0.130 - - 0.0051 -
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
b 0.230 0.280 0.330 0.0091 0.0110 0.0130
D 6.950 7.000 7.050 0.2736 0.2756 0.2776
D1 5.950 6.000 6.050 0.2343 0.2362 0.2382
E 6.950 7.000 7.050 0.2736 0.2756 0.2776
E1 5.950 6.000 6.050 0.2343 0.2362 0.2382
e - 0.500 - - 0.0197 -
F 0.450 0.500 0.550 0.0177 0.0197 0.0217
ddd - - 0.100 - - 0.0039
eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 85. UFBGA169 - Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

Table 119. UFBGA169 - Example of PCB design rules (0.5 mm pitch BGA)
Dimension Values

Pitch 0.5 mm
Dpad 0.27 mm
0.35 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Solder paste 0.27 mm aperture diameter.

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Note: Non-solder mask defined (NSMD) pads are recommended.

Note: 4 to 6 mils solder paste screen printing process.

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6.6 LQFP176 package information (1T)

This LQFP is a 176-pin, 24 x 24 mm, 0.5 mm pitch, low profile quad flat package.
Note: See list of notes in the notes section.

Figure 86. LQFP176 - Outline(15)

ș2 ș1

(2) R1

H R2

B(See SECTION B-B)

(6) GAUGE PLANE
0.25
D1/4
S
B ș
L
E1/4 ș
4x N/4 TIPS 4x (L1)
(1) (11)
bbb H A-B D
aaa C A-B D

BOTTOM VIEW SECTION A-A

A2 0.05
(N-4) x e 
C
A
A1 (12) ddd C A-BD ccc C
b

SIDE VIEW

D (4)
(2) (5) D1
D  (9) (11)
(10) N
(4) b WITH PLATING

E1/4

(11) c c1 (11)
D1/4 (6) (5)

A B (2)
E1 E b1 BASE METAL
(11)

SECTION A-A
A A
SECTION B-B

TOP VIEW 1T_LQFP176_ME_V2

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Table 120. LQFP176 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1(12) 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
(9)(11)
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
(11)
b1 0.170 0.200 0.230 0.0067 0.0079 0.0091
c(11) 0.090 - 0.200 0.0035 - 0.0079
(11)
c1 0.090 - 0.160 0.0035 - 0.063
(4)
D 26.000 1.0236
(2)(5)
D1 24.000 0.9449
E(4) 26.000 0.0197
(2)(5)
E1 24.000 0.9449
e 0.500 0.1970
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1(1)(11) 1 0.0394 REF
N(13) 176
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.080 - - 0.0031 - -
R2 0.080 - 0.200 0.0031 - 0.0079
S 0.200 - - 0.0079 - -
(1)
aaa 0.200 0.0079
(1)
bbb 0.200 0.0079
(1)
ccc 0.080 0.0031
ddd(1) 0.080 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

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Figure 87. LQFP176 - Footprint example

1.2
176 133
1 0.5 132

0.3
26.7

21.8

44 89
45 88
1.2

21.8

26.7

1T_FP_V1

1. Dimensions are expressed in millimeters.

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6.7 UFBGA(176+25) package information (A0E7)

This UFBGA is a 176+25-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array
package

Figure 88. UFBGA(176+25) - Outline

Seating plane
C A4
ddd C

A
A2 A3 b A1
A1 ball A
A1 ball index E
identifier area
E1
e F
A
F

D1 D

e
B
R
15 1
Øb (176 + 25 balls)
BOTTOM VIEW TOP VIEW
Ø eee M C A B
Ø fff M C

A0E7_ME_V10

1. Drawing is not to scale.

Table 121. UFBGA(176+25) - Mechanical data

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

A - - 0.600 - - 0.0236
A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 - 0.450 - - 0.0177 -
A3 - 0.130 - - 0.0051 -
A4 - 0.320 - - 0.0126 -
b 0.240 0.290 0.340 0.0094 0.0114 0.0134
D 9.850 10.000 10.150 0.3878 0.3937 0.3996
D1 - 9.100 - - 0.3583 -
E 9.850 10.000 10.150 0.3878 0.3937 0.3996
E1 - 9.100 - - 0.3583 -
e - 0.650 - - 0.0256 -
F - 0.450 - - 0.0177 -
ddd - - 0.080 - - 0.0031

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Table 121. UFBGA(176+25) - Mechanical data (continued)

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

eee - - 0.150 - - 0.0059

fff - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 89. UFBGA(176+25) - Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

Table 122. UFBGA(176+25) - Example of PCB design rules (0.65 mm pitch BGA)
Dimension Values

Pitch 0.65 mm
Dpad 0.300 mm
0.400 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.300 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm

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STM32F469xx Package information

6.8 TFBGA216 package information (A0L2)

This TFBGA is a 216-ball, 13 x 13 mm, 0.8 mm pitch, fine pitch ball grid array package.

Figure 90. TFBGA216 - Outline

Z Seating plane

ddd Z

A2
A1 A
D1 A1 ball A1 ball X
identifier index area D
e F

A
G

E1 E

e
Y
R
15 1
BOTTOM VIEW Øb (216 balls) TOP VIEW
Ø eee M Z Y X
Ø fff M Z
A0L2_ME_V3

1. Drawing is not to scale.

2. • The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized
markings, or other feature of package body or integral heat slug.
• A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optional

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Table 123. TFBGA216 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.200 - - 0.0472
(2)
A1 0.150 - - 0.0059 - -
A2 - 0.760 - - 0.0299 -
(3)
b 0.350 0.400 0.450 0.0138 0.0157 0.0177
D 12.850 13.000 13.150 0.5059 0.5118 0.5177
D1 - 11.200 - - 0.4409 -
E 12.850 13.000 13.150 0.5059 0.5118 0.5177
E1 - 11.200 - - 0.4409 -
e - 0.800 - - 0.0315 -
F - 0.900 - - 0.0354 -
G - 0.900 - - 0.0354 -
ddd - - 0.100 - - 0.0039
(4)
eee - - 0.150 - - 0.0059
(5)
fff - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. • The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized
markings, or other feature of package body or integral heat slug.
• A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optional.
3. Initial ball equal 0.350 mm.
4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true
position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone.
5. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each
tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball
must lie simultaneously in both tolerance zones.

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STM32F469xx Package information

Figure 91. TFBGA216 - Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

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Package information STM32F469xx

Table 124. TFBGA216 - Example of PCB design rules (0.8 mm pitch)

Dimension Values

Pitch 0.8 mm
Dpad 0.400 mm
0.470 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.400 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.120 mm

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STM32F469xx Package information

6.9 LQFP208 package information

This LQFP is a 208-pin, 28 x 28 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 92. LQFP208 - Outline(15)

BOTTOM VIEW

2 1
(2)
R1
R2

B
H

B-
N
O
TI
C
SE
B GAUGE PLANE

0.25
D 1/4 (6)
S
B
L
3
(L1) (1) (11)

E 1/4 SECTION A-A

4x N/4 TIPS
aaa C A-B D bbb H A-B D 4x

(N – 4)x e (13)
C
A
A2
b ddd C A-B D
0.05 A1(12) ccc C
D (4)
(2) (5) D1
D (3)
(10) N
(4) (9) (11)
b WITH
1 PLATING
2
3
E 1/4
(11) (11)
c c1

D 1/4 (6)
b1 BASE METAL
(3) A B (3) (11)

E1 E SECTION B-B
(2)
(5)

A A
(Section A-A)

TOP VIEW UH_LQFP208_ME_V2

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Package information STM32F469xx

Table 125. LQFP208 - Mechanical data

millimeters inches(15)
Symbol
Min Typ Max Min Typ Max

A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0091
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 30.00 BSC 1.1732 BSC
(2)(5)
D1 28.00 BSC 1.0945 BSC
E(4) 30.00 BSC 1.1732 BSC
E1(2)(5) 28.00 BSC 1.0945 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 208
θ 0° 3.5° 7° 0° 3.5° 7°

θ1 0° - - 0° - -

θ2 10° 12° 14° 10° 12° 14°

θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1)(7) 0.20 0.0079
(1)(7)
bbb 0.20 0.0079
ccc(1)(7) 0.08 0.0031
(1)(7)
ddd 0.08 0.0031

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STM32F469xx Package information

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 93. LQFP208 - footprint example

208 157

1 156
0.50 1.25
0.30
28.3
30.7

52 105

53 104 1.2
25.8
30.7
UH_LQFP208_FP_V3

1. Dimensions are expressed in millimeters.

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Package information STM32F469xx

6.10 Thermal characteristics

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
where:
• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = ∑(VOL × IOL) + ∑((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.

Table 126. Package thermal characteristics

Symbol Parameter Value Unit

Thermal resistance junction-ambient

43
LQFP100
Thermal resistance junction-ambient
40
LQFP144
Thermal resistance junction-ambient
31
WLCSP168
Thermal resistance junction-ambient
38
LQFP176 - 24 × 24 mm / 0.5 mm pitch
ΘJA °C/W
Thermal resistance junction-ambient
19
LQFP208 - 28 × 28 mm / 0.5 mm pitch
Thermal resistance junction-ambient
52
UFBGA169 - 7 × 7mm / 0.5 mm pitch
Thermal resistance junction-ambient
39
UFBGA176 - 10 × 10 mm / 0.5 mm pitch
Thermal resistance junction-ambient
29
TFBGA216 - 13 × 13 mm / 0.8 mm pitch

Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.

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STM32F469xx Part numbering

7 Part numbering

Example: STM32 F 469 V I T 6 xxx

Device family
STM32 = Arm®-based 32-bit microcontroller

Product type
F = general-purpose
Device subfamily
469= STM32F469xx, USB OTG FS/HS, camera interface, Ethernet,
LCD-TFT, DSI Host, Quad-SPI, Chrom-ART graphical accelerator.

Pin count
V = 100 pins
Z = 144 pins
A = 168 and 169 pins
I = 176 pins
B = 208 pins
N = 216 pins

Flash memory size

E = 512 Kbytes of Flash memory
G = 1024 Kbytes of Flash memory
I = 2048 Kbytes of Flash memory

Package
T = LQFP
H = BGA
Y = WLCSP

Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C

Options
xxx = programmed parts
TR = tape and reel

For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, contact your nearest ST sales office.

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Important security notice STM32F469xx

8 Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.

220/225 DS11189 Rev 8

STM32F469xx Recommendations when using internal reset OFF

Appendix A Recommendations when using internal reset

OFF

When the internal reset is OFF, the following integrated features are no longer supported:
• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
• The brownout reset (BOR) circuitry must be disabled.
• The embedded programmable voltage detector (PVD) is disabled.
• VBAT functionality is no more available and VBAT pin should be connected to VDD.
• The over-drive mode is not supported.

A.1 Operating conditions

Table 127. Limitations depending on the operating power supply range
Operating Maximum Flash Maximum
Possible
power ADC memory access Flash memory
I/O operation Flash memory
supply operation frequency with no access frequency
operations
range wait states (fFlashmax) with wait states (1)(2)

Conversion 168 MHz with 8 wait 8-bit erase and

VDD =1.7 to – No I/O
time up to 20 MHz(4) states and over-drive program
2.1 V(3) compensation
1.2 Msps OFF operations only
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the
execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state
program execution.
3. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 2.19.1: Internal
reset ON).
4. Prefetch is not available. Refer to AN3430, available on www.st.com, for details on how to adjust performance and power.

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Revision history STM32F469xx

Revision history

Table 128. Document revision history

Date Revision Changes

01-Sep-2015 1 Initial release.

Updated Table 4: Regulator ON/OFF and internal reset ON/OFF
availability and Table 54: EMI characteristics.
Updated Figure 35: PLL output clock waveforms in center spread
13-Oct-2015 2
mode and Figure 36: PLL output clock waveforms in down spread
mode.
Updated title of Section 6.8: TFBGA216 package information.
Updated cover page with introduction of LQFP100 and LQFP144
packages.
Updated Section 1: Description and Section 1.1: Compatibility
throughout the family.
Updated Figure 1: Incompatible board design for LQFP176 package
and its footnote.
Updated Table 1: Device summary, Table 2: STM32F469xx features
and peripheral counts, Table 4: Regulator ON/OFF and internal reset
ON/OFF availability, Table 10: STM32F469xx pin and ball definitions,
Table 11: FMC pin definition, Table 12: Alternate function, Table 17:
General operating conditions, Table 55: ESD absolute maximum
ratings, Table 76: ADC characteristics, Table 125: Package thermal
08-Mar-2016 3 characteristics and Table 125: Ordering information scheme.
Removed former Table 73: Ethernet DC electrical characteristics.
Added Figure 13: STM32F46x LQFP100 pinout and Figure 14:
STM32F46x LQFP144 pinout.
Updated Figure 17: STM32F46x UFBGA176 ballout, Figure 18:
STM32F46x LQFP176 pinout and Figure 33: ACCHSI vs. temperature.
Added Section 6.2: LQFP100 package information and Section 6.3:
LQFP144 package information.
Replaced former footnote 7 of Table 10: STM32F469xx pin and ball
definitions with footnote 2.
Added footnote 3 to Table 14: Voltage characteristics.
Updated footnote 1 of Figure 56 and footnote 1 of Figure 57.
Updated Table 12: Alternate function.
Corrected maximum characterized wakeup timing values for Stop
mode in Table 34: Low-power mode wakeup timings.
Updated Figure 14: STM32F46x LQFP144 pinout.
02-Mar-2017 4 Updated Device marking for LQFP100, Device marking for
UFBGA169, Device marking for LQFP176, Device marking for
LQFP176 and Device marking for LQFP176.
Updated footnotes of figures 82, 85, 89, 92, 98 and 100 in Section 6:
Package information.

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STM32F469xx Revision history

Table 128. Document revision history (continued)

Date Revision Changes

Updated Video Mode interfaces features, Section 2.14: Nested

vectored interrupt controller (NVIC) and Section 2.18: Power supply
schemes.
04-May-2018 5 Updated Table 17: General operating conditions, Table 57: I/O current
injection susceptibility and Table 64: SPI dynamic characteristics.
Updated Figure 49: USB OTG full speed timings: definition of data
signal rise and fall time.
Updated Table 2: STM32F469xx features and peripheral counts, Table
109: LTDC characteristics and Table 119: UFBGA(176+25) -
Mechanical data.
Updated footnote 2 of Figure 41: Recommended NRST pin protection
18-Jan-2021 6 and footnote 1 of Table 39: HSI oscillator characteristics.
Updated Section 6.3: LQFP144 package information.
Updated Figure 93: UFBGA(176+25) - Outline and Figure 94:
UFBGA(176+25) - Recommended footprint.
Minor text edits across the whole document.
Updated Table 2: STM32F469xx features and peripheral counts.
05-May-2021 7
Updated Section 1: Description.

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Revision history STM32F469xx

Table 128. Document revision history (continued)

Date Revision Changes

Added the following sections:

Section 8: Important security notice
Section 6.1: Device marking

Removed the following sections:

Device marking obsolete content.

Updated the following:

Section 6.2: LQFP100 package information (1L)
Section 6.3: LQFP144 package information (1A)
Section 6.4: WLCSP168 package information
Section 6.5: UFBGA169 package information (A0YV)
Section 6.7: UFBGA(176+25) package information (A0E7)
Section 6.8: TFBGA216 package information (A0L2)
Section 6.9: LQFP208 package information
Section 2.26: Universal synchronous/asynchronous receiver
transmitters (USART)
Table 2: STM32F469xx features and peripheral counts
Table 39: HSI oscillator characteristics
07-Nov-2023 8
Table 22: Reset and power control block characteristics
Section 2.4: Embedded flash memory
Section : Features
Section Table 10.: STM32F469xx pin and ball definitions
Section 5.3.20: I/O port characteristics
Section 2.38: True random number generator (RNG)
Section 5.3.7: Supply current characteristics (I/O static current
consumption, and I/O dynamic current consumption).
Figure 40: I/O AC characteristics definition.
Figure 55: Typical connection diagram using the ADC with FT/TT pins
featuring analog switch funcion
Table 54: EMI characteristics for fHSE=8 MHz and fCPU=168 MHz
Table 55: EMI characteristics for fHSE=8 MHz and fCPU=180 MHz
Figure 42: SPI timing diagram - slave mode and CPHA = 0
Figure 43: SPI timing diagram - slave mode and CPHA = 1
Figure 44: SPI timing diagram - master mode
Figure 67: NAND controller waveforms for read access
Figure 68: NAND controller waveforms for write access
Applied minor terminology changes.

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STM32F469xx

IMPORTANT NOTICE – READ CAREFULLY

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© 2023 STMicroelectronics – All rights reserved

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