Instruction Pipeline
Instruction Pipeline: Detailed Explanation
Instruction pipeline is a technique used in modern computer architecture where multiple instruction phases
are overlapped to improve instruction throughput (the number of instructions completed per unit of time).
Instead of completing one instruction before starting the next, the CPU starts a new instruction before the
previous one finishes, dividing the work into separate stages, much like an assembly line in a factory.
Basic Concept
An instruction cycle (fetch, decode, execute, store result) is broken down into stages:
| Stage | Name | Task |
|------|--------------------------|------------------------------------|
| IF | Instruction Fetch | Fetch instruction from memory |
| ID | Instruction Decode | Decode instruction & read operands |
| EX | Execute | Perform operations (ALU) |
| MEM | Memory Access (if needed) | Access memory (for load/store) |
| WB | Write Back | Write result back to register |
In a pipeline, while one instruction is being decoded, another can be fetched, another can be executed, and
so on.
Example
Suppose you have 5 stages and 5 instructions:
Clock Cycle | IF | ID | EX | MEM | WB
------------|-----|-----|-----|-----|----
1 | I1 | | | |
2 | I2 | I1 | | |
Instruction Pipeline
3 | I3 | I2 | I1 | |
4 | I4 | I3 | I2 | I1 |
5 | I5 | I4 | I3 | I2 | I1
6 | | I5 | I4 | I3 | I2
7 | | | I5 | I4 | I3
8 | | | | I5 | I4
9 | | | | | I5
Key Points:
- Without pipelining: 5 instructions would take 5 × 5 = 25 cycles.
- With pipelining: After 5 initial cycles to fill the pipeline, one instruction completes every cycle - total = 9
cycles.
- Performance Gain = almost 5 times faster (ideal case).
Advantages of Pipelining
- Increased throughput
- Better resource utilization
- Higher instruction execution speed
Difficulties in Instruction Pipelining (Pipeline Hazards)
1. Structural Hazards
Occurs when hardware resources are insufficient to support all the concurrent operations.
Example: Only one memory unit available, but two stages (Instruction Fetch and Memory Access) want to
access it at the same time.
2. Data Hazards
Occurs when an instruction depends on the result of a previous instruction still in the pipeline.
Types:
Instruction Pipeline
- RAW (Read After Write)
- WAR (Write After Read)
- WAW (Write After Write)
Example:
I1: R1 = R2 + R3
I2: R4 = R1 + R5
Solution: Stalling, Forwarding/Bypassing
3. Control Hazards (Branch Hazards)
Occurs when the pipeline makes wrong decisions on branch instructions (e.g., jumps, if-else).
Solution: Branch Prediction, Delayed Branching
Pipeline Performance
Ideal Speedup = Number of stages
Actual Speedup = Less due to hazards and stalls.
Speedup = (Time without pipelining) / (Time with pipelining)
Efficiency reduces if there are too many hazards.
Quick Diagram
IF -> ID -> EX -> MEM -> WB
Each arrow represents the flow of an instruction through the CPU stages.
Summary
Instruction Pipeline
- Instruction pipelining improves CPU performance by overlapping instruction stages.
- It faces difficulties due to structural, data, and control hazards.
- Techniques like stalling, forwarding, and branch prediction help minimize pipeline inefficiencies.
- Ideal speedup is rarely achieved due to real-world complications.
