EXPERIMENT - 01

REALISATION OF BASIC GATES

Aim: To realise and simulate all logic gates using Verilog.
Apparatus:
• PC installed with Vivado(IDE)
• Keyboard
• Mouse
• Monitor

Theory:
There are seven basic logic gates: AND, OR, XOR, NOT, NAND, NOR and XNOR.

The AND gate is named so because, if 0 is false and 1 is true, the gate acts in the
same way as the logical "and" operator. The output is "true" when both inputs are
"true." Otherwise, the output is "false." In other words, the output is 1 only when
both inputs are 1.

The OR gate gets its name from behaving like the logical inclusive "or." The output
is true if one or both of the inputs are true. If both inputs are false, then the output
is false. In other words, for the output to be 1, at least one input must be 1.

The XOR (exclusive-OR) gate acts in the same way as the logical "either/or." The
output is true if either, but not both, of the inputs are true. The output is false if
both inputs are "false" or if both inputs are true. Similarly, the output is 1 if the
inputs are different but 0 if the inputs are the same.

A logical inverter, sometimes called a NOT gate to differentiate it from other types
of electronic inverter devices, has only one input. A NOT gate reverses the logic
state. If the input is 1, then the output is 0. If the input is 0, then the output is 1.

The NAND (Negated AND) gate operates as an AND gate followed by a NOT gate.
It acts in the manner of the logical operation "and" followed by negation. The
output is false if both inputs are true. Otherwise, the output is true.

The NOR (NOT OR) gate is a combination OR gate followed by an inverter. Its
output is true if both inputs are false. Otherwise, the output is false.
The XNOR (exclusive-NOR) gate is a combination of an XOR gate followed by an
inverter. Its output is true if the inputs are the same and false if the inputs are
different.

Procedure:
1. Open Vivado app and create or select the project.
2. Click on next and select RTL project type.
3. Click on next, go to create source file and select verilog file type with a
unique filename.
4. Select target and system language to be verilog and click on next.
5. Select your editor file in sources and enter the appropriate verilog code as
per the design
6. Also enter the test bench module.
7. Check the code for any errors, run the simulation and record the
observation.

CIRCUITS AND TABLES

Truth Table:
A B OUTPUT (A.B)
0 0 0
0 1 0
1 0 0
1 1 1

Symbol:
Truth Table:
A B OUTPUT (A+B)
0 0 0
0 1 1
1 0 1
1 1 1

Symbol:

Truth table:
A OUTPUT (A’)
0 1
1 0

Symbol:
Truth Table:
A B OUTPUT (A^B)
0 0 0
0 1 1
1 0 1
1 1 0

Symbol:

Truth Table:
A B OUTPUT (A’.B’)
0 0 1
0 1 0
1 0 0
1 1 0

Symbol:
CODE:
GATE LEVEL
module Gates(
input a,
input b,
output c,
output d,
output e,
output f,
output g,
output h,
output i
);
and (c,a,b);
or (d,a,b);
xor (e,a,b);
not (f,a);
xnor (g,a,b);
nor (h,a,b);
nand (i,a,b);
endmodule

module gatetb;
reg a,b;
wire c,d,e,f,g,h,i;
Gates gate(a,b,c,d,e,f,g,h,i);
initial
begin
a=0;b=0;#200;
a=0;b=1;#200;
a=1;b=0;#200;
a=1;b=1;#200;
end
endmodule

DATA FLOW
module Gates_DF(
input a,
input b,
output c,
output d,
output e,
output f,
output g,
output h,
output i
);
assign c=a&b;
assign d=a+b;
assign e=a^b;
assign f=~a;
assign g=(~(a^b));
assign h=(~(a+b));
assign i=(~(a&b));
endmodule

module gatetb;
reg a,b;
wire c,d,e,f,g,h,i;
Gates gate(a,b,c,d,e,f,g,h,i);
initial
begin
a=0;b=0;#200;
a=0;b=1;#200;
a=1;b=0;#200;
a=1;b=1;#200;
end
endmodule

BEHAVIOURAL MODEL
module Gates_BM(
input a,
input b,
output c,
output d,
output e,
output f,
output g,
output h,
output i
 );
reg c,d,e,f,g,h,i;
always@(a or b)
begin
c=a&b;
d=a+b;
e=a^b;
f=~a;
g=(~(a^b));
h=(~(a+b));
i=(~(a&b));
end
endmodule

module gatetb;
reg a,b;
wire c,d,e,f,g,h,i;
Gates gate(a,b,c,d,e,f,g,h,i);
initial
begin
a=0;b=0;#200;
a=0;b=1;#200;
a=1;b=0;#200;
a=1;b=1;#200;
end
endmodule
Observation:

Challenges:
1. In the Behavioural Model, all the outputs are required to be declared as
register variables.
2. Test bench is the same for all models.
3. In the Data Flow Model, all the outputs are required to be declared as wire
variables.
4. Avoid syntax errors like colon or semicolon. Use appropriate syntax.
5. Before simulating the present code, close the previous simulation.
6. Always place the test module at top in source.
7. Make sure to end all begin blocks.
8. In test bench make sure to use all possible cases to ensure that the design
is accurate and works for all test cases.
9. Verify the result with the truth table.

Result:
Hence, the basic and, or, xor, not, xnor, nor and nand logic gates are realised.
 EXPERIMENT - 02
8 TO 3 ENCODER
Aim:
To design a 8 to 3 Encoder

Apparatus:
1)PC installed with Vivado
2)Keyboard
3)Mouse
4)Monitor

Theory:
An encoder is a digital circuit or device that performs the function of
converting a set of input signals into a coded output. The primary purpose of an
encoder is to represent information in a more efficient or compact form. There are
various types of encoders, and they serve different applications.
Two common types are:
Priority Encoder: This type of encoder is used when multiple input lines are active,
and it prioritizes them based on the significance of the input lines. The output
represents the binary code of the highest-priority active input.
Decimal-to-Binary Encoder: This encoder is designed to convert a decimal (BCD -
Binary Coded Decimal) input into its equivalent binary representation. For
example, a 4-to-2 decimal-to-binary encoder takes four inputs representing a
decimal digit and produces a 2-bit binary code.
Encoders are widely used in digital systems for tasks such as address decoding in
memory circuits, data compression, and communication systems. They play a
crucial role in converting different types of data into a format that is suitable for
processing or transmission within digital systems. The specific design and
functionality of an encoder depend on the application requirements and the type
of encoding needed.
Procedure:
1. Open Vivado app and create or select the project.
2. Click on next and select RTL project type.
3. Click on next, go to create source file and select verilog file type with a
unique filename.
4. Select target and system language to be verilog and click on next.
5. Select your editor file in sources and enter the appropriate verilog code
as per the design.
6. Also enter the test bench module.
7. Check the code for any errors, run the simulation and record the
observation.
Circuit Diagram:

Truth Table:
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A2 A1 A0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
CODE:
GATE LEVEL
module ENC_8_3(
input i0,
input i1,
input i2,
input i3,
input i4,
input i5,
input i6,
input i7,
output d0,
output d1,
output d2
);
or x1(d0,i1,i3,i5,i7);
or x2(d1,i2,i3,i6,i7);
or x3(d2,i4,i5,i6,i7);
endmodule

module enctb;
reg i0,i1,i2,i3,i4,i5,i6,i7;
wire d0,d1,d2;
ENC_8_3 enc83(i0,i1,i2,i3,i4,i5,i6,i7,d0,d1,d2);
initial
begin
i0=1;i1=0;i2=0;i3=0;i4=0;i5=0;i6=0;i7=0;#100;
i0=0;i1=1;i2=0;i3=0;i4=0;i5=0;i6=0;i7=0;#100;
i0=0;i1=0;i2=1;i3=0;i4=0;i5=0;i6=0;i7=0;#100;
i0=0;i1=0;i2=0;i3=1;i4=0;i5=0;i6=0;i7=0;#100;
i0=0;i1=0;i2=0;i3=0;i4=1;i5=0;i6=0;i7=0;#100;
i0=0;i1=0;i2=0;i3=0;i4=0;i5=1;i6=0;i7=0;#100;
i0=0;i1=0;i2=0;i3=0;i4=0;i5=0;i6=1;i7=0;#100;
i0=0;i1=0;i2=0;i3=0;i4=0;i5=0;i6=0;i7=1;#100;
end
endmodule

DATA FLOW
module ENC_8_3_DF(
input i0,
input i1,
input i2,
input i3,
input i4,
input i5,
input i6,
input i7,
output d0,
output d1,
output d2
);
assign d0=i1+i3+i5+i7;
assign d1=i2+i3+i6+i7;
assign d2=i4+i5+i6+i7;
endmodule

module enctb;
reg i0,i1,i2,i3,i4,i5,i6,i7;
wire d0,d1,d2;
ENC_8_3 enc83(i0,i1,i2,i3,i4,i5,i6,i7,d0,d1,d2);
initial
begin
i0=1;i1=0;i2=0;i3=0;i4=0;i5=0;i6=0;i7=0;#100;
i0=0;i1=1;i2=0;i3=0;i4=0;i5=0;i6=0;i7=0;#100;
i0=0;i1=0;i2=1;i3=0;i4=0;i5=0;i6=0;i7=0;#100;
i0=0;i1=0;i2=0;i3=1;i4=0;i5=0;i6=0;i7=0;#100;
i0=0;i1=0;i2=0;i3=0;i4=1;i5=0;i6=0;i7=0;#100;
i0=0;i1=0;i2=0;i3=0;i4=0;i5=1;i6=0;i7=0;#100;
i0=0;i1=0;i2=0;i3=0;i4=0;i5=0;i6=1;i7=0;#100;
i0=0;i1=0;i2=0;i3=0;i4=0;i5=0;i6=0;i7=1;#100;
end
endmodule

BEHAVIOURAL MODEL
module ENC_8_3_BM(
input i0,
input i1,
input i2,
 input i3,
input i4,
input i5,
input i6,
input i7,
output d0,
output d1,
output d2
);
reg d0,d1,d2;
always@(i0 or i1 or i2 or i3 or i4 or i5 or i6 or i7)
begin
d0=i1+i3+i5+i7;
d1=i2+i3+i6+i7;
d2=i4+i5+i6+i7;
end
endmodule

module enctb;
reg i0,i1,i2,i3,i4,i5,i6,i7;
wire d0,d1,d2;
ENC_8_3 enc83(i0,i1,i2,i3,i4,i5,i6,i7,d0,d1,d2);
initial
begin
i0=1;i1=0;i2=0;i3=0;i4=0;i5=0;i6=0;i7=0;#100;
i0=0;i1=1;i2=0;i3=0;i4=0;i5=0;i6=0;i7=0;#100;
i0=0;i1=0;i2=1;i3=0;i4=0;i5=0;i6=0;i7=0;#100;
i0=0;i1=0;i2=0;i3=1;i4=0;i5=0;i6=0;i7=0;#100;
i0=0;i1=0;i2=0;i3=0;i4=1;i5=0;i6=0;i7=0;#100;
i0=0;i1=0;i2=0;i3=0;i4=0;i5=1;i6=0;i7=0;#100;
i0=0;i1=0;i2=0;i3=0;i4=0;i5=0;i6=1;i7=0;#100;
i0=0;i1=0;i2=0;i3=0;i4=0;i5=0;i6=0;i7=1;#100;
end
endmodule

Observation:
Challenges:
1. In the Behavioural Model, all the outputs are required to be declared as
register variables.
2. Test bench is the same for all models.
3. In the Data Flow Model, all the outputs are required to be declared as wire
variables.
4. Avoid syntax errors like colon or semicolon. Use appropriate syntax.
5. Before simulating the present code, close the previous simulation.
6. Always place the test module at top in source.
7. Make sure to end all begin blocks.
8. In test bench make sure to use all possible cases to ensure that the design
is accurate and works for all test cases.
9. Verify the result with the truth table.

Result:
Hence 8 to 3 Encoder is designed and simulated.
 8 TO 3 PRIORITY ENCODER
Aim: Design of 8-to-3 encoder (priority) using HDL code.
Apparatus:
1. PC installed with Vivado.
2. Keyboard.
3. Mouse.
4. Monitor.

Theory:
A priority encoder is used to give binary-coded n-bits of output for signifying the
location of the maximum order input of 2n inputs. If the minimum of two or above
inputs is high simultaneously, the input including the maximum priority will take
priority. This kind of encoder is used for controlling the requests of the interrupt by
performing on the maximum priority demand.

This encoder has the priority function which depends on the input’s relative
magnitudes. Therefore, the input including high magnitude must be encoded first.
In several practical applications, these encoders select the inputs with maximum
priority. So this kind of selection process is known as arbitration.

The best example of arbitration is, the computer has several input devices where
these devices try to provide the data for the computer immediately. In those
situations, this allows the input device that has the maximum priority between
those devices which try to access the system simultaneously.

There are different forms of priority encoders available. Some of the best examples
are discussed below like 8 to 3 type & 4 to 2 type.

These are standard integrated circuits and the best example of this is the TTL
74LS148 which includes 8 active LOW inputs & provides 3 outputs. First, this
encoder generates the output like the highest order input. For instance, if the input
lines are Y2, Y3 & Y5 then the output will be y5 because this is the highest order
input. Once the highest order input like Y5 is removed then the subsequent
maximum output would be for ‘Y3’ input & so on.
Procedure:
• Open Vivado Software and select “Create Project”.
• Enter the Project name and Project location.
• Choose the Project Type to “RTL Project” and press Next.
• In the Add Sources page, create a new Verilog File using the “Create
• File” option under the “+” option.
• In the Default Part page, select “ZedBoard Zynq Evaluation and
• Development kit” from the Boards and finish the setup.
• Enter the Code in the Design Source file and run the “Behavioural and
Simulation” from the Simulation Section to observe the output and note
down the values.
Truth Table:
CODE:
GATE LEVEL
module priority_8_3_encoder(
input y7,
input y6,
input y5,
input y4,
input y3,
input y2,
input y1,
input y0,
inout a,
inout b,
inout c,
inout d,
inout e,
output d2,
output d1,
output d0
);
wire y7n,y6n,y5n,y4n,y3n,y2n,y1n,y0n;

not (y7n,y7);
not (y6n,y6);
not (y5n,y5);
not (y4n,y4);
 not (y3n,y3);
not (y2n,y2);
not (y1n,y1);
not (y0n,y0);

and (a,y6n,y4n,y2n,y1);
and (b,y6n,y4n,y3);
and (c,y6n,y5);
and (d,y5n,y4n,y2);
and (e,y5n,y4n,y3);

or (d0,a,b,c,y7);
or (d1,d,e,y6,y7);
or (d2,y4,y5,y6,y7);
endmodule

module prioritytb;
reg y7,y6,y5,y4,y3,y2,y1,y0;
wire d2,d1,d0;
priority_8_3_encoder priorityencoder(y7,y6,y5,y4,y3,y2,y1,y0,a,b,c,d,e,d2,d1,d0);
initial
begin
y7=0;y6=0;y5=0;y4=0;y3=0;y2=0;y1=0;y0=1;#100;
y7=0;y6=0;y5=0;y4=0;y3=0;y2=0;y1=1;y0=1;#100;
y7=0;y6=0;y5=0;y4=1;y3=0;y2=1;y1=0;y0=0;#100;
y7=0;y6=0;y5=0;y4=0;y3=1;y2=0;y1=0;y0=0;#100;
y7=0;y6=0;y5=0;y4=1;y3=0;y2=0;y1=0;y0=0;#100;
y7=0;y6=0;y5=1;y4=0;y3=1;y2=0;y1=0;y0=0;#100;
y7=0;y6=1;y5=0;y4=1;y3=0;y2=0;y1=0;y0=0;#100;
y7=1;y6=0;y5=0;y4=0;y3=0;y2=0;y1=1;y0=0;#100;
end
endmodule

DATA FLOW
module priority_8_3_encoder_DF(
input y7,
input y6,
input y5,
input y4,
input y3,
input y2,
input y1,
input y0,
output a,
output b,
output c,
output d,
output e,
output d2,
output d1,
output d0
);
assign y7n=~y7;
assign y6n=~y6;
assign y5n=~y5;
assign y4n=~y4;
assign y3n=~y3;
assign y2n=~y2;
assign y1n=~y1;
assign y0n=~y0;
assign a=y6n&y4n&y2n&y1;
assign b=y6n&y4n&y3;
assign c=y6n&y5;
assign d=y5n&y4n&y2;
assign e=y5n&y4n&y3;
assign d0=a+b+c+y7;
assign d1=d+e+y6+y7;
assign d2=y4+y5+y6+y7;
endmodule

module prioritytb;
reg y7,y6,y5,y4,y3,y2,y1,y0;
wire d2,d1,d0;
priority_8_3_encoder priorityencoder(y7,y6,y5,y4,y3,y2,y1,y0,a,b,c,d,e,d2,d1,d0);
initial
begin
y7=0;y6=0;y5=0;y4=0;y3=0;y2=0;y1=0;y0=1;#100;
y7=0;y6=0;y5=0;y4=0;y3=0;y2=0;y1=1;y0=1;#100;
y7=0;y6=0;y5=0;y4=1;y3=0;y2=1;y1=0;y0=0;#100;
y7=0;y6=0;y5=0;y4=0;y3=1;y2=0;y1=0;y0=0;#100;
y7=0;y6=0;y5=0;y4=1;y3=0;y2=0;y1=0;y0=0;#100;
y7=0;y6=0;y5=1;y4=0;y3=1;y2=0;y1=0;y0=0;#100;
y7=0;y6=1;y5=0;y4=1;y3=0;y2=0;y1=0;y0=0;#100;
y7=1;y6=0;y5=0;y4=0;y3=0;y2=0;y1=1;y0=0;#100;
end
endmodule

BEHAVIOURAL MODEL
module priority_8_3_encoder_BM(
input y7,
input y6,
input y5,
input y4,
input y3,
input y2,
input y1,
input y0,
output a,
output b,
output c,
output d,
output e,
output d2,
output d1,
 output d0
);
reg y0n,y1n,y2n,y3n,y4n,y5n,y6n,y7n;
reg d2,d1,d0,a,b,c,d,e;
always@(y7 or y6 or y5 or y4 or y3 or y2 or y1 or y0)
begin
y7n=~y7;
y6n=~y6;
y5n=~y5;
y4n=~y4;
y3n=~y3;
y2n=~y2;
y1n=~y1;
y0n=~y0;
a=y6n&y4n&y2n&y1;
b=y6n&y4n&y3;
c=y6n&y5;
d=y5n&y4n&y2;
e=y5n&y4n&y3;
d0=a+b+c+y7;
d1=d+e+y6+y7;
d2=y4+y5+y6+y7;
end
endmodule

module prioritytb;
reg y7,y6,y5,y4,y3,y2,y1,y0;
wire d2,d1,d0;
priority_8_3_encoder priorityencoder(y7,y6,y5,y4,y3,y2,y1,y0,a,b,c,d,e,d2,d1,d0);
initial
begin
y7=0;y6=0;y5=0;y4=0;y3=0;y2=0;y1=0;y0=1;#100;
y7=0;y6=0;y5=0;y4=0;y3=0;y2=0;y1=1;y0=1;#100;
y7=0;y6=0;y5=0;y4=1;y3=0;y2=1;y1=0;y0=0;#100;
y7=0;y6=0;y5=0;y4=0;y3=1;y2=0;y1=0;y0=0;#100;
y7=0;y6=0;y5=0;y4=1;y3=0;y2=0;y1=0;y0=0;#100;
y7=0;y6=0;y5=1;y4=0;y3=1;y2=0;y1=0;y0=0;#100;
y7=0;y6=1;y5=0;y4=1;y3=0;y2=0;y1=0;y0=0;#100;
y7=1;y6=0;y5=0;y4=0;y3=0;y2=0;y1=1;y0=0;#100;
end
endmodule
Observation:

Challenges:
1. In the Behavioural Model, all the outputs are required to be declared as
register variables.
2. Test bench is the same for all models.
3. In the Data Flow Model, all the outputs are required to be declared as wire
variables.
4. Avoid syntax errors like colon or semicolon. Use appropriate syntax.
5. Before simulating the present code, close the previous simulation.
6. Always place the test module at top in source.
7. Make sure to end all begin blocks.
8. In test bench make sure to use all possible cases to ensure that the design
is accurate and works for all test cases.
9. Verify the result with the truth table.

Result:
Hence 8 to 3 encoder is designed and simulated.
 2 TO 4 DECODER
Aim:
To design a 2 to 4 decoder

Apparatus:
1)Vivado software
2)Windows Os
3)Monitor

Theory:
In the context of combinational circuits, a decoder is a digital circuit that takes an
input code and produces one or more output signals based on that code. The
main function of a decoder is to select one specific output line from among
several possible lines. Decoders are commonly used in digital systems for various
purposes, including addressing memory locations, controlling multiplexers, and
enabling specific functions based on input conditions.
Here are the basic characteristics of a decoder in a combinational circuit:
Input:
Code: The input to a decoder is typically a binary code. The number of input lines
(bits) determines the possible combinations or codes that the decoder can
interpret.
Output:
Enable Lines: In some decoders, there might be an additional input called an
"enable" line, which determines whether the decoder should be active or not.
Output Lines:
The decoder has multiple output lines, and each output corresponds to a specific
binary combination at the input.
Operation:
When a specific binary code is presented at the input of the decoder, the
corresponding output line is activated or asserted.
The output lines are mutually exclusive, meaning that only one output line is
active at a time.
Use Cases:
Memory Addressing: In memory systems, a decoder is often used to select a
specific memory location based on the binary address input.
Multiplexing/De-multiplexing: Decoders are used in multiplexers and de-
multiplexers to select one data input from multiple inputs.
Control Logic: Decoders can be used in control circuits to enable specific
operations based on certain conditions.
Types of Decoders:
Binary Decoder: Has 2^n output lines, where n is the number of input bits.
BCD (Binary-Coded Decimal) Decoder: Specifically designed to decode 4-bit
binary codes into their decimal equivalents.

Procedure:
1. Open Vivado app and create or select the project.
2. Click on next and select RTL project type.
3. Click on next, go to create source file and select verilog file type with a
unique filename.
4. Select target and system language to be verilog and click on next.
5. Select your editor file in sources and enter the appropriate verilog code as
per the design
6. Also enter the test bench module.
7. Check the code for any errors, run the simulation and record observation.
Circuit diagram:

Truth table:
E A1 A0 Y3 Y2 Y1 Y0
0 x X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
CODE:
GATE LEVEL
module DEC_2_4(
input b,
input c,
output d0,
output d1,
output d2,
output d3
);
wire bn,cn;
not x1(bn,b);
not x2(cn,c);
and x3(d0,bn,cn);
and x4(d1,bn,c);
and x5(d2,b,cn);
and x6(d3,b,c);
endmodule

module dectb;
reg b,c;
wire d0,d1,d2,d3;
DEC_2_4 dec(b,c,d0,d1,d2,d3);
initial
begin
b=0;c=0;#100;
b=0;c=1;#100;
b=1;c=0;#100;
b=1;c=1;#100;
end
endmodule

DATA FLOW
module Gates_DF(
input a,
input b,
output c,
output d,
output e,
output f,
output g,
output h,
output i
);
assign c=a&b;
assign d=a+b;
assign e=a^b;
assign f=~a;
assign g=(~(a^b));
assign h=(~(a+b));
assign i=(~(a&b));
endmodule
module dectb;
reg b,c;
wire d0,d1,d2,d3;
DEC_2_4 dec(b,c,d0,d1,d2,d3);
initial
begin
b=0;c=0;#100;
b=0;c=1;#100;
b=1;c=0;#100;
b=1;c=1;#100;
end
endmodule

BEHAVIOURAL MODEL
module DEC_2_4(
input b,
input c,
output d0,
output d1,
output d2,
output d3
);
reg d0,d1,d2,d3,bn,cn;
always@(b or c)
begin
bn=~b;
cn=~c;
d0=bn&cn;
d1=bn&c;
d2=b&cn;
d3=b&c;
end
endmodule

module dectb;
reg b,c;
wire d0,d1,d2,d3;
DEC_2_4 dec(b,c,d0,d1,d2,d3);
initial
begin
b=0;c=0;#100;
b=0;c=1;#100;
b=1;c=0;#100;
b=1;c=1;#100;
end
endmodule
Observation:

Challenges:
1. In the Behavioural Model, all the outputs are required to be declared as
register variables.
2. Test bench is the same for all models.
3. In the Data Flow Model, all the outputs are required to be declared as wire
variables.
4. Avoid syntax errors like colon or semicolon. Use appropriate syntax.
5. Before simulating the present code, close the previous simulation.
6. Always place the test module at top in source.
7. Make sure to end all begin blocks.
8. In test bench make sure to use all possible cases to ensure that the design
is accurate and works for all test cases.
9. Verify the result with the truth table.

Result:
Hence a 2 to 4 decoder is designed.
 EXPERIMENT – 03
MUX AND DEMUX
Aim: To design and realize 8x1 multiplexer and 1x8 demultiplexer.
Apparatus:

• PC installed with Vivado(IDE)

• Keyboard and Mouse
• Monitor

Theory:
A multiplexer is a data selector which selects a particular data line and produce
that in the output section. It is implemented using combinational circuits and is
very commonly used in digital systems. Sending data over multiplexing reduces
the cost of transmission lines and save bandwidth.
A 2^n:1 multiplexer has 2^n input lines, n select lines and a single output line.
A demultiplexer is also called as demux or data distributor and its operation is
quite opposite to that of a multiplexer. In order to select a particular output, we
have to use to particular set of select lines and the bit combination of these
select lines control the specific output line to be connected to the input at a given
instant.
A 1:2^n demultiplexer has 2^n output lines, n select lines and a single input line.

Procedure:
1. Open Vivado app and create or select the project.
2. Click on next and Select RTL project type.
3. Click on next, go to create source file and select verilog file type with a
unique filename.
4. Select target and system language to be verilog and click on next.
5. Select your editor file in sources and enter the appropriate verilog code as
per the design. Also enter the test bench module.
6. Check the code for any errors, run the simulation and record the
observation.
Design:
8x1 Multiplexer:

S2 S1 S0 Y
0 0 0 A0
0 0 1 A1
0 1 0 A2
0 1 1 A3
1 0 0 A4
1 0 1 A5
1 1 0 A6
1 1 1 A7

1x8 De-multiplexer:

S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 0 0 0 0 0 0 0 0 0 A

0 0 1 0 0 0 0 0 0 A 0

0 1 0 0 0 0 0 0 A 0 0

0 1 1 0 0 0 0 A 0 0 0

1 0 0 0 0 0 A 0 0 0 0

1 0 1 0 0 A 0 0 0 0 0

1 1 0 0 A 0 0 0 0 0 0

1 1 1 A 0 0 0 0 0 0 0
CODE:
8X1 MULTIPLEXER
GATE LEVEL
module MUX_8_1(
input i0,
input i1,
input i2,
input i3,
input i4,
input i5,
input i6,
input i7,
input s0,
input s1,
input s2,
output x,
output d0,
output d1,
output d2,
output d3,
output d4,
output d5,
output d6,
output d7
);
wire s0n,s1n,s2n;
not x1(s0n,s0);
not x2(s1n,s1);
not x3(s2n,s2);
and x4(d0,s0n,s1n,s2n,i0);
and x5(d1,s0n,s1n,s2,i1);
and x6(d2,s0n,s1,s2n,i2);
and x7(d3,s0n,s1,s2,i3);
and x8(d4,s0,s1n,s2n,i4);
and x9(d5,s0,s1n,s2,i5);
and x10(d6,s0,s1,s2n,i6);
and x11(d7,s0,s1,s2,i7);
or x12(x,d0,d1,d2,d3,d4,d5,d6,d7);
endmodule

module muxtb;
reg i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2;
wire x;
MUX_8_1 mux81(i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2,x,d0,d1,d2,d3,d4,d5,d6,d7);
initial
begin
s0=0;s1=0;s2=0;i0=1;i1=0;i2=0;i3=0;i4=0;i5=0;i6=0;i7=0;#100;
s0=0;s1=0;s2=1;i0=0;i1=1;i2=0;i3=0;i4=0;i5=0;i6=0;i7=0;#100;
s0=0;s1=1;s2=0;i0=0;i1=0;i2=1;i3=0;i4=0;i5=0;i6=0;i7=0;#100;
s0=0;s1=1;s2=1;i0=0;i1=0;i2=0;i3=1;i4=0;i5=0;i6=0;i7=0;#100;
s0=1;s1=0;s2=0;i0=0;i1=0;i2=0;i3=0;i4=1;i5=0;i6=0;i7=0;#100;
s0=1;s1=0;s2=1;i0=0;i1=0;i2=0;i3=0;i4=0;i5=1;i6=0;i7=0;#100;
s0=1;s1=1;s2=0;i0=0;i1=0;i2=0;i3=0;i4=0;i5=0;i6=1;i7=0;#100;
s0=1;s1=1;s2=1;i0=0;i1=0;i2=0;i3=0;i4=0;i5=0;i6=0;i7=1;#100;
end
endmodule

DATA FLOW
module MUX_8_1_DF(
input i0,
input i1,
input i2,
input i3,
input i4,
input i5,
input i6,
input i7,
input s0,
input s1,
input s2,
output x,
output d0,
output d1,
output d2,
output d3,
output d4,
output d5,
output d6,
output d7
 );
wire s0n,s1n,s2n,x,d0,d1,d2,d3,d4,d5,d6,d7;
assign s0n=~s0;
assign s1n=~s1;
assign s2n=~s2;
assign d0=s2n&s1n&s0n&i0;
assign d1=s2n&s1n&s0&i1;
assign d2=s2n&s1&s0n&i2;
assign d3=s2n&s1&s0&i3;
assign d4=s2&s1n&s0n&i4;
assign d5=s2&s1n&s0&i5;
assign d6=s2&s1&s0n&i6;
assign d7=s2&s1&s0&i7;
assign x=d0+d1+d2+d3+d4+d5+d6+d7;
endmodule

module muxtb;
reg i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2;
wire x;
MUX_8_1 mux81(i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2,x,d0,d1,d2,d3,d4,d5,d6,d7);
initial
begin
s0=0;s1=0;s2=0;i0=1;i1=0;i2=0;i3=0;i4=0;i5=0;i6=0;i7=0;#100;
s0=0;s1=0;s2=1;i0=0;i1=1;i2=0;i3=0;i4=0;i5=0;i6=0;i7=0;#100;
s0=0;s1=1;s2=0;i0=0;i1=0;i2=1;i3=0;i4=0;i5=0;i6=0;i7=0;#100;
s0=0;s1=1;s2=1;i0=0;i1=0;i2=0;i3=1;i4=0;i5=0;i6=0;i7=0;#100;
s0=1;s1=0;s2=0;i0=0;i1=0;i2=0;i3=0;i4=1;i5=0;i6=0;i7=0;#100;
s0=1;s1=0;s2=1;i0=0;i1=0;i2=0;i3=0;i4=0;i5=1;i6=0;i7=0;#100;
s0=1;s1=1;s2=0;i0=0;i1=0;i2=0;i3=0;i4=0;i5=0;i6=1;i7=0;#100;
s0=1;s1=1;s2=1;i0=0;i1=0;i2=0;i3=0;i4=0;i5=0;i6=0;i7=1;#100;
end
endmodule

BEHAVIOURAL MODEL
module MUX_8_1_BM(
input i0,
input i1,
input i2,
input i3,
input i4,
input i5,
input i6,
input i7,
input s0,
input s1,
input s2,
output x,
output d0,
output d1,
output d2,
output d3,
output d4,
output d5,
 output d6,
output d7
);
reg s0n,s1n,s2n;
reg x,d0,d1,d2,d3,d4,d5,d6,d7;
always@(i0 or i1 or i2 or i3 or i4 or i5 or i6 or i7 or s0 or s1 or s2)
begin
s0n=~s0;
s1n=~s1;
s2n=~s2;
d0=s2n&s1n&s0n&i0;
d1=s2n&s1n&s0&i1;
d2=s2n&s1&s0n&i2;
d3=s2n&s1&s0&i3;
d4=s2&s1n&s0n&i4;
d5=s2&s1n&s0&i5;
d6=s2&s1&s0n&i6;
d7=s2&s1&s0&i7;
x=d0+d1+d2+d3+d4+d5+d6+d7;
end
endmodule

module muxtb;
reg i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2;
wire x;
MUX_8_1 mux81(i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2,x,d0,d1,d2,d3,d4,d5,d6,d7);
initial
begin
s0=0;s1=0;s2=0;i0=1;i1=0;i2=0;i3=0;i4=0;i5=0;i6=0;i7=0;#100;
s0=0;s1=0;s2=1;i0=0;i1=1;i2=0;i3=0;i4=0;i5=0;i6=0;i7=0;#100;
s0=0;s1=1;s2=0;i0=0;i1=0;i2=1;i3=0;i4=0;i5=0;i6=0;i7=0;#100;
s0=0;s1=1;s2=1;i0=0;i1=0;i2=0;i3=1;i4=0;i5=0;i6=0;i7=0;#100;
s0=1;s1=0;s2=0;i0=0;i1=0;i2=0;i3=0;i4=1;i5=0;i6=0;i7=0;#100;
s0=1;s1=0;s2=1;i0=0;i1=0;i2=0;i3=0;i4=0;i5=1;i6=0;i7=0;#100;
s0=1;s1=1;s2=0;i0=0;i1=0;i2=0;i3=0;i4=0;i5=0;i6=1;i7=0;#100;
s0=1;s1=1;s2=1;i0=0;i1=0;i2=0;i3=0;i4=0;i5=0;i6=0;i7=1;#100;
end
endmodule

Observation:
CODE:
1X8 DEMULTIPLEXER
GATE LEVEL
module DEMUX_1_8(
input a,
input s0,
input s1,
input s2,
output d0,
output d1,
output d2,
output d3,
output d4,
output d5,
output d6,
output d7
);
wire s0n,s1n,s2n;
not (s0n,s0);
not (s1n,s1);
not (s2n,s2);
and (d0,s0n,s1n,s2n,a);
and (d1,s0n,s1n,s2,a);
and (d2,s0n,s1,s2n,a);
and (d3,s0n,s1,s2,a);
and (d4,s0,s1n,s2n,a);
and (d5,s0,s1n,s2,a);
and (d6,s0,s1,s2n,a);
and (d7,s0,s1,s2,a);
endmodule

module demuxtb;
reg a,s0,s1,s2;
wire d0,d1,d2,d3,d4,d5,d6,d7;
DEMUX_1_8 demux(a,s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7);
initial
begin
a=1;s0=0;s1=0;s2=0;#100;
a=1;s0=0;s1=0;s2=1;#100;
a=1;s0=0;s1=1;s2=0;#100;
a=1;s0=0;s1=1;s2=1;#100;
a=1;s0=1;s1=0;s2=0;#100;
a=1;s0=1;s1=0;s2=1;#100;
a=1;s0=1;s1=1;s2=0;#100;
a=1;s0=1;s1=1;s2=1;#100;
end
endmodule
 DATA FLOW
module DEMUX_1_8_DF(
input a,
input s0,
input s1,
input s2,
output d0,
output d1,
output d2,
output d3,
output d4,
output d5,
output d6,
output d7
);
wire s0n,s1n,s2n;
assign s0n=~s0;
assign s1n=~s1;
assign s2n=~s2;
assign d0=s0n&s1n&s2n&a;
assign d1=s0n&s1n&s2&a;
assign d2=s0n&s1&s2n&a;
assign d3=s0n&s1&s2&a;
assign d4=s0&s1n&s2n&a;
assign d5=s0&s1n&s2&a;
assign d6=s0&s1&s2n&a;
assign d7=s0&s1&s2&a;
endmodule

module demuxtb;
reg a,s0,s1,s2;
wire d0,d1,d2,d3,d4,d5,d6,d7;
DEMUX_1_8 demux(a,s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7);
initial
begin
a=1;s0=0;s1=0;s2=0;#100;
a=1;s0=0;s1=0;s2=1;#100;
a=1;s0=0;s1=1;s2=0;#100;
a=1;s0=0;s1=1;s2=1;#100;
a=1;s0=1;s1=0;s2=0;#100;
a=1;s0=1;s1=0;s2=1;#100;
a=1;s0=1;s1=1;s2=0;#100;
a=1;s0=1;s1=1;s2=1;#100;
end
endmodule
 BEHAVIOURAL MODEL
module DEMUX_1_8_BM(
input a,
input s0,
input s1,
input s2,
output d0,
output d1,
output d2,
output d3,
output d4,
output d5,
output d6,
output d7
);
reg s0n,s1n,s2n,d0,d1,d2,d3,d4,d5,d6,d7;
always@(a or s0 or s1 or s2)
begin
s0n=~s0;
s1n=~s1;
s2n=~s2;
d0=s0n&s1n&s2n&a;
d1=s0n&s1n&s2&a;
d2=s0n&s1&s2n&a;
d3=s0n&s1&s2&a;
d4=s0&s1n&s2n&a;
d5=s0&s1n&s2&a;
d6=s0&s1&s2n&a;
d7=s0&s1&s2&a;
end
endmodule

module demuxtb;
reg a,s0,s1,s2;
wire d0,d1,d2,d3,d4,d5,d6,d7;
DEMUX_1_8 demux(a,s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7);
initial
begin
a=1;s0=0;s1=0;s2=0;#100;
a=1;s0=0;s1=0;s2=1;#100;
a=1;s0=0;s1=1;s2=0;#100;
a=1;s0=0;s1=1;s2=1;#100;
a=1;s0=1;s1=0;s2=0;#100;
a=1;s0=1;s1=0;s2=1;#100;
a=1;s0=1;s1=1;s2=0;#100;
a=1;s0=1;s1=1;s2=1;#100;
end
endmodule
Observation:

Challenges:
1. In the Behavioural Model, all the outputs are required to be declared as
register variables.
2. Test bench is the same for all models.
3. In the Data Flow Model, all the outputs are required to be declared as wire
variables.
4. Avoid syntax errors like colon or semicolon. Use appropriate syntax.
5. Before simulating the present code, close the previous simulation.
6. Always place the test module at top in source.
7. Make sure to end all begin blocks.
8. In test bench make sure to use all possible cases to ensure that the design
is accurate and works for all test cases.
9. Verify the result with the truth table.

Result:
Hence, the design of an 8x1 Multiplexer and 1x8 Demultiplexer using verilog has
been done and simulated.
 EXPERIMENT - 04
4 BIT BINARY TO GRAY CODE CONVERTER

Aim:
Design of 4 bit binary to gray code converter

Apparatus:
• PC installed with Vivado(IDE)
• Keyboard and Mouse
• Monitor

Theory:
Binary to Gray code conversion is a fundamental process in digital systems and
communication, particularly in cases where minimizing errors during transitions
between consecutive values is critical. This conversion involves transforming a
binary number into its Gray code equivalent, also known as reflected binary code
Gray code is a binary numeral system where successive values differ by only one
bit.
This property ensures that transitions between adjacent Gray code values involve
only a single-bit change, reducing errors in applications like rotary encoders and
digital communication systems
The conversion algorithm proceeds bit by bit, starting with the Most Significant Bit
(MSB) and iteratively performing an XOR operation between each bit of the binary
number and its preceding bit.
The result of the XOR operation gives the corresponding bit in the Gray code.

Procedure:
1. Open Vivado app and create or select the project.
2. Click on next and select RTL project type.
3. Click on next, go to create source file and select verilog file type with a
unique filename.
4. Select target and system language to be verilog and click on next.
5. Select your editor file in sources and enter the appropriate verilog code as
per the design. Also enter the test bench module.
Design:

Truth Table:
CODE:
GATE LEVEL
module BIT_4_Binary_to_Gray(
input b3,
input b2,
input b1,
input b0,
output g3,
output g2,
output g1,
output g0
);
xnor (g3,b3,1);
xor (g2,b3,b2);
xor (g1,b2,b1);
xor (g0,b1,b0);
endmodule

module bit_4_tb;
reg b3,b2,b1,b0;
wire g3,g2,g1,g0;
BIT_4_Binary_to_Gray binarytogray(b3,b2,b1,b0,g3,g2,g1,g0);
initial
begin
b3=0;b2=0;b1=0;b0=0;#100;
b3=0;b2=0;b1=0;b0=1;#100;
b3=0;b2=0;b1=1;b0=0;#100;
b3=0;b2=0;b1=1;b0=1;#100;
b3=0;b2=1;b1=0;b0=0;#100;
b3=0;b2=1;b1=0;b0=1;#100;
b3=0;b2=1;b1=1;b0=0;#100;
b3=0;b2=1;b1=1;b0=1;#100;
b3=1;b2=0;b1=0;b0=0;#100;
b3=1;b2=0;b1=0;b0=1;#100;
b3=1;b2=0;b1=1;b0=0;#100;
b3=1;b2=0;b1=1;b0=1;#100;
b3=1;b2=1;b1=0;b0=0;#100;
b3=1;b2=1;b1=0;b0=1;#100;
b3=1;b2=1;b1=1;b0=0;#100;
b3=1;b2=1;b1=1;b0=1;#100;
end
endmodule

DATA FLOW
module BIT4_BTOG_DF(
input b3,
input b2,
input b1,
input b0,
output g3,
output g2,
output g1,
output g0 );
assign g3=b3;
assign g2=b3^b2;
assign g1=b2^b1;
assign g0=b1^b0;
endmodule

module bit_4_tb;
reg b3,b2,b1,b0;
wire g3,g2,g1,g0;
BIT_4_Binary_to_Gray binarytogray(b3,b2,b1,b0,g3,g2,g1,g0);
initial
begin
b3=0;b2=0;b1=0;b0=0;#100;
b3=0;b2=0;b1=0;b0=1;#100;
b3=0;b2=0;b1=1;b0=0;#100;
b3=0;b2=0;b1=1;b0=1;#100;
b3=0;b2=1;b1=0;b0=0;#100;
b3=0;b2=1;b1=0;b0=1;#100;
b3=0;b2=1;b1=1;b0=0;#100;
b3=0;b2=1;b1=1;b0=1;#100;
b3=1;b2=0;b1=0;b0=0;#100;
b3=1;b2=0;b1=0;b0=1;#100;
b3=1;b2=0;b1=1;b0=0;#100;
b3=1;b2=0;b1=1;b0=1;#100;
b3=1;b2=1;b1=0;b0=0;#100;
b3=1;b2=1;b1=0;b0=1;#100;
b3=1;b2=1;b1=1;b0=0;#100;
b3=1;b2=1;b1=1;b0=1;#100;
end
endmodule

BEHAVIOURAL MODEL
module BIT4_BTOG_BM(
input b3,
input b2,
input b1,
input b0,
output g3,
output g2,
output g1,
output g0
);

reg g0,g1,g2,g3;
always@(b3 or b2 or b1 or b0)
begin
g3=b3;
g2=b3^b2;
g1=b2^b1;
g0=b1^b0;
end
endmodule
module bit_4_tb;
reg b3,b2,b1,b0;
wire g3,g2,g1,g0;
BIT_4_Binary_to_Gray binarytogray(b3,b2,b1,b0,g3,g2,g1,g0);
initial
begin
b3=0;b2=0;b1=0;b0=0;#100;
b3=0;b2=0;b1=0;b0=1;#100;
b3=0;b2=0;b1=1;b0=0;#100;
b3=0;b2=0;b1=1;b0=1;#100;
b3=0;b2=1;b1=0;b0=0;#100;
b3=0;b2=1;b1=0;b0=1;#100;
b3=0;b2=1;b1=1;b0=0;#100;
b3=0;b2=1;b1=1;b0=1;#100;
b3=1;b2=0;b1=0;b0=0;#100;
b3=1;b2=0;b1=0;b0=1;#100;
b3=1;b2=0;b1=1;b0=0;#100;
b3=1;b2=0;b1=1;b0=1;#100;
b3=1;b2=1;b1=0;b0=0;#100;
b3=1;b2=1;b1=0;b0=1;#100;
b3=1;b2=1;b1=1;b0=0;#100;
b3=1;b2=1;b1=1;b0=1;#100;
end
endmodule
Observation:

Challenges:
1. In the Behavioural Model, all the outputs are required to be declared as
register variables.
2. Test bench is the same for all models.
3. In the Data Flow Model, all the outputs are required to be declared as wire
variables.
4. Avoid syntax errors like colon or semicolon. Use appropriate syntax.
5. Before simulating the present code, close the previous simulation.
6. Always place the test module at top in source.
7. Make sure to end all begin blocks.
8. In test bench make sure to use all possible cases to ensure that the design
is accurate and works for all test cases.
9. Verify the result with the truth table.

Result:
4 bit binary to gray code converter is designed in Verilog and simulated.
 EXPERIMENT - 05
4 BIT BINARY COMPARATOR
Aim:
Design of 4 bit binary comparator

Apparatus:
• PC installed with Vivado(IDE)
• Keyboard
• Mouse
• Monitor

Theory:
A 4-bit comparator is a digital circuit that compares two 4-bit binary
numbers and produces outputs indicating the relationship between the
two numbers. The primary purpose of a comparator is to determine
whether one binary number is equal to, greater than, or less than
another binary number.
Typically, a 4-bit comparator consists of four pairs of exclusive OR
(XOR) gates and AND gates, along with additional logic to handle the
various comparison outcomes. Each pair of XOR gates compares
corresponding bits from the two 4-bit numbers. The outputs of these
XOR gates feed into AND gates, which produce the final comparison
results.

The comparator outputs include three main signals: equality (EQ), less
than (LT), and greater than (GT). The equality signal is asserted when
the two 4-bit numbers are equal. The less than signal is activated when
the first number is less than the second, and the greater than signal is
triggered when the first number is greater than the second.
Procedure:
1. Open Vivado app and create or select the project.
2. Click on next and select RTL project type.
3. Click on next, go to create source file and select verilog file type
with a unique filename.
4. Select target and system language to be verilog and click on next.
5. Select your editor file in sources and enter the appropriate verilog
code as per the design
6. Also enter the test bench module.
7. Check the code for any errors, run the simulation and record the
observation.
Design:

Truth Table:

a3 a2 a1 a0 b3 b2 b1 b0 A=B A>B A<B

0 0 0 1 0 0 0 1 1 0 0

1 0 0 1 0 0 0 1 0 1 0

0 0 0 1 1 0 0 1 0 0 1
CODE:
GATE LEVEL
module COMP_4BIT(
input a3,
input a2,
input a1,
input a0,
input b3,
input b2,
input b1,
input b0,
output G,
output L,
output E
);
wire a3n,a2n,a1n,a0n,b3n,b2n,b1n,b0n;

not (a3n,a3);
not (a2n,a2);
not (a1n,a1);
not (a0n,a0);
not (b3n,b3);
not (b2n,b2);
not (b1n,b1);
not (b0n,b0);
xnor (e3,a3,b3);
xnor (e2,a2,b2);
xnor (e1,a1,b1);
xnor (e4,a0,b0);

and (g1,a3,b3n);
and (g2,e3,a2,b2n);
and (g3,e3,e2,a1,b1n);
and (g4,e3,e2,e1,a0,b0n);
or (G,g1,g2,g3,g4);

and (l1,a3n,b3);
and (l2,e3,a2n,b2);
and (l3,e3,e2,a1n,b1);
and (l4,e3,e2,e1,a0n,b0);
or (L,l1,l2,l3,l4);

and (E,e4,e3,e2,e1);
endmodule

module comptb;
reg a3,a2,a1,a0,b3,b2,b1,b0;
wire G,L,E;
COMP_4BIT comp4(a3,a2,a1,a0,b3,b2,b1,b0,G,L,E);
initial
begin
a3=0;a2=0;a1=0;a0=1;b3=0;b2=0;b1=0;b0=1;#200;
a3=1;a2=0;a1=0;a0=1;b3=0;b2=0;b1=0;b0=1;#200;
a3=0;a2=0;a1=0;a0=1;b3=1;b2=0;b1=0;b0=1;#200;
end
endmodule

DATA FLOW
module COMP_4BIT_DF(a, b, Gt_I, Eq_I, Lt_I, Gt, Eq, Lt);

input [3:0] a;
input [3:0] b;
input Gt_I = 2'b00;
input Eq_I = 2'b01;
input Lt_I = 2'b00;
output Gt, Eq, Lt;
wire x, y, z;

Comparator_new c0(.a(a), .b(b), .Gt_I(Gt_I), .Eq_I(Eq_I), .Lt_I(Lt_I), .Gt_O(x),

.Eq_O(y), .Lt_O(z));
Comparator_new c1(.a(a), .b(b), .Gt_I(x), .Eq_I(y), .Lt_I(z), .Gt_O(Gt), .Eq_O(Eq),
.Lt_O(Lt));

assign Gt_O = ~(a[3] & ~b[3] | ~a[3] & b[3]) & a[2] & ~b[2] | a[3] & ~b[3];
assign Eq_O = ~(a[2] & ~b[2] | ~a[2] & b[2]) & ~(a[3] & ~b[3] | ~a[3] & b[3]);
assign Lt_O = ~(a[3] & ~b[3] | ~a[3] & b[3]) & ~a[2] & b[2] | ~a[3] & b[3];
endmodule
module tb_Comparator_stru;
reg a, b;
wire Gt, Eq, Lt;
COMP_4BIT_DF tb(.a(a), .b(b), .Gt(Gt), .Eq(Eq), .Lt(Lt));
initial
begin
$dumpfile("test_Comparator_stru_out.vcd");
$dumpvars(-1, tb);
$monitor("%b", Gt);
$monitor("%b", Eq);
$monitor("%b", Lt);
end

initial
begin
a = 2'b00; b = 2'b00;#50;
a = 2'b01; b = 2'b00;#50;
a = 2'b01; b = 2'b01;#50;
a = 2'b01; b = 2'b10;#50;
a = 2'b10; b = 2'b10;#50;
a = 2'b11; b = 2'b10;#50;
a = 2'b11; b = 2'b11;#50;
end
endmodule
 BEHAVIOURAL MODEL
module COMP_4BIT_BM(
Data_in_A,
Data_in_B,
less,
equal,
greater
);
input [3:0] Data_in_A;
input [3:0] Data_in_B;
output less;
output equal;
output greater;
reg less;
reg equal;
reg greater;

always @(Data_in_A or Data_in_B)

begin
if(Data_in_A > Data_in_B)
begin
less = 0;
equal = 0;
greater = 1;
end
else if(Data_in_A == Data_in_B)
 begin
less = 0;
equal = 1;
greater = 0;
end
else
begin
less = 1;
equal = 0;
greater =0;
end
end
endmodule

module comp4bitbmtb;
reg [3:0] Data_in_A;
reg [3:0] Data_in_B;
wire less;
wire equal;
wire greater;
COMP_4BIT_BM comp4bitbm(
.Data_in_A(Data_in_A),
.Data_in_B(Data_in_B),
.less(less),
.equal(equal),
.greater(greater) );
 initial
begin
Data_in_A = 10;
Data_in_B = 12;
#100;
Data_in_A = 15;
Data_in_B = 11;
#100;
Data_in_A = 10;
Data_in_B = 10;
#100;
end
endmodule
Observation:
Challenges:
1. In the Behavioural Model, all the outputs are required to be declared as
register variables.
2. Test bench is the same for all models.
3. In the Data Flow Model, all the outputs are required to be declared as wire
variables.
4. Avoid syntax errors like colon or semicolon. Use appropriate syntax.
5. Before simulating the present code, close the previous simulation.
6. Always place the test module at top in source.
7. Make sure to end all begin blocks.
8. In test bench make sure to use all possible cases to ensure that the design
is accurate and works for all test cases.
9. Verify the result with the truth table.

Result:
Hence, 4 bit binary comparator is designed and realised.
 EXPERIMENT – 06
FULL ADDER
Aim: To design a full adder using three modelling styles
1. Gate-level Model Design
2. Dataflow Model Design
3. Behavioural Model Design

Apparatus:
1. Vivado Software.
2.Windows OS

Theory:
A full adder is a digital circuit that can perform addition on two binary digits, as
well as an input carry bit.
A full adder has two inputs, A and B, which are the binary digits to be added
together. It also has a third input, Cin, which is the carry input from the previous
stage (if any). The outputs of a full adder are the sum (S) of the two inputs, and the
carry out (Cout) from the addition. The sum is the least significant bit of the
addition, while the carry out is the most significant bit.

1. Gate-level Modelling: This style describes the full adder using gates like
AND, OR, and XOR. It's a lower-level abstraction than behavioural modelling and
is closer to the actual hardware implementation. You can use Verilog to describe
the circuit using gates.

2. Dataflow Modelling: This style describes the full adder using a set of
equations that define the output values in terms of the input values. It's similar to
behavioural modelling but focuses more on the dataflow aspect of the design. You
can use Verilog to describe the dataflow equations for the full adder.

3. Behavioural modelling: This style describes the functionality of the full

adder without specifying the internal hardware components. You can use HDLs
like Verilog or VHDL to describe the behaviour of the full adder, such as how it
adds two inputs (A and B) along with a carry-in (Cin) to produce a sum (Sum) and
a carry-out (Cout).
The full adder can be used to add two binary numbers together, as well as to
perform other arithmetic operations such as subtraction, multiplication, and
division. It is a fundamental building block in digital systems, and is used in many
different applications.

Procedure:
1. Open Vivado and create a new project.
2. In the 'Create a New Project' wizard, select the project location, project name,
and RTL project type. Click 'Next'.
3. In the 'Add Sources' window, click the '+' button to add a new source. Select
'Verilog' as the file type and click 'Next'.
4. Enter the desired file name and click 'Finish' to create the Verilog source file.
5. Write the Verilog code for gate model of the full adder.
6. Enter the desired file name and click 'Finish' to create the Verilog source file.
7. Save the Verilog file and return to Vivado.
8. In the 'Flow Navigator' pane, select 'Simulation' under the 'Run Simulation'
section.
9. In the 'Simulation Settings' pane, click 'Add Sources' and select the testbench
Verilog file you created.
10. Click 'Run Simulation' to simulate the full adder.
11. Similarly write the code for Data Flow and Behavioural Models and simulate.
Circuit Diagram:

Truth Table:
CODE:
GATE LEVEL
module FA_GL(
input a,
input b,
input c,
output s,
output co
);
wire i0,i1,i2;
and(i0,a,b);
and(i1,b,c);
and(i2,c,a);
xor(s,a,b,c);
or(co,i0,i1,i2);
endmodule

module FAtb;
reg a,b,c;
wire co,s;
FA_GL FAtb(a,b,c,s,co);
initial
begin
a=0;b=0;c=0;#100;
a=0;b=0;c=1;#100;
a=0;b=1;c=0;#100;
a=0;b=1;c=1;#100;
a=1;b=0;c=0;#100;
a=1;b=0;c=1;#100;
a=1;b=1;c=0;#100;
a=1;b=1;c=1;#100;
end
endmodule

DATA FLOW
module FA_DF(
input a,
input b,
input c,
output s,
output co
);
assign{co,s}=a+b+c;
endmodule

module FAtb;
reg a,b,c;
wire co,s;
FA_GL FAtb(a,b,c,s,co);
initial
begin
a=0;b=0;c=0;#100;
a=0;b=0;c=1;#100;
a=0;b=1;c=0;#100;
a=0;b=1;c=1;#100;
a=1;b=0;c=0;#100;
a=1;b=0;c=1;#100;
a=1;b=1;c=0;#100;
a=1;b=1;c=1;#100;
end
endmodule

BEHAVIOURAL MODEL
module FA_BM(
input a,
input b,
input c,
output s,
output co
);
reg s,co;
always@(a or b or c)
begin
s=(a^b)^c;
co=(a&b)|(b&c)|(c&a);
end
endmodule
module FAtb;
reg a,b,c;
wire co,s;
FA_GL FAtb(a,b,c,s,co);
initial
begin
a=0;b=0;c=0;#100;
a=0;b=0;c=1;#100;
a=0;b=1;c=0;#100;
a=0;b=1;c=1;#100;
a=1;b=0;c=0;#100;
a=1;b=0;c=1;#100;
a=1;b=1;c=0;#100;
a=1;b=1;c=1;#100;
end
endmodule
Observations:

Challenges:
1. In the Behavioural Model, all the outputs are required to be declared as
register variables.
2. Test bench is the same for all models.
3. In the Data Flow Model, all the outputs are required to be declared as wire
variables.
4. Avoid syntax errors like colon or semicolon. Use appropriate syntax.
5. Before simulating the present code, close the previous simulation.
6. Always place the test module at top in source.
7. Make sure to end all begin blocks.
8. In test bench make sure to use all possible cases to ensure that the design
is accurate and works for all test cases.
9. Verify the result with the truth table.

Result:
Hence, Full Adder is designed in three different modelling styles and its output is
verified.
 EXPERIMENT – 07
FLIP FLOPS
Aim: To design all types of flip flops which are
1. SR Flip Flop
2. JK Flip Flop
3. D Flip Flop
4. T Flip Flop

Apparatus:
1. Vivado Software.
2. Windows OS

Theory:
Flip-flop is a circuit that maintains a state until directed by input to change the
state. A basic flip-flop can be constructed using four-NAND or four-NOR gates.
Flip flop is popularly known as the basic digital memory circuit. It has its two
states as logic 1(High) and logic 0(low) states. A flip flop is a sequential circuit
which consist of single binary state of information or data. The digital circuit is a
flip flop which has two outputs and are of opposite states. It is also known as a
Bistable Multivibrator.

Types of flip-flops:
1. SR Flip Flop
2. JK Flip Flop
3. D Flip Flop
4. T Flip Flop

Procedure:
1. Open Vivado and create a new project.
2. In the 'Create a New Project' wizard, select the project location, project name,
and RTL project type. Click 'Next'.
3. In the 'Add Sources' window, click the '+' button to add a new source. Select
'Verilog' as the file type and click 'Next'.
4. Enter the desired file name and click 'Finish' to create the Verilog source file.
5. Write the Verilog code for gate model of the full adder.
6. Enter the desired file name and click 'Finish' to create the Verilog source file.
7. Save the Verilog file and return to Vivado.
8. In the 'Flow Navigator' pane, select 'Simulation' under the 'Run Simulation'
section.
9. In the 'Simulation Settings' pane, click 'Add Sources' and select the testbench
Verilog file you created.
10. Click 'Run Simulation' to simulate the full adder.
11. Similarly write the code for Data Flow and Behavioural Models and simulate.
 CIRCUITS AND TABLES
SR Flip Flop
Circuit Diagram:

Truth Table:
 JK Flip Flop
Circuit Diagram:

Truth Table:
 D Flip Flop
Circuit Diagram:

Truth Table:
 T Flip Flop
Circuit Diagram:

Truth Table:
CODE:
SR FLIP-FLOP
module SR_FF(
input s,
input r,
input q0,
input clk,
output q
);
reg q;
always @ (posedge clk)
begin
if(s==0&&r==0)
q=q0;
else if(s==0&&r==1)
q=0;
else if(s==1&&r==0)
q=1;
else if(s==1&&r==1)
q=1'bx;
end
endmodule

module SR_FFtb;
reg s,r,q0,clk;
wire q;
SR_FF SRtb(s,r,q0,clk,q);
initial
begin
clk=1;
forever #10 clk=~clk;
end
initial
begin
s=0;r=0;q0=0;#20;
s=0;r=0;q0=1;#20;
s=0;r=1;q0=0;#20;
s=0;r=1;q0=1;#20;
s=1;r=0;q0=0;#20;
s=1;r=0;q0=1;#20;
s=1;r=1;q0=0;#20;
s=1;r=1;q0=1;#20;
end
endmodule
 JK FLIP-FLOP
module JK_FF(
input j,
input k,
input q0,
input clk,
output q
);
reg q;
always @ (posedge clk)
begin
if(j==0&&k==0)
q=q0;
else if(j==0&&k==1)
q=0;
else if(j==1&&k==0)
q=1;
else if(j==1&&k==1)
assign q=~q0;
end
endmodule

module JK_FFtb;
reg j,k,q0,clk;
wire q;
JK_FF jktb(j,k,q0,clk,q);
initial
begin
clk=1;
forever #10 clk=~clk;
end
initial
begin
j=0;k=0;q0=0;#20;
j=0;k=0;q0=1;#20;
j=0;k=1;q0=0;#20;
j=0;k=1;q0=1;#20;
j=1;k=0;q0=0;#20;
j=1;k=0;q0=1;#20;
j=1;k=1;q0=0;#20;
j=1;k=1;q0=1;#20;
end
endmodule
 D FLIP-FLOP
module D_FF(
input d,
input q0,
input clk,
output q
);
reg q;
always @ (posedge clk)
begin
q=d;
end
endmodule

module JK_FFtb;
reg d,q0,clk;
wire q;
D_FF dtb(d,q0,clk,q);
initial
begin
clk=1;
forever #10 clk=~clk;
end
initial
begin
d=0;q0=0;#20;
d=0;q0=1;#20;
d=1;q0=0;#20;
d=1;q0=1;#20;
end
endmodule

T FLIP-FLOP
module T_FF(
input t,
input q0,
input clk,
output q
);
reg q;
always @ (posedge clk)
begin
if(t==0)
begin
q=q0;
end
else
begin
q=~q0;
end
end
endmodule

module T_FFtb;
reg t,q0,clk;
wire q;
T_FF ttb(t,q0,clk,q);
initial
begin
clk=1;
forever #10 clk=~clk;
end
initial
begin
t=0;q0=0;#20;
t=0;q0=1;#20;
t=1;q0=0;#20;
t=1;q0=1;#20;
end
endmodule
Observations:
SR Flip Flop

JK Flip Flop

D Flip Flop
 T Flip Flop

Challenges:
1. In the Behavioural Model, all the outputs are required to be declared as
register variables.
2. Test bench is the same for all models.
3. In the Data Flow Model, all the outputs are required to be declared as wire
variables.
4. Avoid syntax errors like colon or semicolon. Use appropriate syntax.
5. Before simulating the present code, close the previous simulation.
6. Always place the test module at top in source.
7. Make sure to end all begin blocks.
8. In test bench make sure to use all possible cases to ensure that the design
is accurate and works for all test cases.
9. Verify the result with the truth table.

Result:
Hence, all types of flip flops are designed and their output is verified.
 EXPERIMENT – 08
BINARY AND BCD COUNTERS
Aim: To design the Binary up , Binary down and BCD counters.
Apparatus:
1.Vivado Software.
2.Windows OS

Theory:
A binary counter is a type of sequential logic circuit which is able to count in
binary numbers. A binary counter can counter from 0 to 2(n-1), where n is the
total number of bits in the counter.

Basically, a binary counter is a type of digital circuit which counts the number of
clock pulses that occur over a time period.

The binary counters are built up of flip flops, where a flip flop is a most
elementary memory element that can store 1-bit of information. In a binary
counter, each flip flop represents one bit of the binary number. The counter
increases its count by one whenever a clock pulse occurs.

For example, a 3-bit binary counter can count from 000 (0) to 111 (7) before
wrapping around to 000 again. We can design a binary counter to count up or
down. Also, a binary counter has more advanced features such as ability to
reset the count to zero, to load a specific count, etc.

• Up Counter − The type of binary counter that counts upwards from zero to
its maximum count value is known as up counter. In the case of up counter,
the count is increased by one on each clock pulse.
• Down Counter − The type of binary counter that counts downwards from its
maximum count value to zero is known as a down counter. In the down
counter, the count value of the counter is decreased by one on each clock
pulse.
Procedure:
1. Open Vivado and create a new project.
2. In the 'Create a New Project' wizard, select the project location, project name,
and RTL project type. Click 'Next'.
3. In the 'Add Sources' window, click the '+' button to add a new source. Select
'Verilog' as the file type and click 'Next'.
4. Enter the desired file name and click 'Finish' to create the Verilog source file.
5. Write the Verilog code for gate model of the full adder.
6. Enter the desired file name and click 'Finish' to create the Verilog source file.
7. Save the Verilog file and return to Vivado.
8. In the 'Flow Navigator' pane, select 'Simulation' under the 'Run Simulation'
section.
9. In the 'Simulation Settings' pane, click 'Add Sources' and select the testbench
Verilog file you created.
10. Click 'Run Simulation' to simulate the full adder.
11. Similarly write the code for Data Flow and Behavioural Models and simulate.
 BINARY UP COUNTER

BINARY DOWN COUNTER

BCD COUNTER
CODE:
BINARY UP COUNTER
BEHAVIOURAL MODEL
module COUNTER(o,c);
input c;
output reg[3:0]o;
always@(posedge c)
begin
if(o<=4'b1111)
begin
o=o+1;
end
else
begin
o=4'b0000;
end
end
endmodule

module counter_tb();
reg c;
wire [3:0]o;
COUNTER x1(o,c);
initial
begin
c=1;
forever #20 c=~c;
end
endmodule

BINARY DOWN COUNTER

BEHAVIOURAL MODEL
module COUNTER(o,c);
input c;
output reg[3:0]o;
always@(posedge c)
begin
if(o>=4'b0000)
begin
o=o-1;
end
else
begin
o=4'b1111;
end
end
endmodule

module counter_tb();
reg c;
wire [3:0]o;
COUNTER x1(o,c);
initial
begin
c=1;
forever #20 c=~c;
end
endmodule

BCD COUNTER
BEHAVIOURAL MODEL
module counter_4_BIT(o,c);
input c;
output reg[3:0]o;
always@(posedge c)
begin
if(o<=4'b1001)
begin
o=o+1;
end
else
begin
o=4'b0000;
end
end
endmodule
module counter_tb();
reg c;
wire [3:0]o;
counter_4_BIT x1(o,c);
initial
begin
c=1;
forever #20 c=~c;
end
endmodule

Observation:

BINARY UP COUNTER

BINARY DOWN COUNTER

BCD COUNTER
Challenges:
1. In the Behavioural Model, all the outputs are required to be declared as
register variables.
2. Test bench is the same for all models.
3. In the Data Flow Model, all the outputs are required to be declared as wire
variables.
4. Avoid syntax errors like colon or semicolon. Use appropriate syntax.
5. Before simulating the present code, close the previous simulation.
6. Always place the test module at top in source.
7. Make sure to end all begin blocks.
8. In test bench make sure to use all possible cases to ensure that the design
is accurate and works for all test cases.
9. Verify the result with the truth table.

Result:
Hence, Binary up, down and BCD Counters are designed and their output is
verified.
 EXPERIMENT – 09
FINITE STATE MACHINE
Aim: To design a Finite State Machine (FSM).
Apparatus:
1.Vivado Software.
2.Windows OS

Theory:
A useful formalism for designing more complex digital circuits is that of the finite
state machine (FSM). Here, the circuit's function is broken down into a
collection of states and rules which determine when the system moves from
one state to another state. This concept can be committed to paper by drawing
what is called a state diagram.
The state diagram consists of nodes which represent the states and arrows
(sometimes called edges) which give the possible transitions between states.
The states usually are named something which indicates the function of that
state. It will be seen that the state is held in flip flops, therefore there must be
some mapping made between the states and their representation in the FFs. The
arrows should be labeled with some condition which must be satisfied in order
for that state transition to take place.Typically, the transitions are taken in
response to external stimuli.
Finally, the state machine must produce some desired configuration of outputs.
State transitions and the output configuration are mediated by combinational
logic acting on the inputs to the circuit and the circuit's internal state.

Procedure:
1. Open Vivado and create a new project.
2. In the 'Create a New Project' wizard, select the project location, project name,
and RTL project type. Click 'Next'.
3. In the 'Add Sources' window, click the '+' button to add a new source. Select
'Verilog' as the file type and click 'Next'.
4. Enter the desired file name and click 'Finish' to create the Verilog source file.
5. Write the Verilog code for gate model of the full adder.
6. Enter the desired file name and click 'Finish' to create the Verilog source file.
7. Save the Verilog file and return to Vivado.
8. In the 'Flow Navigator' pane, select 'Simulation' under the 'Run Simulation'
section.
9. In the 'Simulation Settings' pane, click 'Add Sources' and select the testbench
Verilog file you created.
10. Click 'Run Simulation' to simulate the full adder.
11. Similarly write the code for Data Flow and Behavioural Models and simulate.
Circuit Diagram:

CODE:
BEHAVIOURAL MODEL
module FSM( clk,in,rst,out);
input clk, in,rst;
output out;
reg [1:0]ps,ns;
parameter
s0=2'b00,
s1=2'b01,
s2=2'b10,
s3=2'b11;
always@(posedge clk or posedge rst)
begin
if(rst)
ps<=s0;
else
ps<=ns;
end
always@(in,ps)
begin
ns=s0;
case(ps)
s0:if(in)
ns=s1;
else
ns=s0;
s1:if(in)
ns=s1;
else
ns=s2;
s2:if(in)
ns=s3;
else
ns=s0;
s3:if(in)
ns=s1;
else
ns=s0;
endcase
end
assign out=(ps==s3)?1:0;
endmodule
module fsm_tb();
reg in,clk,rst;
wire out;
FSM x1(clk,in,rst,out);
initial
begin
clk=0;
forever #5 clk=~clk;
end
initial
begin
rst=1;#10;
rst=0;
in=1;#10;
in=0;#10;
in=1;#10;
in=1;#10;
in=0;#10;
end
endmodule
Observation:

Challenges:
1. In the Behavioural Model, all the outputs are required to be declared as
register variables.
2. Test bench is the same for all models.
3. In the Data Flow Model, all the outputs are required to be declared as wire
variables.
4. Avoid syntax errors like colon or semicolon. Use appropriate syntax.
5. Before simulating the present code, close the previous simulation.
6. Always place the test module at top in source.
7. Make sure to end all begin blocks.
8. In test bench make sure to use all possible cases to ensure that the design
is accurate and works for all test cases.
9. Verify the result with the truth table.

Result:
Hence, Finite State Machine is designed and its output is verified.
 ASSIGNMENT QUESTIONS
1. FULL SUBTRACTOR USING HALF
SUBTRACTORS
Aim: To realise and simulate full subtractor using half subtractors.
Apparatus:
• PC installed with Vivado(IDE)
• Keyboard
• Mouse
• Monitor

Theory:
A full subtractor is a combinational circuit that performs subtraction of two
bits, one is minuend and other is subtrahend, taking into account borrow of the
previous adjacent lower minuend bit. This circuit has three inputs and two
outputs. The three inputs A, B and bin, denote the minuend, subtrahend, and
previous borrow, respectively. The two outputs, D and Bout represent the
difference and output borrow, respectively. In this experiment the full subtractor
is realised using half subtractors and other gates.

Procedure:
1. Open Vivado app and create or select the project.
2. Click on next and Select RTL project type.
3. Click on next ,goto create source file and select verilog file type with a
unique filename.
4. Select target and system language to be verilog and click on next.
5. Select your editor file in sources and enter the appropriate verilog code as
per the design
6. Also enter the test bench module.
7. Check the code for any errors , run the simulation and record the
observation.
Design:
Half Subtractor:

A B D(Difference) b (Borrow)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Full Subtractor:

A B bin D Bout
(Difference) (Borrow)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
CODE:
Observation:

Challenges:
1. In the Behavioural Model, all the outputs are required to be declared as
register variables.
2. Test bench is the same for all models.
3. In the Data Flow Model, all the outputs are required to be declared as wire
variables.
4. Avoid syntax errors like colon or semicolon. Use appropriate syntax.
5. Before simulating the present code, close the previous simulation.
6. Always place the test module at top in source.
7. Make sure to end all begin blocks.
8. In test bench make sure to use all possible cases to ensure that the design
is accurate and works for all test cases.
9. Verify the result with the truth table.

Result:
Full subtractor is designed using half subtractor in Verilog and simulated.
 2. FULL ADDER USING 4 TO 1 MUX

Aim:
To design and simulate a full adder using 4 to 1 MUX.

Apparatus:
• Pc Installed with Vivado (IDE)
• Keyboard
• Mouse
• Monitor

Theory:
An adder is digital circuit that perform addition of numbers. In modern computer
adder resides in the arithmetic logic unit (ALU).
Full Adder
A full adder accepts two inputs bits and an input carry and generates a sum
output and an output carry. The first two inputs are A and B and the third input is
an input carry designated as Cin. When a full adder logic is designed we will be
able to string four of them together to create a 4 bit adder and cascade the carry
bit from one adder to the next.
Multiplexer
In electronics, a multiplexer (or MUX) is a device that selects one of several
analog or digital input signals and forwards the selected input into a single line. A
multiplexer of 2n inputs has n select lines, which are used to select which input
line to send to the output. Multiplexers are mainly used to increase the amount of
data that can be sent over the network within a certain amount of time and
bandwidth. A multiplexer is also called a data selector.
Full Adder using 4 to 1 Multiplexer
Multiplexer is also called a data selector, whose single output can be connected
to anyone of N different inputs. A 4 to 1 line multiplexer has 4 inputs and 1 output
line.
Multiplexer and Full adder are two different Digital Logic circuits. The Multiplexer
is a digital switch. It allows digital information from several sources to be routed
onto a single output line. On the other hand, the Full adder circuit performs the
addition of three bits and produces the Sum and Carry as an output. Our aim is to
build the Full Adder circuit using Multiplexers rather than the usual basic logic
gates.

Procedure:
1. Open Vivado app and create or select the project.
2. Click on next and select RTL project type.
3. Click on next, go to create source file and select Verilog file type with a
unique filename.
4. Select target and system language to be Verilog and click on next.
5. Select your editor file in sources and enter the appropriate Verilog code as
per the design.
6. Also enter the test bench module.
7. Check the code for any errors, run the simulation and record the
observation.
Design:

Truth Table:
CODE:
Observation:

Challenges:
1. In the Behavioural Model, all the outputs are required to be declared as
register variables.
2. Test bench is the same for all models.
3. In the Data Flow Model, all the outputs are required to be declared as wire
variables.
4. Avoid syntax errors like colon or semicolon. Use appropriate syntax.
5. Before simulating the present code, close the previous simulation.
6. Always place the test module at top in source.
7. Make sure to end all begin blocks.
8. In test bench make sure to use all possible cases to ensure that the design
is accurate and works for all test cases.
9. Verify the result with the truth table.

Result:
A full adder using 4 to 1 MUX has been designed and simulated.