1 Unit-I: Introduction to Testing

EC2V13-TESTING OF VLSI CIRCUITS

INTRODUCTION TO TESTING
Role of testing VLSI circuits
Testing is a critical phase in the development and production of VLSI (Very Large Scale
Integration) circuits. It ensures that the designed circuits function correctly and meet the desired
specifications. The role of testing in VLSI circuits can be broken down into several key aspects:
1. Defect Detection
• Purpose: Identify manufacturing defects, such as open circuits, short circuits, missing
connections, or transistor-level faults.
• Significance: Ensures the fabricated chip is free from physical defects caused during
the manufacturing process.
2. Functional Verification
• Purpose: Verify that the VLSI circuit performs all intended operations according to its
design specifications.
• Methods: Input patterns are applied to the circuit, and the output is compared with
expected results.
• Significance: Confirms the correctness of logical operations and circuit behavior.

3. Parametric Testing
• Purpose: Measure circuit parameters such as power consumption, timing performance,
and signal integrity.
• Significance: Ensures that the circuit meets performance criteria under specified
conditions.
4. Fault Isolation
• Purpose: Pinpoint specific faults in the circuit when errors are detected.
• Techniques: Techniques like fault models (e.g., stuck-at faults, transition faults) and
Automatic Test Pattern Generation (ATPG) are used.
• Significance: Helps identify areas for redesign or refinement.
5. Yield Improvement
• Purpose: Analyze test results to determine common failure modes and improve the
manufacturing process.
• Significance: Enhances production yield and reduces costs.
6. Quality Assurance
• Purpose: Guarantee the reliability and robustness of the VLSI circuit over its lifetime.

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• Methods: Burn-in testing and reliability testing simulate operating conditions to detect
potential early failures.
• Significance: Builds confidence in product quality for end users.

7. Test Time and Cost Optimization

• Purpose: Balance thorough testing with production efficiency.
• Strategies: Built-In Self-Test (BIST) and Design for Testability (DFT) techniques
reduce test time and complexity.
• Significance: Ensures cost-effectiveness without compromising quality.
8. Field Testing and Debugging
• Purpose: Detect and resolve errors that might occur during real-world use.
• Significance: Enhances product reliability and provides feedback for future designs

VLSI Trends Affecting Testing

1. Increasing Design Complexity
o Modern VLSI designs integrate billions of transistors with advanced
functionalities.
o Requires sophisticated fault models and automation tools like ATPG for
efficient testing.
2. Miniaturization and Smaller Nodes
o Scaling to 5nm, 3nm nodes increases sensitivity to defects and process
variations.
o Demands precise parametric and fault-specific testing techniques.
3. 3D ICs and Heterogeneous Integration
o Multi-die systems and stacked layers pose challenges for interconnect and TSV
testing.
o Non-invasive testing methods are crucial.
4. Low-Power Design
o Testing low-power circuits requires power-aware methods to avoid
overstressing the system.
o Verifying sleep modes and dynamic voltage operations adds complexity.
5. Advanced Packaging and Chiplets
o Chiplet architectures necessitate pre-bond and post-bond testing of individual
dies and interconnects.

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6. AI and Machine Learning in Testing

o AI-driven test optimization and predictive models improve fault detection.
o Enhances real-time diagnostics and adaptive testing.
7. Built-In Self-Test (BIST) and DFT
o Integration of BIST simplifies testing during production and operation.
o Enhanced DFT techniques improve fault coverage and debugging.
8. High-Speed and Mixed-Signal Designs
o High-frequency and mixed-signal circuits require advanced equipment and
signal integrity validation.
9. Reliability and Aging Effects
o Stress tests simulate long-term effects like NBTI and electromigration.
o On-chip monitors track real-time reliability.
10. IoT and Edge Devices
o Scalable, cost-effective testing is essential for high-volume, low-cost devices.
o Robust testing ensures performance in diverse environments.
These trends demand innovative test strategies to handle the complexities and
challenges of modern VLSI systems.
Stuck-at Faults
Stuck-at Fault
The most common model used for logical faults is the single stuck-at fault. It assumes that a
fault in a logic gate result in one of its inputs or the output is fixed at either a logic 0 (stuckat-
0) or at logic 1 (stuck-at-1). Stuck-at-0 and stuck-at-l faults are often abbreviated to s-a-0 and
s-a-1, respectively
Let us assume that in Fig.1 the A input of the NAND gate is s-a-1.

The NAND gate perceives the A input as a logic 1 irrespective of the logic value placed on the
input. For example, the output of the NAND gate is 0 for the input pattern A=0 and B=1, hen
input A is s-a-1 in. In the absence of the fault, the output will be 1. Thus, AB=01 can be

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considered as the test for the A input s-a-l, since there is a difference between the output of the
fault-free and faulty gate.
The single stuck-at fault model is often referred to as the classical fault model and offers a good
representation for the most common types of defects [e.g., shorts and opens in complementary
metal oxide semiconductor (CMOS) technology]. Fig. 2 illustrates the CMOS realization of
the two-input NAND.

The number 1 in the figure indicates an open, whereas the numbers 2 and 3 identify the short
between the output node and the ground and the short between the output node and the VDD,
respectively. A short in a CMOS result if not enough metal is removed by the photolithography,
whereas over-removal of metal results in an open circuit. Fault 1 in Fig. 2 will disconnect input
A from the gate of transistors T1 and T3. It has been shown that in such a situation one transistor
may conduct and the other remain nonconducting. Thus, the fault can be represented by a stuck
at value of A; if A is s-a-0, T1 will be ON and T3 OFF, and if A is s-a-l, T1 will be OFF and T3
ON. Fault 2 forces the output node to be shorted to VDD, that is, the fault can be considered as
an s-a-l fault. Similarly, fault 3 forces the output node to be s-a-0.
The stuck-at model is also used to represent multiple faults in circuits. In a multiple stuck-at
fault, it is assumed that more than one signal line in the circuit is stuck at logic 1 or logic 0; in
other words, a group of stuck-at faults exist in the circuit at the same time. A variation of the
multiple faults is the unidirectional fault. A multiple fault is unidirectional if all of its
constituent faults are either s-a-0 or s-a-l but not both simultaneously. The stuck-at model has
gained wide acceptance in the past mainly because of its relative success with small scale
integration. However, it is not very effective in accounting for all faults in present day very
large scale integrated (VLSI), circuits which mainly uses CMOS technology. Faults in CMOS

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circuits do not necessarily produce logical faults that can be described as stuck-at faults. For
example, in Fig. 2, faults 3 and 4 create stuck-on transistors faults.
Stuck-open and Stuck-short Faults
Stuck-open and stuck-short faults are generally referred to as transistor faults. Faults at the
physical level are called defects. The electrical or logic-level faults that can be produced by
physical defects are classified as defect-oriented faults. Examples of physical defects are
broken wires, bridges, improper semiconductor doping, and improperly formed devices. To
understand the operation of purely digital MOS circuits, the simple model of the transistor is
useful. A MOS transistor as a switch, a defect is modeled as the switch being permanently in
either the open or the shorted state.

Stuck-Open Fault:
Figure shows a NOR gate implemented using CMOS technology. P1 and P2 are PMOS
transistors when the gate terminal inputs A and B are 0. Further, the inputs A and B also applied
at the gate of NMOS transistors, N1 and N2, If A = B = 0 then P1 and P2 are shorted in the fault-
free circuit and only P2 is shorted in the faulty circuit. N1 and N2 are open in both circuits. In
CMOS circuit output C has some parasitic capacitance with the charge from the previous
operation of the circuit. In order to detect the fault, Z assumes value 0. The test vectors are, 10
or 00 which produces an output 0 or 1 in the good circuit and 0 or 0 in the faulty circuit. Figure
also shows gate level model of the CMOS NOR circuit. Here every series interconnection
between a supply node to output is replaced by AND gate. Further, a parallel interconnection
is replaced by an OR gate. The output is produced by a BUS network whose truth table is
shown in Figure. Furthermore, as unknown three-state simulation, the state in this model
indicates the short circuit between the supply nodes. Stuck-open fault of a PMOS transistor is
modeled as a stuck-at-1 fault at the corresponding input signal and that of an NMOS transistor
as a stuck-at-0 fault.

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Stuck-Short Fault:
In the gate-level model of above figure a stuck-short fault of a PMOS transistor is represented
as a stuck-at-0 fault at the corresponding input to a logic gate. Further, a stuck-short fault of an
NMOS transistor is represented as a stuck-at-1 fault of a gate input. For detecting the fault
P1 stuck short, a stuck-at-0 fault at the site where stuck-at-1 is shown in the figure. The input
vector 10 produces a 0/S output at C. Since S represents a short circuit between the supply
nodes, this test produces a high current in the faulty circuit when it reaches the steady state.
This current is orders of magnitude larger than the normal quiescent current of a CMOS circuit.
Therefore, measurement of device current detects the fault.
Permanent Faults
• Faults that occur due to permanent physical defects in the circuit.
• The faulty behavior persists until the defective component is repaired or replaced.
• Manufacturing defects, such as shorts, opens, or broken transistors.
• Wear and tear, such as electromigration or oxide breakdown.
• A stuck-at fault where a node is permanently fixed at logic 0 or logic 1.
• Broken interconnects causing open circuits.
• Use fault models like stuck-at fault and bridging fault models.
• Techniques: ATPG (Automatic Test Pattern Generation), BIST (Built-In Self-Test).
Intermittent Faults
• Faults that occur sporadically, making them difficult to predict or reproduce.
• The circuit alternates between correct and incorrect behavior.
• Process variations leading to marginal components.
• External factors like noise, temperature changes, or voltage fluctuations.
• Aging effects, such as degradation of transistors or interconnects.
• A memory cell intermittently failing to store a value.
• Timing violations caused by process variations or temperature spikes.
• Stress testing under different environmental conditions (temperature, voltage).
• Burn-in testing to identify marginal components.
• Random pattern testing to detect rare faults.
Pattern-Sensitive Faults
• Faults that manifest only for specific input patterns or combinations of signal states.
• These faults depend on the state of neighbouring cells or components.
• Coupling effects, where a fault in one node is triggered by the state of another.
• Crosstalk between signal lines.

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• Parasitic capacitances or resistances.

• A memory cell failing when a specific pattern of 1s and 0s is written.
• Logic gates failing for specific combinations of inputs due to coupling noise.
• March tests for memory, which systematically apply patterns to detect sensitive faults.
• Pattern-based ATPG to cover possible state combinations.
• Crosstalk and noise analysis during testing.
Functional Versus Structural Testing
Let us examine the testing of a ten-input AND function. Suppose that we apply an input
pattern 0101010101 and observe a 0 output.
This is a correct output, but what can we conclude: the gate under test is (A) an AND,
(B) not a NAND, (C) not a NOR, or (D) not an OR function? Since the obtained output
violates the truth tables of NAND and OR gates, only (B) and (D) are correct answers.
We could use another pattern, 1111111111, to make sure that the gate is not a NOR.
However, that does not guarantee that the given circuit will function correctly as an AND
gate for all possible input patterns.
Given ten inputs, it is possible to construct Boolean functions, and in the present
situation our functional test must allow us to conclude that the function is AND and not one
of the others. A complete functional test will check each entry of the truth table.
Though possible with ten inputs, such a test will be too long and impossible to use with
a real circuit with several hundred input lines.
Difficult as it is, the use of functional tests is often found necessary for verification of
design. Methods of design verification lie outside the scope of this book, which focuses on
hardware tests. The purpose of a hardware test (also referred to as manufacturing test) is to
discover any faults caused due to manufacturing defects or errors. Such tests are called
structural because they depend on the specific structure (gate types, interconnects, netlist)
of the circuit.
One of the greatest advantages of structural testing is that it allows us to develop
algorithms. Central to these algorithms are fault models. As we will see in later chapters,
most test generation and test evaluation (fault simulation) algorithms are based on selected
fault models.
Fault models:
Assertion Fault: An assertion expresses a property of a high-level function in the form:
“antecedent consequent,” where antecedent and consequent can be simple predicates like “line
L takes symbolic value v” or conjunctions of simple predicates.

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Behavioural Faults (Functional or High level): When the behavior of an electronic system
is described in computer-readable form, it is generally written in a programming language (such
as C) or some other hardware description language that resembles a programming language.
Structural Faults: The structure of a circuit may refer to its topology or to physical geometry.
Examples of structural faults are single stuck-at faults and bridging faults. Focus is on
manufacturing defects not functional aspect of DUT.

Common Structural Fault Models

➢Single stuck-at faults

➢Transistor open and short faults

➢Bridging Faults
➢Delay faults (transition, path)
➢Analog faults
Single Stuck-at faults

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XOR circuit has 12 fault sites (● ) and 24 single stuck-at faults

SSF (Single Stuck at fault) on fanout wires not equivalent to SSF on fanout branches
Faults on stems and faults on branches are counted separately
Example: E is fanout stem; L,F are fanout branches

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Multiple Stuck-at faults

Several stuck-at faults occur at the same time
- Important in high density circuits
𝐼𝑓 𝑡ℎ𝑒𝑟𝑒 𝑎𝑟𝑒 𝑁 𝑝𝑜𝑠𝑠𝑖𝑏𝑙𝑒 𝑓𝑎𝑢𝑙𝑡 𝑙𝑜𝑐𝑎𝑡𝑖𝑜𝑛𝑠 𝑖𝑛 𝑎 𝑐𝑖𝑟𝑐𝑢𝑖𝑡
𝑇𝑜𝑡𝑎𝑙 𝑝𝑜𝑠𝑠𝑖𝑏𝑖𝑙𝑖𝑡𝑖𝑒𝑠 𝑖𝑠 3 𝑁 𝑎𝑠 𝑎 𝑙𝑖𝑛𝑒 𝑏𝑒 𝑏𝑒 𝑠𝑎0 , 𝑠𝑎1 𝑜𝑟 𝑔𝑜𝑜𝑑
𝑂𝑛𝑒 𝑝𝑜𝑠𝑠𝑖𝑏𝑖𝑙𝑖𝑡𝑦 𝑜𝑓 𝑐𝑖𝑟𝑐𝑢𝑖𝑡 𝑏𝑒𝑖𝑛𝑔 𝑔𝑜𝑜𝑑
2𝑁 𝑝𝑜𝑠𝑠𝑖𝑏𝑖𝑙𝑖𝑡𝑖𝑒𝑠 of single fault Possibilities of multiple fault 3𝑁- 1- 2N
MSF- Multiple Stuck-at faults not considered in practice

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What should be the test vector ? 011 SA1 is Masking SA0

What should be the test vector ? 010 detects the MSF {c SA0, a SA1}

➢ Improper masking or etching

➢ Loose or excess bare wires

➢ Defective printed circuit boards

➢ Shorting of pins of a chip
Test Vectors for Input and Output Stuck-at Faults cover Input-to-Output Shorts

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Bridging faults

Test Vectors for Input and Output Stuck-at Faults cover Input-to-Output Shorts

Short is Modeled as Low Resistance

If F,G = 0,0 can be detected as F s-a-0

If F,G = 1,1 can be detected as G s-a-1
High Resistance Bridges do not affect the logic value, and hence are undetectable by a static
logic test.
Different Models Need Different Patterns

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Delay faults

Slow to rise (STR), slow to fall Transition (STF), faults due to Vt Variation, Doing Variation,
Improper contacts etc Slow to rise, slow to fall
No fault detected at static and low frequency operation but glitches can be there at high
operating frequencies and cause errors in sequential circuits
Delay Faults requires two test vectors

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Can be modelled a RC delay but can be because of poor MOSFET being fabricated or nay other
fab defects.

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Experimental Results

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Transition Faults: Assumes large delay defect concentrated at one logical node, such that any
signal transition passing through this node will be delayed past the clock period.
Path Faults : Assumes a distributed delay along a combinational path from latch to latch. z A
new delay fault model(Heragu and Patel 1996)
Segment Delay Fault Model : Assumes distributed delay along a small segment of a long path.

Transition Delay Fault Model

Slow-to-rise (0 to 1) transition on line k

A two-pattern sequence is a test for slow to-rise fault on line k if
V1 sets line k to 0
V2 tests line k stuck-at-0 z
Slow-to-fall (1 to 0) transition
A two-pattern sequence <V1, V2> is a test for slow-to-fall fault on line k if
V1 sets line k to 1
V2 tests line k stuck-at-1
Advantages:
May detect delay defects like shorts, coupling defects, opens etc. missed by stuck-at-tests
Practically Very Useful
Stuck-at-fault CAD tools with minor modifications
Fault lists, Coverage Metrics similar to stuck-faults
Disadvantages:
May miss distributed and small delay defects
Smaller cycle times imply more sensitivity to small delay defects
Intel: more high resistance bridges in 0.18u as compared to 0.25u [ITC ’99]

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IBM: more small delay defects than large [ITC ‘00]

Transition Fault Test

A large delay defect on line A will be detected at pin C if delay on path A-C exceeds
specifications
A small delay defect on line A may not make delay of path A-C large enough to be detected. It
should be tested through long path A-D to be detected.
Path Delay Fault Model
A path is a sequence of connected gates from a circuit primary input to a primary output
A path delay fault is said to have occurred if the delay of a path is more than the specified clock
period of the circuit
Features:
Models distributed delay defects
Path delay fault tests are more likely to detect small delay defects
Much more complex than transition delay model
Low fault coverage
Fault Equivalence and Fault Location
• Two faults f and g are considered functionally equivalent iff Zf(x) = Zg(x).
o There is no test that can distinguish between f and g. i.e. , all tests that detect f
and g, T f and T g, are such that:

• Functional equivalence partitions the set of all faults into functional equivalence
classes, from each of which only one fault needs to be considered.

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• This property is useful for test generation programs.

o Fault equivalence reduces the size of the fault list.
Fault Equivalence and Fault Location
• Any n-input gate has 2(n+1) SA faults.
o For the NAND gate, the SA0 on the inputs are equivalent to SA1 on the output
and all three are detected by the same test pattern AB =( 11 ).

• For any n-input gate with n>1, only n+2 single SA faults need to be considered.

• Fault equivalence is important for fault location analysis as well.

o A complete location test set can diagnose a fault to within a functional
equivalence class.

o This represents the maximal diagnostic resolution achievable by edge-pin

testing.
o Note that for large circuits, complete detection or location test sets are
generally not used, and therefore, maximum resolution is not achievable.

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Equivalence Fault Collapsing

• Equivalence fault collapsing is performed in a level-by-level pass from inputs to
output using local (gate level) fault equivalences.

• Reduction is between 50-60% and is larger, in general, for fanout free circuits.
Equivalence Fault Collapsing
• Notice that structural equivalence is confined to fanout free regions.

• A SAx stem fault is not functionally equivalent with a SAx fault on any of its
branches.
o For example, open defects (as shown earlier) can cause faults to show up on
only the branch.

• However, reconvergent fanout may create structurally equivalent faults in different

fanout free regions.
o See next example.
• Our method of equivalence fault collapsing will not identify faults b SA0 and f SA0
as structurally equivalent.

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• Therefore, the structural equivalence class derived are not maximal.

o Faults from this type of structural equivalence and from the general class of
functional equivalence are not identified.
• The benefit of identifying these additional fault equivalences is not worth the effort,
however.
• See text for ISCAS'85 benchmark circuit results.

Functional vs. Structural Equivalence

• The general process of determining if two arbitrary faults are functionally equivalent
is NP-complete.

• Our methods determine equivalent faults that are structurally related.

o We outlined a process in the context of redundancy earlier (it was applied in
the example shown above).
o Remove the stuck lines and gates and compare the circuits.

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• Structural equivalence implies functional equivalence but the converse is NOT true.
• Structural equivalence analysis is local, functional is global.

Fault Dominance
• If fault detection is the objective (not diagnosis), then fault dominance can be used to
further reduce the fault list.

• A fault f dominates another fault g if the set of all tests that detect g, T g , is a subset of
the test set of Tf.

• Therefore, any test that detects g will also detect f.

• Since g implies f, it is sufficient to include g in the fault list.

• For example, the SA1 test (g) for input A of the NAND gate also detects SA0 (f) on the
output (the same is true for input B .)
o Therefore, Z-SA0 can be dropped from the list.

• It is possible to have to faults f and g such that any test that detects g also detects f,
withOUT f dominating g.

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• The test set Tg consists only of xy = 10.

o But f does not dominate g since the faulty circuits are NOT functionally
equivalent under Tg.
o Although f does not need to be considered, it is difficult to determine this from
an analysis of the circuit.
• For sequential circuits, it should be noted that equivalence fault-collapsing techniques
are valid but dominance fault-collapsing techniques are NOT.

• For larger input gates.

• Dominance fault collapsing is performed from outputs to inputs.

• Here, the x indicates the collapsing of the fault via dominance.

o We can also, optionally, choose to move the output fault preserved in the
equivalence fault collapsing to an arbitrary input.

• One such fault list may be: { A/0 , A/1 , B/1 , C/0 , C/1 , D/0 , E/1 }
• Or another may be: { B/0 , A/1 , B/1 , C/0 , D/1 , D/0 , E/1 }

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Fault Dominance (Example)

Checkpoint Faults (Crosspoint Faults)

• Note that these lists contains only faults on the Primary Inputs (PIs)
o Any test set that detects all SSFs on the PIs of a fanout free combinational
circuit C detects all SSFs in C.

• What happens in the presence of fanout?

• SAB = ( 010 ) detects C SA1, SAB = ( 001 ) detects D SA1 => both detect S SA1.
• SAB = ( 110 ) detects C SA0, SAB = ( 101 ) detects D SA0 => b oth detect S SA0.
o Therefore, SA faults on stem dominate SA faults on the fanout branches.

• More generally, any test set that detects all SSF on the PIs and fanout branches of C
detects all SSF in C.
o The PIs and fanout branches are called checkpoints.
Checkpoint Faults
• Therefore, it is sufficient to target faults only at the checkpoints.
• Structural equivalence and dominance relations can then be used to further collapse
the list of faults.

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• For example, this circuit has 24 SSFs.

o But it only has 14 checkpoint faults (the 5 PIs) + g and h.

• This leaves 10 faults from the original list of 14 checkpoint faults.

Checkpoint Faults
• Example from the text.

• A test generation strategy that targets checkpoint faults is valid only

for irredundant circuits.
o In redundant circuits, some checkpoint faults are undetectable.

• Test sets that detect all checkpoint faults are not guaranteed to detect all detectable
SSFs.
o Additional patterns may be required to obtain a complete detection test set.
Fanout and Equivalence and Dominance
• Neither equivalence nor dominance relations exist between a stem SAx and an
individual fanout branch SAx.

• Detection of a stem fault but failure to detect the fanout branch fault.

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Fanout and Equivalence and Dominance

• Detection of the fanout branch fault but failure to detect the stem fault.

Fault Equivalence
Definition: If Ta is the set of ALL TVs which Detect Fault a, and Tb is the set of ALL Test
Vectorss which Detect some other Fault b; the Two Faults a, and b are said to be Equivalent
Equivalent IF Ta = Tb .
In Other Words, Two Faults are Equivalent Equivalent IF any test detecting one, also detects
the Other and vice versa

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Fault Equivalence (Example)

3-Input AND Gate • Faults ( A/0 , B/0, C/0, F/1 ) are All Detectable by the single Test Vector
( t = 111/0 ) → All 4 Faults Are Equivalent
Equivalence Rules

Fault Equivalence Indicated by Blue or Violet lines with Two-Way Arrows

Equivalence Rules

Single Faults at the STEM and Fanout Nodes are not equivalent

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Equivalence Example

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