4.

A computer system has a logical address space composed of 128

segments. Each segment can contain up to 32 pages, and each page
holds 4K (4096) words. The physical memory has 4K blocks, each block
also holding 4K words. Formulate the logical and physical address
formats. [5]
Each chip = 1024 × 1 bit = 128 bytes (since 1 byte = 8 bits, and 1024 bits
÷ 8 = 128 bytes) i. Logical Address Format

To get 1024 bytes => 1024 ÷ 128 = 8 chips We are given:

Segments = 128
These 8 chips must work in parallel, each providing 1 bit to form a Pages per segment = 32
complete 8 - bit data word. number
Words per page = 4K = 2¹² Need 12 bits for word offset
All chips receive the same 10 address lines
to access 1024 locations. Total logical address format:
Each chip stores 1 bit per location, so 8 chips give 1 byte per
location. Segment: 7 bits
Page: 5 bits
b) How many chips are required to build a memory of 16 KB? Explain Offset (within page): 12 bits
how these chips are connected to the address bus.
Logical Address = [Segment (7) | Page (5) | Word Offset (12)]
Each chip = 1024 × 1 bit = 128 bytes
Total = 7 + 5 + 12 = 24 bits
To get 16,384 bytes :

16,384 ÷ 128 = 128 chips ii. Physical Address Format

To organize : We are given :
Physical memory has 4K blocks log (4K) = 12 bits for block
Group the 128 chips into 16 groups, each group having 8 chips (to
number
form 1 byte per address).
Each block has 4K words log (4K) = 12 bits for word offset
These 16 groups will be selected one at a time using 4 address
to 16 decoder. Physical Address = [Block Number (12) | Word Offset (12)]
Connection Summary : Total = 12 + 12 = 24 bits

b. Simpler recovery: In case of power failure, no dirty data is lost as Lower 10 address lines go to all chips (to access 1024 rows).
memory is already updated. Next 4 address lines go to the decoder for chip group selection.
c. Simpler cache design: No need for dirty bits or complex tracking logic. Within each group, 8 chips provide 8 bits = 1 byte of data per
address.

5. If given a choice between increasing the number of memory banks or 9.

implementing memory interleaving, which approach would be more
effective in improving memory access speed? [5]
00 for RAM, 01 for
Memory interleaving would be more effective than just increasing the
ROM, 10 for interface registers.
number of memory banks.
A. How many RAM and ROM chips are needed?
Interleaving allows parallel access to multiple memory blocks, B. Draw a memory - address map for the system.
reducing access time. C. Give the address range (in hexadecimal) for RAM, ROM, and
interface.
It improves throughput by starting the next memory access while the
previous one is still completing. A. RAM chip = 256 bytes
ROM chip = 1024 bytes
Just increasing banks without interleaving can cause bottlenecks if
access patterns are not optimized. System requirements:
RAM needed = 2K bytes = 2048 bytes
Interleaving makes better use of available memory banks, maximizing 2048 ÷ 256 = 8 RAM chips
performance.
ROM needed = 4K bytes = 4096 bytes
It is a scalable solution for faster memory operations in high-speed
4096 ÷ 1024 = 4 ROM chips
systems.

B. Since 2 highest bits decide the section :

Section
00XXXXXXXXXXXX RAM (2K bytes)
01XXXXXXXXXXXX ROM (4K bytes)
10XXXXXXXXXXXX Interface (Registers)

C. RAM (00) :
Starts from 0000H to 07FFH
(2K bytes = 2048 locations = 0x0000 to 0x07FF)
ROM (01) :
Starts from 0800H to 17FFH
(4K bytes = 4096 locations = 0x0800 to 0x17FF)
Interface (10) :
Starts from 1800H onwards (for the interface registers)
 10. A virtual memory system has : B. LRU (Least Recently Used) 11. Assume there are three small caches, each consisting of four one - word
Address space = 8K words, Replace the least recently used page. blocks. One cache is fully associative, a second is two - way set -
Physical memory space = 4K words, associative, and the third is direct - mapped. Find the number of misses
Page size = 1K words. Step Reference Memory Status for each cache organization given the following sequence of block
addresses: 0, 8, 0, 6, and 8. [5]
The following page reference changes occur during a time interval :
1 4 4---
420126140102357 A. Fully Associative Cache :
2 2 42--
(Each change is listed once even if referenced again.) Any block can go anywhere.
3 0 420- Cache initially empty.
Determine the four pages that are resident in main memory after each
page reference change using : Access Result Cache Content
4 1 4201
A. FIFO page replacement 0 Miss 0---
5 2 4 2 0 1 (hit, update usage) 8 Miss 08--
B. LRU page replacement.
0 Hit 08--
6 6 6 2 0 1 (replace 4, least used) 8 Miss 086-
6 Hit 086-
A. FIFO (First In First Out) 7 1 6 2 0 1 (hit, update usage)
Start with an empty memory. Misses = 3
Replace the oldest page when a new page needs to be loaded. 8 4 4 2 0 1 (replace 6, least used)
B. Two - Way Set Associative Cache :
Step Reference Memory Status 9 0 4 2 0 1 (hit, update usage) 2 sets, each with 2 blocks (because 4 blocks total, 2 blocks per set).
1 4 4---
Block address modulus 2 = set number (Set 0 or Set 1).
2 2 42-- 10 1 4 2 0 1 (hit, update usage)
3 0 420- Block Set (block mod 2) Result Set Content
11 0 4 2 0 1 (hit, update usage)
4 1 4201
0 0 Miss Set0 : 0 -
5 2 4 2 0 1 (hit, no change) 12 2 4 2 0 1 (hit, update usage)
6 6 6 2 0 1 (replace 4) 8 0 Miss Set0 : 0 8
13 3 3 2 0 1 (replace 4, least used)
7 1 6 2 0 1 (hit, no change)
0 0 Hit Set0 : 0 8
8 4 6 4 0 1 (replace 2) 14 5 5 2 0 1 (replace 3, least used)
9 0 6 4 0 1 (hit, no change) 8 0 Miss Set0 : 8 6
10 1 6 4 0 1 (hit, no change) 15 7 7 2 0 1 (replace 5, least used) (replace 0)
11 0 6 4 0 1 (hit, no change) 6 0 Hit Set0 : 8 6
12 2 2 4 0 1 (replace 6)
13 3 2 3 0 1 (replace 4) Misses = 3
14 5 2 3 5 1 (replace 0)
15 7 2 3 5 7 (replace 1)

13.

Block address modulus 4 = cache line.