SL74HC174

Hex D Flip-Flop with

Common Clock and Reset
High-Performance Silicon-Gate CMOS

The SL74HC174 is identical in pinout to the LS/ALS174. The device

inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of six D flip-flops with common Clock and
Reset inputs. Each flip-flop is loaded with a low-to-high transition of
the Clock input. Reset is asynchronous and active-low.
ORDERING INFORMATION
• Outputs Directly Interface to CMOS, NMOS, and TTL
SL74HC174N Plastic
• Operating Voltage Range: 2.0 to 6.0 V
SL74HC174D SOIC
• Low Input Current: 1.0 µA
TA = -55° to 125° C for all packages
• High Noise Immunity Characteristic of CMOS Devices

PIN ASSIGNMENT

LOGIC DIAGRAM

FUNCTION TABLE
Inputs Output

Reset Clock D Q

L X X L

PIN 16=VCC H H H
PIN 8 = GND
H L L

H L X no change

H X no change

X = Don’t care

System Logic
SLS Semiconductor
SL74HC174

MAXIMUM RATINGS *

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±20 mA
IOUT DC Output Current, per Pin ±25 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PD Power Dissipation in Still Air, Plastic DIP+ 750 mW
SOIC Package+ 500
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds 260 °C
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TA Operating Temperature, All Package Types -55 +125 °C
tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V 0 1000 ns
VCC =4.5 V 0 500
VCC =6.0 V 0 400

This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.

System Logic
SLS Semiconductor
 SL74HC174

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C ≤85 ≤125 Unit
to °C °C
-55°C
VIH Minimum High-Level VOUT=0.1 V or VCC-0.1 V 2.0 1.5 1.5 1.5 V
Input Vo ltage IOUT≤ 20 µA 4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
VIL Maximum Low -Level VOUT=0.1 V or VCC-0.1 V 2.0 0.5 0.5 0.5 V
Input Voltage IOUT ≤ 20 µA 4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
VOH Minimum High-Level VIN=VIH or VIL 2.0 1.9 1.9 1.9 V
Output Voltage IOUT ≤ 20 µA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
VIN=VIH or VIL
IOUT ≤ 4.0 mA 4.5 3.98 3.84 3.7
IOUT ≤ 5.2 mA 6.0 5.48 5.34 5.2
VOL Maximum Low-Level VIN= VIL or VIH 2.0 0.1 0.1 0.1 V
Output Voltage IOUT ≤ 20 µA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
VIN= VIL or VIH
IOUT ≤ 4.0 mA 4.5 0.26 0.33 0.4
IOUT ≤ 5.2 mA 6.0 0.26 0.33 0.4
IIN Maximum Input VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
Leakage Current
ICC Maximum Quiescent VIN=VCC or GND 6.0 4.0 40 160 µA
Supply Current IOUT=0µA
(per Package)
NOTE: Total Supply Current = ICC +Σ ∆ICC

System Logic
SLS Semiconductor
SL74HC174

AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns)

VCC Guaranteed Limit
Symbol Parameter V 25 °C to ≤85°C ≤125°C Unit
-55°C
fmax Maximum Clock Frequency (50% Duty Cycle) 2.0 6.0 4.8 4.0 MHz
(Figures 1 and 4) 4.5 30 24 20
6.0 35 28 24
tPLH, t PHL Maximum Propagation Delay, Clock to Q (Figures 2.0 110 140 165 ns
1 and 4) 4.5 22 28 33
6.0 19 24 28
tPHL Maximum Propagation Delay , Reset to Q 2.0 110 140 160 ns
(Figures 2 and 4) 4.5 21 28 32
6.0 19 24 27
tTLH, t THL Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
(Figures 1 and 4) 4.5 15 19 22
6.0 13 16 19
CIN Maximum Input Capacitance - 10 10 10 pF

Power Dissipation Capacitance (Per Enabled Typical @25°C,VCC=5.0 V

Output)
CPD Used to determine the no-load dynamic power 62 pF
consumption: PD=CPDVCC2f+ICCVCC

TIMING REQUIREMENTS (CL=50pF,Input t r=t f=6.0 ns)

VCC Guaranteed Limit
Symbol Parameter V 25 °C to ≤85°C ≤125°C Unit
-55°C
tSU Minimum Setup Time, Data to 2.0 50 65 75 ns
Clock (Figure 3) 4.5 10 13 15
6.0 9 11 13
th Minimum Hold Time, Clock to 2.0 5 5 5 ns
Data (Figure 3) 4.5 5 5 5
6.0 5 5 5
trec Minimum Recovery Time, 2.0 5 5 5 ns
Reset Inactive to Clock (Figure 4.5 5 5 5
2) 6.0 5 5 5
tw Minimum Pulse Width, Clock 2.0 75 95 110 ns
(Figure 1) 4.5 15 19 22
6.0 13 16 19
tw Minimum Pulse Width, Reset 2.0 75 95 110 ns
(Figure 2) 4.5 15 19 22
6.0 13 16 19
tr, tf Maximum Input Rise and Fall 2.0 1000 1000 1000 ns
Times (Figure 1) 4.5 500 500 500
6.0 400 400 400

System Logic
SLS Semiconductor
 SL74HC174

Figure 1. Switching Waveforms Figure 2. Switching Waveforms

Figure 3. Switching Waveforms Figure 4. Test Circuit

EXPANDED LOGIC DIAGRAM

System Logic
SLS Semiconductor