HElJLm PACKARD Basically, a switch lIlarker will be an external procedure

l1larker with STATUSB added; an interrupt l1larker is then a

COMPUTER SYSTEMS - 19447 Pruneridge Ave. CUpertino CA 95014 SlIJitch l1larker with XO-X15' and BO-B5 added.
An additional bit in the TCB, called RSYIP (return-switch
in progress) will keep the IEXIT logic straight.
----------------------------------------------------------------------- UpdatedACD pages are provided.
Frol1l: Bert Speelpenning X413~ Date: February 8, 1983 b) switch entry point
To: Dick Anderson Subject: VISION architecture A dedicated object in group zero (see under 11) will
Alan Christensen status (CPU) provide the'entry point for the switch software in
Shane Dickey native lIlode. The SlIJitch operation is no longer regarded
Bob Erickson as a trap. I t will have no paraJlleters.
Bob Frankenberg This will sav~ 'SOl1le execution time at the expense of
Bill Gimple SCll1le replicated code.
Larry Goldman (IND)
Rich HaJIIl1lons (TCG)
Carson Kan 2. Nil~:blect spec if i.cat ions
Leon Leong (I NO )
Jil1l Nissen The Nil' object is further defined (relative to the ACD"version 5)
Ed Olander to guarantee that all implelllentations ca~se consistent traps ,to
Elik Porat occur :,rhen atte!1lpting to access lIlel1lory through the nil pointer.
Howard S!1li th The full statel1lent is that operating syste!1l software shall set
Ken Spalding the OD of object zero in group zero to values that correspond to
an object type of data, access rUhts R31d3, a lower bound of 1
Cc: Alan Hewer and an upper bound of O.:Tht vi;.tual object nUl1lber of the nil
Jil1l Miller object shall also be fixed ~~z~lb.
Dave Salol1laki
3. SIT trap
An updated description of the HP3000 l1lode 'of the Vision architecture The SIT trap (DBSIT) will report the pointer to the next
has now been released, through the efforts of Terry Jackson. instruction as its paraJII~.ter rather than the previous instruction
For questions or cOl1ll1lents pleaSe refer to Terry.
j
address. The obvious ,hardware implel1lentation for SIT uses similar
logic -'lS for external. interrupts and it is unnecessarily expensive
The following issues have been resolved, cl~rified or addressed for hardwaret.o hang on to the previous instruction counter.
,sinu~ the pre'"ious Vision CPU architecture l1lel1lo. Ide don' texpect thiS. to create any diff,~'(;ulty for f<1oftware.

4, AcceSS rights checking

1. Mode SlIJitch
Both VCF60 and VCF50 teaJlls have requested reconsideration of
Ide have identified several ways to shave til'le frolll~the lIlode SlIJitch certain aspects of the access rights checking rules.
operations between Vision lIlode and HP300Q Plode. This is clearly
il1lportant for the perforl1lance of HPE. ' a) write access to iIIlply read access
a) switCh Aarker Hardware silllpll-tications accrue (and redesign can be
avoided) if write access to a data object always iIIlplies
SlIIitching lIIodes is not a truly asynchronO\lSevent like read access. The access right fields in an Object
an external interrupt;":' This allotas us to get by with Il(-lscriptor ,keep their original l1leaning; we plan to lIIerely
saving only a subset'df the register values" undQr software "add a state.lllent that operating systel1l softlJlare shall
qontrol. this l1leans that fewer pushes and pops are , "nat ~reateobjects that have write access without also
requHed to do the l1lode SlIJitch. ' In order to accol1lp'lish granti~ the\ll, read access.
this we need to distinguish between a SlIJitch l1larker and
a full blown interrupt l1larker. Ide also need to give lEXIT
the lIleans to distinguish between the two lIlarkers.

\
 b) read access to the current code object For this to really work, we need to extend the notion of overlap
to cover the case exel'lplified by MOVE8 [B5+X6], X6.
The ACD roakes a distinction bet~een read access to the If MOVE8 encounters a page fault at [B5+X6+1] , the value of X6
current code object and read access to the saroe object roay already have been l'Iodified to the value at [B5+X6].
~hen it does not happen to be the current code object. To avoid this, the definition of "overlap" l'Iust incorporate the
It does this by stating that read access to the current cOl'lponents of an address calculation for the source operands.
code object is al~ays granted regardless of the contents
of the Obj'ect Descriptor for the, code object.
7. Code object size
,Currently, this ca'n be iropleroe~ted on the VCF60 and the
, VCF50, only by, doing extra ~ork in CALLX and EXIT, ~hich A Vision mode code object is limited in size to 2~24 bytes.
',will slo~, these il'lpprtant instructions do~n. . This is not currently stated explicitly in the ACO but could be
l.Jetherefore feel that very strong reasons are needed asSUl'\ed froro the forroat of the external procedure l'Iarker.
to retain this exceptional treatl'lent of the current code We no~ l'Iake this assuroption explicit.
object in the Vision architecture. If you feel you have
such strong reasons, ~e would like to hear them by Feb 15.
On the HP3000, P-relative addressing of data is a basic 8. OST and CST descriptors
addressing roode and the only one available to offer
protection to third-party soft~are. On Vision, no l.Je will extend the MOVEfSP8 instruction to allow software to
perforl'lance benefits derive from keeping data in your get access to the current values of the CST and OST descriptors.
code segroent rather than in soroe data segroent, and third-
party software can be protected by separate privilege
level and by exploiting the group structure. 9; Bounds checking on variable length instructions
Some instructions such as MaVEC and CMPC involve a sequence of
5. Interruptible instructions byte operations over a length given in the instruction.
The way bounds checking is perforl'led optil'lally in such an
Questions have been raised regarding the expected behavior when instruction depends on the organization of the hardware. On the
an interruptible instruction is resul'led and finds that its data VCF60, bounds checking is performed in parallel with an actual
on the stack has been corrupted. In particular, ~hat should access. On the VCF50, bounds checking is done explicitly in
happen when the lIP bit is set but the word popped frol'l the stack microcode As a consequence, on the VCF60 it is fastest to start up
(which represents how roany til'les around the loop have already the loop of MOVEC or CMPC and trap out when the end of the object
been performed) is found to be negative? is reached before the loop counter is exhausted. In contrast, on
The expected behavior in this and siroilar cases is allowed to be the VCF50 it is fastest to check whether both first and last byte
il'lplementation dependent, as long as the "damage" does not extend are within bounds and not do any bounds checking for interl'lediate
to another task. For exarople, it is acceptable to iml'lediately bytes once the loop starts.
continue to the next instruction when this happensj it is not The issue then arises when and how a bounds violation roust be
acceptable to hang in an infinite microcode loop. reported and how much of the instruction should be preSU!1led to
have been cOl'lpleted when this occurs.
l.Je have decided that hardware should be left free to choose the
6. "Overlap" sequence that is optil'lal for it. The definition for MOVEC ~ill
no~ state that if MOVEC cannot be completed due to a bounds violation,
The notion of overlap between source and destination of an the effect of MOVEC is that a contiguous but unspecified nUl'lber of
instruction needs soroe revision to get' around,sol'le nasty bytes has been l'Ioved, all ~ithin the object's bounds.
roicrocode iroplications. An instruction such as A siroilar l'Iodification ~ill serve for CMPC.
MOVE8 source, destination
10. Pagecfault trap
is only guaranteed to obtain the expected result when the
destination does not "overlap" the source. This is to allo~ The pararoeters for the page fault trap are currently listed as
hardware to do the roove in either one 64-bit gulp or two, 32-bit including an 8-byte Virtual Page Nurober (left justified) and
gulp or (probably incase of misaligroents) insomenul'lber of odd- a 4-byte.;P~ge" Offset (right justified).
sized gulps, and yet be able to recover from a page fault in l.Je have collapsed these no~ to a single a-byte Virtual Address.
the l'Iiddle of the l'Iove. The exclusion of overlap roakes it
permissible to restart the instruction even if the destination
had been partially l'Iodified.
11. Architecturally fixed object numbers 14. "MENSAC" instructions
We have received a request fro~ HPE-I to dedicate certain objects We have decided in principle to adopt the ~e~ory diagnostic
in group zero for certain uses and to fix these objects capabilities proposed by Jim Yichelroan and Ji~ Chiochios.
architecturally. In the version 5 ACD, four objects are fixed by We are in the process of refining all the encodings to assist
their logical address (the NIL object, trap code object, channel the hardware in iropleroenting these.
interrupt code object and processor interrupt code object) and The latest iteration is reflected in a roemo by Brian Button
four are fixed by their virtual address (SYSCOM area, hasn table, dated Feb 1.
page directory and PME). We have been asked to extend this list
and also to J1Iove the logical object nu~bers for trap code object,
etc. downward so that SYSCOM area, etc. can be given a logical 15. STATUSC'and STATUSD
object number that is the same as its virtual object number.
The current definition of STATUSC and STATUSD is based on the
We believe that the only object nUJ1lbers (logical or virtual) that difference in behavior of changes in status in a shared-~eJ1lory
need to be fixed architecturally are those that ~ust be known to J1Iultiprocessor syste~. Ite~s in STATUSC, when changed, do not
both software and roicrocode. Any other object numbers can be fixed affect any other processor in the systeJ1l; whereas changes to
by software convention, not "architectural mandate. STATUSO must be propagated to all other processors in the shared-
We are willing to move the logical object,nuro~ers for trap code memory ulultiprocessor syste~.
object, etc. downward in order to make it possible for HPE-I to
implement the sche~e they proposed as a software convention. We are currently investigating whether the responsibility'for
The revised numbering is shown below. More object numbers will notifying other processors can be relegated to syste~ software;
be fixed only after it has been demonstrated that both software this would J1Iake the multiprocessor imple~entation potentially
and hardware (microcode) are affected. simpler, faster and more reliable.
Until this investigation is cOJ1lplete, we will hold off on other
logical address changes to STATUSC and STATUSD that have been proposed, such as
reJ1loving the J1Iode bit froJ1l STATUSC.
NIL object
trap object
group
group
0,
0,
object
object
°10 It is quite possible that the eventual result will be to ~ove all
items of STATUSC and STATU SO into the SYSCOM area.
channel interrupt object group 0, object 11
processor interrupt object group 0, object 12
switch handler (nm) object group 0, object 13 16. PROBE and BPROBE.
PROBE is intended for use by systeJ1l intrinsics to allow theJ1l to
test whether the caller has passed a legal address (range) to the
12. Deci~al instructions intrinsic.
Jim Miller has made a proposal, with Alan Hewer, for a change
We have decided to allow conversions fro~ 54-bit integers to in the definition of PROBE and for a new variant (BPROBE) of
both 8-byte deci~al and 16-byte deci~al and vice versa. PROBE that takes the address to be probed from a base register
All these instructions will be ~oved to the CONVERT escape rather than fro~ ~e~ory. The change in PROBE closes a protection
group. hole having to do with the fact that the value of S in the
We have also decided to co~bine the ZEXT3 and TRUNC3 instructions environment of the procedure doing the PROBE is larger than the
of the previous status me~o into a single MOVE3 instruction. value of S that applied in the environment of the caller.
We will include a fuller description of these later. The variant BPROBE would help ~ake passing address par~eters
An updated opcode chart, though still tentative, is included. in base registers ~ore,effective.
Updated ACO pages for these two instructions are provided.
Note that the encodings for "ring" have been changed as well.
13. IEEE floating point
The Proposed Standard fo~ floating point arithooetic has co~e
one i~portant step closer to beco~lng the Standard for floating
point aritrjuletic.
In the latest round of balloting so~e ~all ~end~ents were passed.
We will i,nclude a description of this later. In the Man time,
please consult Bill Ames.
17. CHECKA and CHECKB.
CUrrently, the definition of CHECKA,B includes a special way - all references to "tme of day" should be replaced with "til1le
of treating the operand of the instruction. If the bit CBA of century"
or eBB is not set, the specification prohibits trapping on
an illegal operand. This was done so that mplel1lentations - MOVEtSP4; setting CBA and CBB does not require special privilege.
could il1lplel1lent CHECKA,B without having to do an operand fetch; Privilege level 3 is sufficient.
this could speed up the (frequent) case where CBA,CBB is clear MOVEfSP4; CBA and CBB do not warrant their own selector.
at the expense of the case where the bit is set. Accessing CBA and CBB must now be done using MOVEfSP STATUSB1.
However, it turns out that in l1lany situations the operand fetch
does not slow down execution and the special prohibition on - The breakrange trap does not return the operand responsible for
operand traps incurs a cost smply because it involves a special tripping the breakrange. -rt is up to software to deterl1line what
case. values changed within the breakrange. It is precisely because it
In retrospect, it is therefore clear that CHECKA and CHECKB were is not very feasible for hardware to keep track of the operand
overspecified. A better statel1lent is that CHECKA and CHECKB are responsible that the VISION architecture has a break range for write
not required to trap an operand violation if CBA,CBB are clear. but not for read and not for execute.
section 7.1.2 still l1lentions SI. This is an unintended carry-over
18. Ring level for code running on the ICS frol1l the version 3 ACD. Because of the redefinition of the
dispatcher marker, in version 5 QI and SI are one and the saroe.
We are looking into the possibility of relegating l1l0re code that Hence any reference to SI should be deleted.
l1lust run on the lCS to ring level 1 rather than level O.
This would allow better granularity on protection in systero code. - TCBX is no longer architecturally defined. In version 5 the TCB
It would also allow the trap object to run at level 1. is accessible to software, so a MOVEf/tSP is no longer needed
Changes to IEXIT lJJould be required to allow it to exit into code to manipulate a TCBX pointer. The TCB-extension is a software
that runs at a higher level. concept only.
We hope to have a proposal by next month.
- clarification: MOVEtSP4 task clock enable has no effect when
executed on the ICS.
- corrections and clarifications prove necessary in the definitions
of CALLX, EXIT and POOEL. Updated ACO pages are provided.
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6.1.4 Opcode Assignments 6.2.6.2 CALL target.r4

Procedure call. A procedure ~arker is pushed onto the stack
The following chart shows the association of opcodes with the and control is passed to "target", interpreted as
instruction name (~ne~onic). The 8-bit encoding of the opcode a 32-bit half-word offset relative to the start of
is found by adding the heKadeci~al n~ber in the ro~ of the the CALL instruction. CALL requires the procedure
instruction to the hexadeci~al nu~ber in its colu~n. to be within the current code object.

OPCODE lIP := i-lIP; if IIP=l and PTE=l then Trap"DBCALL";

~
+100

!10 DISABLE
! 18
+!01
NOP
+!02
EXIT
+!03
SEXIT
*ENABLE *INTERRUPT*UNTRY
TESTSTRI P* *QUAD4 *
+!04
TESTA
PSEB
EXTEND
*POP8
+!05
TESTB
PSDB
DELETE
BRX
+!06
TESTOV
DI8P
CHECKA
*
+!07
MrEAU
TRY
CHECKB
*POP16
-- lIP := OJ
S := 8 + 4; {pushes garbage}
PUSH4 P[32 .. 63];
PUSH4 Q[32 .. 63] j
Q := 8j
!20 * *PUSH2 ** * * P := P + target * 2;
!28 PUSH1 PUSH8 TESTDOlJN UP DOlJN PUSH16
. ! 30 POPl POP2 * *
*TEST4F TEST4D TESTREF * TEST16D Traps: STKOVF
138 * TEST2 TEST8 TEST8D TEST8F TEST16F CODEBNDSV
140 AND4 * * MPY4F MPY8 * MPY8F MPY16F DBCALL
!48 NOT4 DIV4
*REM4 NEG4 DIV4F DIV8 *REM8 DIV8F DIV16F
!50 OR4 NEG4F NEGB NEG8F NEG16F
158 XOR4 MOD4 ABS4 ABS4F ABS8 MOD8 ABS8F ABS16F 6.2.6.3 CALLX loi.r4
160 CMP1 CMP2 CMP4 CMP4F CMP8 BCMP8 CMP8F CMP16F
168 MOVE1 MOVE2 MOVE4 * MOVE8 B8ET8 *ADD8F MOVE16 External call. A procedure marker is pushed onto the stack and
170 TESTBIT I8C42 ADD4 ADD4F ADD8 BGET4 ADD16F control is passed to the entry point specified in the
178 * MPY4 SUB4 SUB4F SUB8 B8ET4 SUB8F 8UB16F OD for "loi". "Loi" contains the high 32 bits of a
180 MOVEADR BMOVEADR* * * * * *8L16D logical address into the target object.
188 * * MOVEf8P4 MOVEf8P8 TEST8EMASL4D 8L8D
190 * * MOVEtSP4 MOVEtSP8 MOVE8EMA8R4D SR8D 8R16D
198 CHECKLO CHECKHI DUP OVPUNCH MOVE3 CMP4D CMP8D CMP16D lIP := l-IIP; if IIP=l and PTE=l then Trap"DBCALL"j
lAO L8L4 A8L4 BCMP4 GET8IGN ZEXT2 ADD4D ADD8D ADD16D lIP := OJ
!A8 LSR4 ASR4 BADD4 VALN r - SUB4D SUB8D SUB16D PUSH8 Preturn;
lBO LSL8 ASL8 BSUB4 VALD i" MPY4D MPY8D MPY16D (8-4)[0 .. 2] := STATU8A[0 .. 2];
lB8 LSR8 ASR8 * * i" DIV4D DIV8D DIV16D PUSH4 Q[32 .. 63] j
lCO PROBE BPROBE MOVEBIT MOVEC * * MOVEBLR CMPB Q '= 8'
lC8 DPF ~ REP CMPC * TRANSL MOVEBRL CMPT if'loi'non-existent-object then Trap"CODEODTV";
lDO POLY4F POLY8F POLY16F SCANUNTIL* * * * if 00 (loi) . ITP <> VisionCode then Trap"CODETYPV";
lD8 * * *BRGL *BRNU *PUSH4 VECTOR SYS CONVERT if STATUSA. XL > OD (loi) . PR then Trap"CODERINGV";
@lEO BRG BRGE PUSHADR POP4 BPOP8 STATUSA.XL := OD(loi).KLj
@lE8 BRGU BRNL BRNE BR TESTLSB TESTl TEST4 BTEST8 Ptarget[ 0 .. 31] '= loi;
@!FO BRN BRE BRL BRLE CALL CALLX * BREAK Ptarget[32 .. 63] '= OD(loi).EPlJO * 4;
lF8 BRU BREU BRLU BRNG * * * ERROR P := Ptarget;

Note 1: the rows~arked with "@" contain the instructions that Traps: STKOVF
can be packed two per word. CODEODTV
CODETYPV
Note 2: the instructions VECTOR ,SYS and CONVERT are escapes to CODEBNDSV
a secondary set of opcodes. CODERNGV
DBCALL
6-13 6-47
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6.2.6.5 EXIT
6.2.4.9 SCANUNTIL liroit.r4, charset.ror, string.ror, index.rw4
Exit froro procedure. This instruction can be used to return
froro a procedure called lIJith CALL or CALLX. The Scan string until condition satisfied. The string of characters
procedure roarker located at 0 contains the necessary (bytes) pointed to by "string" is scanned for a character
inforroation to restore the context of the caller. that satisfies a particular condition. Scanning starts
If r.he caller executed in a different code object at the byte index "index" into the string and will not
than the current one, a nUillber of checks are lIlade. go beyond "lilllit". SCANUNTIL sets "index" to the value
of the first byte scanned that satisfies the condition
if such a byte exists; it leaves "index" at the value of
if (0-8)[0] = 1 then begin "lilllit", otherwise. The condition to be satisfied by the
{external exit} character is encoded as a 256-bit bit array (siroilar to a
Pobject := (0-12) [0 .. 31]; Pascal set). Bits found set in the bit array "charset"
Poffset :=.~0-8)[8 .. 31]~.zero-extended; signify that the corresponding character satisfies the
ST_return .- (0-8)[0 .. 7J, condi tion.
if STATUS.XL > ST return.XL then Trap"CODERINGV"; If the logical address of "charset" is lIJithin 32 bytes
if Pobject non-exIstent then Trap"CODEODTV"; of the object's upper bound, an addressing viOlation trap
if OD(Pobjectl. TYPE <> VisionCode then Trap"CODETYPV"; is raised. This instruction lIlust be interruptible.
if ST return.XL > STATUSB.XTL then Trap"INSXTL";
end -
else begin MOVEADR string, Stj
{internal exit} if lIP = 0 then C .= index
Pobject := P[0 •. 31]; else POP4 C;
Poffset := (0-8)[0 .. 31]; lIP '= o·
ST_return := STATUSA; CC :: CCL;
end; Notyetdone := C <= liroit;
o offset := (0-4)[0 .. 31]; while Notyetdone do begin
if 0 offset < 0 or 0 offset> 0[32 .. 63] - 12 Char := (St + C ) [0 .. 7]; {zero-extend}
then-Trap"STKCONSISTV" ; TESTBIT Char, charset;
if Poffset[31] = 1 and {iNpleroentation choice} if CC = CCG then begin
then Trap" INSODDP" ; Notyetdone := false;
Poffset[31] '= 0; index : = C;
8[32 .. 63] '= 0[32 .. 63] - 12; end
0[32 .. 63] '= O_offset; else begin
P[0 .. 31] '= Pobject; C := C + 1;
P[32 .. 63] Poffset; Notyetdone := C <= lilllit;
STATUSA '= ST_return; {SIT and DBP bits not to take { if iropleroentation chooses to acknollJledge
effect until next instruction} an external interrupt here, then
PUSH4 C; set lIP := 1; Notyetdone := false;
end;
Status: restored froro roarker on external exit end;
Traps: INSXTL
CODEODTV
CODERINGV
CODETYPV Status: CC
STKCONSISTV Traps: AddressingV
CODEBNDSV
INSODDP

6-49 6-40
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6.2.8.4 PDDEL ppn.r4 6.2.6.10 CHECKA parameter.r4

Delete from PDIR. The Physical Page Descriptor PPD for the Conditional break. If the "CBA" enable bit is set, a trap is
physical page with physical page nUl'lber "ppn" is taken. The value of "parMeter" is passed to the trap
removed from its hash chain. handler. It is permissible for hardware to not trap on
Ring 0 privilege is required. an illegal operand if CBA is clear.
Searchpa := PDIR.PA + 16 * ppn + 12;
VPN := (PDIR.PA + 16 * ppn + 4)~51]j if STATUSB.CBA 1 then Trap"DBCHECKA"j
Linkpa := HASH.PA + 4 * hash( VPN );
repeat Traps: DBCHECKA
Oldlinkpa := Linkpaj
if (Linkpa)[0 .. 31] = 0 then Trap"ADRPDIR"j
Linkpa := (Linkpa) [0 .. 31] + 12j
until Linkpa = Searchpa; 6.2.6.11 CHECKB pararoeter.r4
(Oldlinkpa) [0 .. 31] := (Searchpa) [0 .. 31]j
Conditonal break. If the "CBB" enable bit is set, a trap is
Notes: (consult carefully when implementing a VISION machine taken. The value of "parameter" is passed to the trap
capable of running as a shared-memory multi-processor) handler. It is permissible for hardware to not trap on
an illegal operand if CBB is clear.
1) Address translation aids (TLB) must be synchronized (by
hardware) with the state of the PDIR/HASH before hardware
may execute the instruction following PDDEL. if STATUSB.CBB 1 then Trap"DBCHECKB"j

2) In a shared-memory multi-processor system, implementations Traps: DBCHECKB

must guarantee that read-write operands never fault on the
write. The burden for ensuring this can be placed entirely
on the implementation of PDDEL. This requires PDDEL to
complete a handshake with all processors in the system 6.2.6.12 CHECKLO source.r4, lobound.r4
before the instruction following PDDEL executes.
Check lower bound. If "source" is less than "lobound", a
3) Various functions compete for access to hash bucket and PPDs bounds check trap occurs. The comparison is a two's
and these functions must be carefully synchronized by complement 32-bit compare.
hardware. These functions are: address translationj writing
dirty/reference bits; PDINS; TESTREFj PDDEL.
Each hash bucket and each PPD has a bit for semaphore use by if source < lobound then Trap"INSCHKLO";
hardware. It is sufficient to lock the appropriate hash
bucket for the entire duration of each function. However, Traps: INSCHKLO
doing so might add overhead to writing dirty/reference bits.
The following scheme is also SUfficient: when writing dirty/
reference bits lock only the PPDj when translating addresses
lock hash bucket and each PPD in the chain and unlock each 6.2.6.13 CHECKHI source.r4, hibound.r4
immediately after reading its contents; PDINS locks the hash
bucket; PDDEL locks two consecutive links in the chain Check upper bound. If "source" is greater than "hibound", a
(starting with the hash bucket) and unlocks the first one bounds check trap occurs. The cOl'lparison is a two's
only after it has obtained the lock for the third one. cOl'lplel'lent 32-bit cOl'lpare.
Hardware must unlock all semaphores when a trap occurs.
Traps: ADRPDIR if source > hibound then Trap" I NSCHKHI " j

Traps: INSCHKHI
6-59 6-51
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4.7 Task Control Block

+------------------------+ \
TCB.VA +144 I SC - HP3000 mode I
Hardware needs a certain amount of information in order to +148 I Stack Pointer I
execute the current task. This information is stored in the +------------------------+ > HP3000 mode
Task Control Block (TCB) , located by a register TCB.VA. +152 csrx I information
This TCB.VA register can be thought of as an extension of +156 descriptor I
srATUSC. TCB.VA must be a multiple of 16. The length of the +------------------------+ /
TCB is 176 bytes. Also, the T.CB must be memory resident. +160 I SN - Vision mode \
+164 I Stack Pointer I
A 64-bit register TCB.LA accompanies TCB.VA; operating system +------------------------+ I
software is responsible for ensuring that the logical address +168 I logobjid of VCSA > Vision mode
TCB.LA does in fact translate into the virtual address TCB.VA. +------------------------+ I information
Moreover, the logical address TCB.LA must have a zero group +172 I TRYOFFSET I
selector. Hardware implementations are free to use either +------------------------+ /
TCB.LA or TCB.VA to locate the TCB. +176 I
A task switch is accomplished by Dispatcher software through
simultaneously changing the TCB.VA and TCB.LA registers.
XM execution mode of the task. On IEXIT to this task,
execution mode srATUSA.XM is set to this value.
o 1 2 3 31
/TCB.LA +--+----+-----+----------+ SlJIP switch in progress. Used by IEXIT.
\TCB.VA ==> IXMI ShlIPI RShlIPI reserved I
+--+----+-----+ + RShlIP return switch in progress. Used by IEXIT.
+4 for hardware
+------------------------+ GDi Group Descriptors. The format of a Group Descriptor is
+8 I reserved for system described in section 4.5.
+12 I software
+------------------------+ Task Breakrange Descriptor.
+16 I I This descriptor is described in section 4.9.
+20 I GD1 -- group descriptor I
+24 I for group 1 I SC Logical address of top-of-stack of the HP3000 mode
+28 I I stack used to initialize S on IEXIT.
+------------------------+
+32 I csrx Descriptor.
The descriptor locates the csrx used in HP3000 mode.
Its format is the same as described in section 4.10.
+108 I
+------------------------+ SN Logical address of top-of-stack of the Vision mode
+112 I stack used to initialize s on IEXIT.
+116 GD7 -- group descriptor I
+120 for group 7 I logobjid of VCSA.
+124 I The logical object id of the logical object in use as
+------------------------+ the Vector Context Save Area. See section 4.11.
+128
+132 Task Breakrange TRYOFFSET.
+136 Descriptor The stack offset saved by the TRY instruction.
+140
+------------------------+
+144

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6.2.9.8 IEXIT IEXIT: if STATUSC.ICS = 0 then Trap"INSPRIV";

if Q = QI and not(todispatch) then begin
Interrupt EKit. This is used at co~pletion of an interrupt case_1: {return to task}
handler (either eKternal or internal). A trap occurs STATUSC.ICS := 0; XM:= TCB.XM;
if the instruction is eKecuted other than on the IeS. if XM = 0 then begin
Q ~ust either point to the dispatcher ~arker, a switch {return to Vision ~ode}
~arker or an interrupt ~arker, otherwise results are S := TCB.SN[0 .. 63];
unpredictable. If any of the pages of the Ies are if TCB.SWIP = 0 then RESTORE RETURN(false)
absent, results are unpredictable. If IEXIT returns else begin -
control to a task, the TCB of that task ~ust be resident. TCB.SWIP := 0;
If any pages on the task's stack containing the interrupt BRX switch handler; {object 13}
~arker are absent, or if that stack is in a..§.!g91L9verflow end
co~dition, the appropriate trap is taken which runs as the else begin
botto~ routine on the IeS (at QI). Neither TeB nor the {return to HP3000 ~ode}
task stack object are ~odified in any way. There are 3 S := TCB.SC[0 .. 63];
cases of IEXIT which are sorted as follows: RESTORE_HP3000; \ don't allow
if TCB.SWIP = 0 then 'EXIT 0' / interrupts
Case 1: IEXIT should return control to a task without else P; = "SWITCHC" trap label;
involving the dispatcher. TCB.S1JIP := 0;
This case obtains if Q=QI, while DRF=O or dispatching end
is otherwise disabled. end
else if Q=QI or (todispatch and (Q)[4]=1) then begin
Case 2: lEXlT should run the dispatcher to have it select case_2: {start dispatcher}
a task to LAUNCH. Q := QI; DRF:= 0;
This case obtains if DRF=l (dispatcher request flag), STATUSB := DispatcherStatusBlnit;
dispatching is not disabled, and no interrupt handler EXIT «but leave S at Q» {Q doesn't change}
is pending. Note that it is possible for the dispatcher end
to preeApt itself. else
case_3: {resu~e code running before interrupted}
Case 3: IEXIT should resu~e whatever code was running prior S : = Q + 120;
to the interrupt handler. This Aay be a lower priority RESTORE_RETURN(true);
interrupt handler that was left pending, or the dispatcher.

The IEXIT description uses these uninterruptible sequences: Note 1: i~ple~entations ~ay substitute for the test Q = Q1 the
test (Q-4)[0 .. 31] = QI[32 .. 63].
RESTORE_RETURN(Bregs): begin Note 2: "todispatch" su~~arizes the condition that dispatching
if (TCB.RSWIP = 0) or Bregs then begin is both desired (DRF=l) and possible (DDC=O, IE=l).
BPOP8 B5; .. BPOP8 BO;
POP4 X15; .. POP4 XO;
end- Status: restored froA Aarker
POP8 sTATUSB; TCB.RSW1P·= 0; Traps: INSPRIV
Q := S; EXIT; STKUNF
end STKCONSISTV
SWITCHC
RESTORE_HP3000: begin 'POP2' DeIQ; Q:= S - DeIQ; AddressingV on all base register loads
'POP8' STATUSB; 'POP2' Z.OFFSET;
'POP2' DL.OFFSET; 'POP2' DB. OFFSET;
'POP2' DB.DST;
end
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DO NOT COpy -- HP PRIVATE INFORMATION DO NOT COpy -- HP PRIVATE INFORMATION

10.5.2.3 ShlITCH 10.5.2.4 RShlITCH

The ShlITCH instruction provides a switch of the execution The RShlITCH is the reverse operation to a corresponding SYT
environment of a process from Native mode directly to instruction which occured from Compatibility mode and basically
Compatibility mode. The Native mode stack is capped with a returns execution control back onto the Compatibility mode stack
Switch Stack Marker, the appropriate mode flags changed, and environment. The Native mode stack is flushed to leave the old
control passed to the Compatibility ShlITCH trap routine on the switch stack marker, the process mode flag set to Compatibility
Compatibility mode stack which executes above the previous mode, and a relaunch of the Compatibility mode process occurs.
interrupt stack marker. Any interference, such as Page Faults,
aborts the operation after setting the 'switch in progress' This instruction requires Ring level 1.
flag which then takes effect on the subsequent IEXIT to the
process. if STATUSC.ICS = 1 or STATUSS.IE o
then Trap" INSShlITCH"
This instruction requires Ring level 1. else
begin
if STATUSC.ICS = 1 or STATUSB.IE 0 S := Q+8;
then Trap" I NSShl ITCH " TCB.SN := Sj
else TCB.XM := lj
begin TCS.RShlIP := 1;
PUSH EXTERNAL PROCEDURE MARKER; \ execute_case_l_of_IEXIT;
PUSH8 STATUSS; - / SbJitch Marker end;
TCB.SN := Sj
TCB XM . = l'
TCS : SlJ I P : = 't;
execute_case_l_of_IEXITj
end;

10-15
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DO NOT COPY -- HP PRIVATE INFORMATION DO NOT COPY -- HP PRIVATE INFORMATION

6.2.7 Interaction ~ith Machine State 6.2.7.2 MOVEtSP4 selector.r1, source.r4

Move to special register. This instruction selects a special
6.2.7.1 MOVEfSP4 selector.r1, destination.~4 hard~are register or dedicated ~e~ory location
based on the value of "selector". The value of
Move fro~ special register. This selects a certain register "source" is stored into this register or location.
or dedicated ~e~ory location based on the value of The least significant bits of "source" are used in
"selector". This register or ~eMry location is then the assignAent, ~ithout any overflo~ indication.
right justified, zero filled and stored in the 32-bit A trap is taken ~hen the selector does not ~atch
"destination". An INSMOVSPL violation occurs ~hen any of the entries in the follo~ing table or if
either the value of the selector does not correspond the current ring level does not ~atch the required
to any entry in the follo~ing list or when the current ring level.
execute level does not ~atch the level required for
reading the selected register.
selector #bits req'd XL Asse~bler Alias
selector #bits req'd XL Asse~bler alias o condition code 2 3 SetCC
1 rounding ~ode 2 3 SetRM
o condition code 2 3 GetCC 2 exit threshold 2 < source SetKTL
1 rounding ~ode 2 3 GetRM 3 flpt trap enable 5 3 SetTEFLP
2 exit threshold 2 3 GetlITL 4 int trap enable 2 3 SetTEINT
3 execute level 2 3 GetKL 5 dec trap enable 2 3 SetTEDEC
4 flpt trap enable 5 3 GetTEFLP 6 flpt ~ode 3 3 SetFPCMODE
5 int trap enable 2 3 GetTEl NT 7 STATUSB2 32 3 SetSTATB2
6 dec trap enable 2 3 GetTEDEC 8 Q offset 32 3 SetQ
7 flpt ~ode 2 3 GetFPCMODE 9 task breakrange LOI 32 3 SetTBR
8 STATUSA 32 3 GetSTATA 10 cond break A 1 3 SetCBA
9 STATUSB1 32 3 GetSTATB1 11 cond break B 1 3 SetCBB
10 STATUSB2 32 3 GetSTATB2 12 task clock enable 1 o SetTCE
11 TRYoffset 32 3 GetTRY 13 Interrupt ~ask 16 o SetIMR
12 task clock enable 1 1 GetTCE 14 Debug ring level 2 o SetDRL
13 STATUSC 32 1 GetSTATC 15 sys breakrange LOI 32 o SetSBR
14 Interrupt Mask 16 1 GetIMR
15 STATUSD 32 1 GetSTATD
16 HASH.PA 32 1 Status: depends on selector
17 HASH. LENGTH 32 1 Traps: depends on selector
18 PDIR.PA 32 1 SELECTORV
19 PDIR.LENGTH 32 1 INSPRIV
STKCONSISTV (if setting Q offset to value
outside SB and S)
Traps: INSMOVSPL

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DO NOT COPY -- HP PRIVATE INFORMATION DO NOT COPY -- HP PRIVATE INFORMATION

6.2.7.3 MOVEfSP8 selector.rl, destinaiton.m8 6.2.8 Instructions that interact mith the address space
Move from special register. This instruction is used to
obtain the contents of a special hardmare register
or dedicated memory location identified by the 6.2.8.1 PROBE ring_access.r1, address.m, length.r4, s_upper.r4
value of "selector". Values of "selector" not
represented in the folloming list cause the trap Probe access rights. This instruction sets condition codes
"SELECTORV" to be raised. dependent on the legality of accessing the address
range given by "address" and "length". PROBE tests
mhether in the ring level specified by "ring" the type
selector ibits req'd XL Assembler Alias of access represented by "access" mould be legal
everywhere in the logical address range starting at
o program counter 64 3 GetP "address" and ending at "address"+"length"-l.
1 ODTO.LA 64 1 A negative "length" is considered illegal; a zero
2 TCB.LA 64 1 GetTCB length represents the case mhere the address range mill
3 interval timer 64 1 not be used, yet the address Nay have to be loaded into
4 task clock' 64 1 a base register.
5 time of century 64 1 If the object is the stack object, then the ending
6 QLLA 64 1 address is cONpared against "s upper" instead of the
7 DST descriptor 64 1 present value of S or SL. -
8 CST descriptor 64 1 PROBE requires ring 1 privilege.
ring '= ring access[0 .. 3];
Traps: SELECTORV access '= ring=access[4 .. 7];
INSPRIV
Encodings: ring access
o o instruction fetch
6.2.7.4 MOVEtSP8 selector.r1, source.r8 1 1 meNory read-
2 2 memory=mrite
Move to special register. This instruction stores the 3 3
value of "source" into the special hardware 4 caller's
register or dedicated memory location identified
by "selector". Values not in this list will cause a SELECTORV trap.
The resulting conditon code settings are as folloms:
selector #bits req'd XL Assembler Alias CCL: the object does not exist or the indicated
access is illegal or the length is negative.
0 interval timer 64 0
1 task clock 64 0 CCE: the indicated access is legal but the indicated
2 time of century 64 0 address range is not wholly mithin the object.
3 QL LA 64 0
4 DST descriptor 64 0 CCG: the indicated access is legal at the indicated
5 CST descriptor 64 0 privilege level over the entire address range
specified; or: the object exists, the access is
legal and the length is zero.
Traps: dependent on selector
SELECTORV Status: CC
INSPRIV Traps: INSPRIV
SELECTORV
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 VISION ARCHITECTURE CONTROL DOCUMENT 02/08
DO NOT COpy -- HP PRIVATE INFORMATION

6.2.8.2 BPROBE ring_access.rl, address.b, length.r4, s_upper.r4

Probe access rights. This instruction sets condition codes
dependent on the legality of accessing the address
range given by "address" and "length".
This instruction differs fro~ PROBE only in that the
address is already loaded into a base register. This
i~plies that the object is already knoron to exist.

BPROBE requires level 1 privilege.

Status: CC
Traps: SELECTORV

6-56.5
 VCF 60 SPU BLOCK DIAGRAM

POWER OPTIONAL
SYSTEM
FLOATING
CENTRAL POINT
PROCESSOR
PSCB
PROCESSOR

DBI UNIT CONTROL BUS

PHYSICAL
CONTROL
FRONT SUPPORT SIB
PANEL PROCESSOR
RS232C I BPIB CACHE
/ ~ i\ / ~ /~
II
MEMORY MEMORY BUS
CONTROLLER
CONSOLI/VIRTUAL
FRONT PANEL

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INTERFACE w::;.~--~
I MENORY
ARRAY F CHANNEL
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II
DEVICE
, ADAPTER
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