UNIT-3

8085 Architecture
What Is Microprocessor ?

A microprocessor is an integrated circuit that consist Only CPU (Central Processing Unit). It consists of an
ALU, control unit and many registers, Where ALU performs arithmetic and logical operations on the data
received from an input device or memory.

Control unit controls the instructions an

d flow of data within the computer and registers like Register B, Register C, Register D, Register E, Register
H, Register L, and accumulator for ALU operations, storing the data/result.

Block
diagram of microprocessor

What Is Microcontroller ?

Microcontroller is a microprocessor based integrated peripherals. It contain CPU, ROM, RAM, timers,
counters, I/O ports, ADC, DAC, serial communication all functional block on a single chip, which make it a
complete system. Microcontroller is dedicated to performing a particular task and execute one specific
application. It is specially designed circuits for embedded applications and is widely used in automatically
controlled electronic devices. In microcontroller you cannot modify the size of RAM, ROM and other
components. Once a controller is designed the structure is fixed. So, the structure of the microcontroller is
not flexible.
Components of Microcontroller
8085 MICROPROCESSOR ARCHITECTURE :
The 8085 microprocessor is an 8-bit processor available as a 40-pin IC package and uses +5
V for power. It can run at a maximum frequency of 3 MHz. Its data bus width is 8-bit and
address bus width is 16-bit, thus it can address 2 16 = 64 KB of memory. The internal
architecture of 8085 is shown is Fig.

Arithmetic and Logic Unit

The ALU performs the actual numerical and logical operations such as Addition (ADD),
Subtraction (SUB), AND, OR etc. It uses data from memory and from Accumulator to
perform operations. The results of the arithmetic and logical operations are stored in the
accumulator.

Registers

The 8085 includes six registers, one accumulator and one flag register, as shown in Fig. 3.
In addition, it has two 16-bit registers: stack pointer and program counter. They are briefly
described as follows.

The 8085 has six general-purpose registers to store 8-bit data; these are identified as B, C,
D, E, H and L. they can be combined as register pairs - BC, DE and HL to perform some
16- bit operations. The programmer can use these registers to store or copy data into the
register by using data copy instructions.

Fig. 3 Register organisation

Accumulator

The accumulator is an 8-bit register that is a part of ALU. This register is used to store 8-bit
data and to perform arithmetic and logical operations. The result of an operation is stored in
the accumulator. The accumulator is also identified as register A.

Flag register
The ALU includes five flip-flops, which are set or reset after an operation according to data
condition of the result in the accumulator and other registers. They are called Zero (Z),
Carry (CY), Sign (S), Parity (P) and Auxiliary Carry (AC) flags. Their bit positions in the
flag register are shown in Fig. 4. The microprocessor uses these flags to test data conditions.

Fig. 4 Flag register

For example, after an addition of two numbers, if the result in the accumulator is larger than
8-bit, the flip-flop uses to indicate a carry by setting CY flag to 1. When an arithmetic
operation results in zero, Z flag is set to 1. The S flag is just a copy of the bit D7 of the
accumulator. A negative number has a 1 in bit D7 and a positive number has a 0 in 2’s
complement representation. The AC flag is set to 1, when a carry result from bit D3 and
passes to bit D4. The P flag is set to 1, when the result in accumulator contains even number
of 1s.
Program Counter (PC)

This 16-bit register deals with sequencing the execution of instructions. This register is a
memory pointer. The microprocessor uses this register to sequence the execution of the
instructions. The function of the program counter is to point to the memory address from
which the next byte is to be fetched. When a byte is being fetched, the program counter is
automatically incremented by one to point to the next memory location.

Stack Pointer (SP)

The stack pointer is also a 16-bit register, used as a memory pointer. It points to a memory
location in R/W memory, called stack. The beginning of the stack is defined by loading 16-
bit address in the stack pointer.

Instruction Register/Decoder

It is an 8-bit register that temporarily stores the current instruction of a program. Latest
instruction sent here from memory prior to execution. Decoder then takes instruction and
decodes or interprets the instruction. Decoded instruction then passed to next stage.

Control Unit

Generates signals on data bus, address bus and control bus within microprocessor to carry
out the instruction, which has been decoded. Typical buses and their timing are described as
follows:

 Data Bus: Data bus carries data in binary form between microprocessor and other
external units such as memory. It is used to transmit data i.e. information, results of
arithmetic etc between memory and the microprocessor. Data bus is bidirectional in
nature. The data bus width of 8085 microprocessor is 8-bit i.e. 2 8 combination of
binary digits and are typically identified as D0 – D7. Thus size of the data bus
determines what arithmetic can be done. If only 8-bit wide then largest number is
11111111 (255 in decimal). Therefore, larger numbers have to be broken down into
chunks of 255. This slows microprocessor.
 Address Bus: The address bus carries addresses and is one way bus from
microprocessor to the memory or other devices. 8085 microprocessor contain 16-bit
address bus and are generally identified as A0 - A15. The higher order address lines
(A8 – A15) are unidirectional and the lower order lines (A0 – A7) are multiplexed
(time-shared) with the eight data bits (D0 – D7) and hence, they are bidirectional.
 Control Bus: Control bus are various lines which have specific functions for
coordinating and controlling microprocessor operations. The control bus carries
control signals partly unidirectional and partly bidirectional. The following control
and status signals are used by 8085 processor:
I. ALE (output): Address Latch Enable is a pulse that is provided when an
address appears on the AD0 – AD7 lines, after which it becomes 0.
 II. RD (active low output): The Read signal indicates that data are being read
from the selected I/O or memory device and that they are available on the
data bus.
III. WR (active low output): The Write signal indicates that data on the data bus
are to be written into a selected memory or I/O location.
IV. IO/M (output): It is a signal that distinguished between a memory operation
and an I/O operation. When
1 it is an I/O operation. IO/M = 0 it is a memory operation IO/M =
and
V. S1 and S0 (output): These are status signals used to specify the type of
operation being performed; they are listed in Table 1.

Table 1 Status signals and associated operations

S1 S0 States
0 0 Halt
0 1 Write
1 0 Read
1 1 Fetch

The schematic representation of the 8085 bus structure is as shown in Fig. 5. The
microprocessor performs primarily four operations:

I. Memory Read: Reads data (or instruction) from memory.

II. Memory Write: Writes data (or instruction) into memory.
III. I/O Read: Accepts data from input device.
IV. I/O Write: Sends data to output device.

The 8085 processor performs these functions using address bus, data bus and control bus as
shown in Fig. 5.
Fig. 5 The 8085 bus structure
 8085 PIN DESCRIPTION

Properties:

 It is a 8-bit microprocessor
 Manufactured with N-MOS technology
 40 pin IC package
 It has 16-bit address bus and thus has 216 = 64 KB addressing capability.
 Operate with 3 MHz single-phase clock
 +5 V single power supply

The logic pin layout and signal groups of the 8085nmicroprocessor are shown in Fig. 6. All
the signals are classified into six groups:

 Address bus
 Data bus
 Control & status signals
 Power supply and frequency signals
 Externally initiated signals
 Serial I/O signals

Fig. 6 8085 microprocessor pin layout and signal groups

Address and Data Buses:

 A8 – A15 (output, 3-state): Most significant eight bits of memory addresses and the
eight bits of the I/O addresses. These lines enter into tri-state high impedance state
during HOLD and HALT modes.
 AD0 – AD7 (input/output, 3-state): Lower significant bits of memory addresses and
 the eight bits of the I/O addresses during first clock cycle. Behaves as data bus
during third and fourth clock cycle. These lines enter into tri-state high impedance
state during HOLD and HALT modes.

Control & Status Signals:

 ALE: Address latch enable

 RD : Read control signal.
 WR : Write control signal.
 IO/M , S1 and S0 : Status signals.

Power Supply & Clock Frequency:

 Vcc: +5 V power supply

 Vss: Ground reference
 X1, X2: A crystal having frequency of 6 MHz is connected at these two pins
 CLK: Clock output

Externally Initiated and Interrupt Signals:

 RESET IN : When the signal on this pin is low, the PC is set to 0, the buses are tri-
stated and the processor is reset.
 RESET OUT: This signal indicates that the processor is being reset. The signal can
be used to reset other devices.
 READY: When this signal is low, the processor waits for an integral number of
clock cycles until it goes high.
 HOLD: This signal indicates that a peripheral like DMA (direct memory access)
controller is requesting the use of address and data bus.
 HLDA: This signal acknowledges the HOLD request.
 INTR: Interrupt request is a general-purpose interrupt.
 INTA : This is used to acknowledge an interrupt.
 RST 7.5, RST 6.5, RST 5,5 – restart interrupt: These are vectored interrupts and
have highest priority than INTR interrupt.
 TRAP: This is a non-maskable interrupt and has the highest

priority. Serial I/O Signals:

 SID: Serial input signal. Bit on this line is loaded to D7 bit of register A using RIM
instruction.
 SOD: Serial output signal. Output SOD is set or reset by using SIM instruction.

 INSTRUCTION SET AND EXECUTION IN 8085

Based on the design of the ALU and decoding unit, the microprocessor manufacturer
provides instruction set for every microprocessor. The instruction set consists of both
machine code and mnemonics.

An instruction is a binary pattern designed inside a microprocessor to perform a specific

function. The entire group of instructions that a microprocessor supports is called
instruction set. Microprocessor instructions can be classified based on the parameters such
functionality, length and operand addressing.

Classification based on functionality:

I. Data transfer operations: This group of instructions copies data from source to
destination. The content of the source is not altered.
II. Arithmetic operations: Instructions of this group perform operations like addition,
subtraction, increment & decrement. One of the data used in arithmetic operation is
stored in accumulator and the result is also stored in accumulator.
III. Logical operations: Logical operations include AND, OR, EXOR, NOT. The
operations like AND, OR and EXOR uses two operands, one is stored in
accumulator and other can be any register or memory location. The result is stored
in accumulator. NOT operation requires single operand, which is stored in
accumulator.
IV. Branching operations: Instructions in this group can be used to transfer program
sequence from one memory location to another either conditionally or
unconditionally.
V. Machine control operations: Instruction in this group control execution of other
instructions and control operations like interrupt, halt etc.

Classification based on length:

I. One-byte instructions: Instruction having one byte in machine code. Examples are
depicted in Table 2.
I. Two-byte instructions: Instruction having two byte in machine code. Examples are
depicted in Table 3
II. Three-byte instructions: Instruction having three byte in machine code. Examples
are depicted in Table 4.

Table 2 Examples of one byte instructions

Opcode Operand Machine code/Hex code

MOV A, B 78
ADD M 86
 Table 3 Examples of two byte instructions
Opcode Operand Machine code/Hex code Byte description
MVI A, 7FH 3E First byte
7F Second byte
ADI 0FH C6 First byte
0F Second byte

Table 4 Examples of three byte instructions

Opcode Operand Machine code/Hex code Byte description
JMP 9050H C3 First byte
50 Second byte
90 Third byte
LDA 8850H 3A First byte
50 Second byte
88 Third byte

Addressing Modes in Instructions:

The process of specifying the data to be operated on by the instruction is called addressing.
The various formats for specifying operands are called addressing modes. The 8085 has the
following five types of addressing:

I. Immediate addressing
II. Memory direct addressing
III. Register direct addressing
IV. Indirect addressing
V. Implicit addressing

Immediate Addressing:

In this mode, the operand given in the instruction - a byte or word – transfers to the
destination register or memory location.

Ex: MVI A, 9AH

 The operand is a part of the instruction.

 The operand is stored in the register mentioned in the

instruction. Memory Direct Addressing:

Memory direct addressing moves a byte or word between a memory location and register.
The memory location address is given in the instruction.

Ex: LDA 850FH

This instruction is used to load the content of memory address 850FH in the accumulator.
Register Direct Addressing:

Register direct addressing transfer a copy of a byte or word from source register to
destination register.

Ex: MOV B, C

It copies the content of register C to register B.

Indirect Addressing:

Indirect addressing transfers a byte or word between a register and a memory

location. Ex: MOV A, M

Here the data is in the memory location pointed to by the contents of HL pair. The data is
moved to the accumulator.

Implicit Addressing

In this addressing mode the data itself specifies the data to be operated upon.

Ex: CMA

The instruction complements the content of the accumulator. No specific data or operand is
mentioned in the instruction.
 INSTRUCTION SET OF 8085

Data Transfer Instructions:

Arithmetic Instructions:
 INSTRUCTION EXECUTION AND TIMING DIAGRAM:

Each instruction in 8085 microprocessor consists of two part- operation code (opcode) and
operand. The opcode is a command such as ADD and the operand is an object to be
operated on, such as a byte or the content of a register.

Instruction Cycle: The time taken by the processor to complete the execution of an
instruction. An instruction cycle consists of one to six machine cycles.

Machine Cycle: The time required to complete one operation; accessing either the memory
or I/O device. A machine cycle consists of three to six T-states.

T-State: Time corresponding to one clock period. It is the basic unit to calculate execution
of instructions or programs in a processor.

––

 Opcode fetch
 Operand fetch
 Memory read/write
 I/O read/write

External communication functions are:

 Memory read/write
 I/O read/write
 Interrupt request acknowledge

Opcode Fetch Machine Cycle:

It is the first step in the execution of any instruction. The timing diagram of this cycle is
given in Fig. 7.

The following points explain the various operations that take place and the signals that are
changed during the execution of opcode fetch machine cycle:

T1 clock cycle

i. The content of PC is placed in the address bus; AD0 - AD7 lines contains lower bit
address and A8 – A15 contains higher bit address.
ii. IO/M signal is low indicating that a memory location is being accessed. S1 and S0
also changed to the levels as indicated in Table 1.
iii. ALE is high, indicates that multiplexed AD0 – AD7 act as lower order bus.

T2 clock cycle

i. Multiplexed address bus is now changed to data bus.

ii. The RD signal is made low by the processor. This signal makes the memory
device load the data bus with the contents of the location addressed by the processor.
T3 clock cycle

i. The opcode available on the data bus is read by the processor and moved to the
instruction register.
ii. The RD signal is deactivated by making it logic 1.
T4 clock cycle

i. The processor decode the instruction in the instruction register and generate the
necessary control signals to execute the instruction. Based on the instruction further
operations such as fetching, writing into memory etc takes place.

Fig. 7 Timing diagram for opcode fetch cycle

Memory Read Machine Cycle:

The memory read cycle is executed by the processor to read a data byte from memory. The
machine cycle is exactly same to opcode fetch except: a) It has three T-states b) The S0
signal is set to 0. The timing diagram of this cycle is given in Fig. 8.
 Fig. 8 Timing diagram for memory read machine cycle

Memory Write Machine Cycle:

The memory write cycle is executed by the processor to write a data byte in a memory
location. The processor takes three T-states and WR signal is made low. The timing
diagram of this cycle is given in Fig. 9.

I/O Read Cycle:

The I/O read cycle is executed by the processor to read a data byte from I/O port or from
peripheral, which is I/O mapped in the system. The 8-bit port address is placed both in the
lower and higher order address bus. The processor takes three T-states to execute this
machine cycle. The timing diagram of this cycle is given in Fig. 10.
Fig. 9 Timing diagram for memory write machine
cycle
Fig. 10 Timing diagram I/O read machine cycle
I/O Write Cycle:

The I/O write cycle is executed by the processor to write a data byte to I/O port or to a
peripheral, which is I/O mapped in the system. The processor takes three T-states to execute
this machine cycle. The timing diagram of this cycle is given in Fig. 11.

Fig. 11 Timing diagram I/O write machine cycle

Ex: Timing diagram for IN 80H.

The instruction and the corresponding codes and memory locations are given in Table 5.

Table 5 IN instruction

Address Mnemonics Opcode

800F IN 80H DB
8010 80

i. During the first machine cycle, the opcode DB is fetched from the memory, placed
in the instruction register and decoded.
ii. During second machine cycle, the port address 80H is read from the next memory
location.
iii. During the third machine cycle, the address 80H is placed in the address bus and the
data read from that port address is placed in the accumulator.
The timing diagram is shown in Fig. 12.
Fig. 12 Timing diagram for the IN instruction