S A N J E E V K UM A R G A U T A M
A1/1 Sona Park Society,
Near Sneha - plaza,
IOC-Road, Chandkheda,
Ahmedabad, Gujarat -382424.
Contact: 7984525365
Email: gautamsanjeev42@gmail.com
CAREER OBJECTIVE:
“To secure employment with a reputable company, where I can utilize my skill and business
studies background to the maximum”
EXPERIENCE:
Having experience of 1.8 years in a MAA Enterprise as a Service Engineer
From 1/11/2021 to 30/06/2023
Having experience of PCBA and PCB Quotation
Currently working as a Purchase Engineer in PNC Design and Development
From July 2023 till today.
TRAINING EXPERIENCE (INTERNSHIP):
Company : Indicus Technology
Duration : March 2021 – September 2021
Designation : VLSI Design & Verification Trainee
EDUCATIONAL QUALIFICATION:
Sr. Standard/Degree Percentage Session University
No.
1. Bachelor of Engineering (E.C.) 7.17 CGPA 2017 Silveroak College of
Engineering &
Technology
2. Diploma Engineering (E.C.) 6.75 CGPA 2014 VPMP Polytechnic
3. SSC 66.00% 2011 GSHSEB
AREA OF INTEREST:
VLSI Technology
Embedded Electronics
Network and Telecommunication
SOFTWARE PROFICIENCY:
Key Skills: Digital Logic Design, RTL design and verification In Verilog HDL
VLSI Programming Languages: Verilog HDL, System Verilog
VLSI Programming Tools: Xilinx, Questa sim
ACADEMIC PROJECTS:
Degree Final Year Project:
Smart Metering System
Description: A smart meter is usually an electronic device that records the Consumption of
electric energy in intervals of an hour or less and communicates that information at least daily
back to the utility for monitoring and bill purposes smart meters enable two-way communication
between the meters and the central system.
Diploma Final Year Project:
Seven Segment Voting Machine
Description: A seven-segment voting machine is to develop the count of votes on a set of seven
segment display. A set of switches are provided through which a user can interface through
8051 easily.
Projects During Internship:
1] 16x8 RAM
Description: Wrote Verilog RTL Code for Designing Ram and Verified the code using Verilog and
System Verilog. Simulated using different types of Test Cases and Implemented Code as well as
functional Coverage while producing the Respective coverage report of the above mention code.
2] FIFO
Description: Wrote Verilog RTL Code for Designing FIFO and Verified the code using Verilog and
System Verilog. Simulated using different types of Test Cases and Implemented Code as well as
functional Coverage while producing the Respective coverage report of the above mention code.
Extra Activities:
Participated in various workshops arranged at colleges.
Achievements:
Attend training on PCB Design, Manufacturing and Testing
Attend Technical Debate on “Money spent on Space Research in India” at Collage
PERSONAL INFORMATION:
Father’s name : UMASHANKAR
Date of Birth : 10th NOV 1994
Marital Status : Un-Married
Sex : Male
Nationality /Religion : Indian/Hindu Languages
Known : English, Hindi and Gujarati
HOBBIES:
Drawing, Reading, Playing Cricket, listening to music, Traveling
DECLARATION:
I hereby declare that all the above information is true to the best of my knowledge and belief.
Date:
Place: Ahmedabad
(SANJEEVKUMAR GAUTAM)
