| | Chay ipter-1 : Data Representation . ‘ z Fixed point representation IEEE floating point number tion © Computer arithmetic + Adding 2 complement numbers ‘© Multiplying floating point num! Chapter-2:Machine instru Mode « Basics puter design: = Comp Layers Computer org} Evolution of digital ‘computers ‘and function ‘ofacomputer system is of computer structure representa! yctions and A s ‘of the come ter ‘of abstraction yanization and: architecture ‘Component = Bus structure Data storage in the memory Instruction oycle = Machine instructions Instruction formats ‘Addressing modes Instruction set = Typesofmacl = Instruction stream ine instructions (vs) Data stream Chapter-3 : CPU Design « ALUstructure: Introduction » AlUdesign «System bus structure: «Data paths «Bus organization of data path + Independent of data path + Control unit design: = Introduction '* Multicycle data path: ‘and control = Control unit «Micro operations and control signals = Control unit implementation Chapter-6 108 n processing + Difference’ petween data paths fesign and Issues: «Pipeline P pipeline data path Instructio“ pipeline hazards pipeline performance analysis speedup 5: Memory Organization e Handling: ‘cache operations types of caches Performance Improving cacl : Input-Output Interface lO interface design: Introduction = [Qaccess structure = [Omodules = Types of interrupts 10 modes: » [Otechniques = Direct memory access = Ochannels = Buses Secondary memory: = Secondary storage = Magnetic memory = Optical memory = Structure of a disk Data organization on nine track tapes he performanceQ4 Q2 Qs | Multiple Choice Questions In the IEEE floating point epresentations the imal Value 0 x ‘Corresponds to (@) the normalized value 2-127 (©) the normatized value 2-126 (6) the normalized value 40 (2) the special value + 0 What is the Biases of the following format: s BE M * y z (@) Normal Bias = (22-y_ *) and excess Bias = (2-2) (©) Normal Bias = (27-1 _ 1) and excess Bias = (2-1) a (©) Normal Bias = Z| and excess Bias = (2-1-1) (d) Normal Bias = +127 and excess Bias = +128 In IEEE floating point representations, all the exponent bits are 1 and mantissa bits are non- Zero. This represent @o (b) infinity (©) denormalized value (d) error Common Data for Q.4 and Q.5 : Consider the following floating point format. 3190 23 o 8 E M Bias = 31 ‘Assume only 0 are padded while shifting a field, " Loew oetans aoukdeo © fue u pestnn 10 peanpoide: aq Aeui 4009 Sk Jo Hed ON "MISC MON ‘SUORBOHAN ASW 3A¥H: ‘ojsejued ven ou yroWMA Wo} Aue ole WETTER ENO Crate Data Representation 2 s 2 a o o 2 a FRedecirlnunber015625.2¢has allowing mal representation without nomalizaton @) 24280000 (®) 24 100000 (©) 21280000 (9) 21 100000 The normalized representation of above number is hexadecimal format (@) 24400000 (©) 21520000 (©) 21400000 (® 24520000 Find the decimal equivalent of the bit Pattern 101999111 101 asper the IEEE 754 standard, in IEEE 754. single bit Precision binary floating point format is stored in 32 bits S(1 bi) | (@ bits) M023 bits) Exponentis biased with 127, (@) 1.625 (b) -1.875 (© 1.625 (©) 0.625 The n-bit fixed-point representation of an unsigned real number X uses f bits for the fraction part, Let i = nf, The range of decimal Values for Xin this representation is (@) 2%to 2 (bd) 2to (2'-2) (0) Oto2! (d) 010 (2-2) © Copyright: MADE EASY @ wow madeeasypubiications.org6 | Computer Science & IT © Computer Organization and A = EVE)| Numerical Answer T ype G8 Questions Q.8 Whatis the decimal equivalent of the fol binary code when the data is in () unsigned format ... {i sign-magnitude format (ii) 1's complement format (iv) 2s complement format Binary code: 101101101 Q.9 What is the hexadecimal following data elements 7 CPU). 0 BAo ervere (A120)y9 ~~ (i) 370 ~ (Ww) (-28)10 perations are required Q.10 How many Arithmetic Of a in the following Booth's multiplication. Muttiicand: 1011011001 Multiplier 1010010101 2:11. Whats the r-coded multiple of he following bit multiplication. Mutiplicand: (-72)10 Multiplier: (-67)i0 Q.12 What is the Binary mutt re-coded multiplier. + 10-14 10-10+1-1+ 10-1 Q.13 What is the largest positive data in the 12 bit CPU, when the ALU performs the signed Arithmetic operations. Q.14 What is the decimal value associated with the following memory data. lowing uivaient of the computer (8 bit eq Tl th iplier of the following BE M L, excess os Q.15 Whats the decimal v falue associated wit following memory data, a i SBE M [o 1000010 10110000] 8 3 3 3 E z z 2 3 s rchitecture at is the rang? g 6 Wh ; following forme pe lel a a OH e of data possible in the 47 What is the rang MADE EAs, Publicane exponents POSsible in thy following format | [asl se Ze bits Le excess Bias 18 Whatis the hexadec! inthe memo mal equivalent of (13.125) ho ry using te folowing format. mM Toe ‘bits 26bis Ly excess Bias fr the following floating point format: q.19 Consid 3B 1—— M 5] E The value of floating value number in this system is Ve (198x277 x 1-F Find the value of the corresponding decimal value if the floati Q.20 The two numbers given bel fing point stored is 3F8000007 low are multiplied using the Booth's algorithm Muttiplicand: 0101 1010 1110 1110 Multiplier 0111 0111 1011 1101 How many additions/subtractions are required for multiplication of the above two numbers? Common Data for Q.21 and Q.22 : Consider the following floating point format 15 14 87 0 ‘expont an bit AE es ent, Mantissa is a pure fraction is sign magnitude form. Q.21 it ees poe x23 has the following ria se a aig ge without normalization @ worm madeecsypubliatons. ogMADE ERsy Publications Q.22 Thenormatized 7 fepresentation, Tormatis speciied as foleme rena above " lissa has animplicit 1 Preceding th, : '@ binary (radix) Assume that ‘Only O's are Padded in. ‘While. ne afield. The normalizag Tepresentation of abo ve pa umber is (0.289 x 218) ig Multiple Select Questions Q.23 Which of the followin, the compute oe PF e8ent the (13) sin (@) 10011 () 11101 (©) 10010 ) 111110011 (©) 111110010 () 100001101 (9) 11100010011 Q.24 In which of the following cases overflow will be Ccourred after adding the signed Binary Data (@) 1101101 (©) o101110 1010100 o110101 (©) 100110 (@) 1101111 oot 1100010 (©) 0101011 000101 Q.25 Which of the following are the redundant data Codes in the system using the sign-magnitude format. A# 000000 and 100000 (b) 000000 and 111111 (©) (000),, and (8FF),, A) (000),, and (800),, (©) (000),, and (FFF),, Q.26 Which of the following codes represent the errors. In the 32 bit format. (a) 011111111.00000000.. 1. 111111111 1010 (&) 111111111 0000000 Ja) 111111111.0001100111 Q.27 Which of the following codes are used to represent the representable minimum and maximum values in the 32 bit format. Ing UBUD @ Q.2e aNd ASV SQV OF ed ON ‘IYI9g MeN ‘sU0} T2. nn 40 poonpoides oq Kew 4009 2} 13. Ned Uenim ous inowym wH0} AUB Ul po \u\er\2s @ clas ©) S:011BE:Alos, M: alos (©) S:0/1 BE: oo000001, M:Allo's (©) $:01BE: allo’, M:0000 01 (23 bit) (@ S:OMBE: alts, M:aNts ©) S:01BE: 11111110, M All's Which of the folowing techniques are used to handle the overtow and underiow data in the floating point format? (@) Roundtonearest (bo) Roundto“0" (C) Special value ‘or (A) Special value +20 and co (©) Round toe Try Yourself The value of a: float type variable is represented using the single-precision: 32-bit floating point format of IEEE-754. ‘standard that uses 1 bit for Sign, 8 bits for biased exponent and 23 bits for ‘mantissa. A float type variable X is assigned the decimal value of -14.25, The. Tepresentation of Xin hexadecimal notation is (@) C1640000H —(o) 416C0000H (©) 41640000 — (d) C16C0000H Ans: (a)] single precision floating point number contains the sequence of bits 100111 1100000000001 000000000000. Information is stored in the following left to right order: sign bit, exponent (bias 127) and mantissa. Which of the following representation in decimal is equivalent (@ 2142") () A) x 24142") () Ay 2°5(142-) (A) (1) x 201421) [Ans: (c)] Sign extension is a step in (@) floating point muttiplication (b) signed 16 bit integer addition (©) arithmetic let shit , (@) converting a signed integer from one size to another © Copyright : MADE ERS © worn adecnpebeaionsrg>» (CU EL cane Machine Instructions and Modes Addressing (a) 7x2 and 1x 2° = ane ° (b) 1x20 and 7 x 2° lool Mitte Choice Question i Oana 28 “actions of the loop body 2 (6) 8x2 and 1x 2? of main memory is 32 K x 8 bit. Q.1 Assume that five instruction: starting memory locations are 5000, 5004,5008, $ @.5 Supposethe size 5012 and 6016 respectively. Assume each i Peoretre szosotadcress bus epee of memory. Find the g (@) Address bus = 92 bits, Data bus = 8 bits Data bus = 3 bits timed & (0) Address bus = 15 bits, 32 bits, Data bus = 3 bits instruction takes 4 bytes 15 bits, Data bus = 8 bits content of Program Counter (PC) atthe tone (©) Address bus = branch target addressis gene neededtoreturn tothe loop are respectively. & 2 er onaeta 2 (@) Address bus = (6) 5020, -16 2 common Data for Q.6 and Q.7 : (©) 5020, -20 3 Consider the following assembly language program (0) 5016, -20 F for a hypothetical processor. A, B and C are 8-bit Q.2. Two registers R, and A with values A = 18 & registers. The meanings as various instructions are and f= 13 respectively, The instruction SUB & shownas comments. Fis inmemary location 5000H. Ifthe size § MoV B, #0; BeO ofaninstuctionis 8 bytes, then after the execution 2 MOV C, #8 C<8 of the instruction the ia ofPCand A,wilbe § 7. cMP 0, #0, CompareCwith 0 f ie = a rf R= i JZ X; Jump toXifzeroflagis set nace ete 5 suB C, #1; CeC-1 (@) PC =5000H, R =5 z RRC A, #1; Rotate right A through carry @.3Inwhich ofthe following ada do,the ear 3 Inwhich of the following addressing mode, the ¢ wy Jump to Y if carry flag i content of program counter is added to the & UMP oZ: faa toZ eee address part ofthe instruction to get the effective gy ” i re 5 Yi Add B, #1; BeB+t (@) Indexed (b) Implied = uMP 2; Jump to Z (c) Relative (d) Register 3K: Q.4 Acomputer system that used memory mapped i Q.6 Ifthe initial value of register Ais A). The value 10 configuration, has a 32-bit address space. 2 of register Bafter the program execution will be Actssyi Teh Be fee Ss ace. § (a) The number of ‘0’ bits in A, /nat is the maximum amount of memory i (b) The number of ‘1’ bits in A, address and I/O port address that canbe g OA $ ? (a8 referenced in such a system respectively? © Copyright : MADE EASY @ wunwmadeeasypublcaionsogy sulle @ MADE Ensy Q7 Which Of th Common Data for Q.8, 0.9 an, Solve the problems Consider the foit hypothetical CPU and R, Instruction MOV A,, 6000; MOV Rp, (R,); MOV 6000, A; Halt; Qs Qe Q.10 * 1000 (decimal). Ifan interrupt occurs ‘during the Publications 0 following 4 Inoorted at location Of rogistor 4 Stor progr ih 8aMO as its initia) Value ne (2) RRC A, #1; Rotate r ht (b) NOP; No, Peration Tech ie (©) LRCA, #1; Lott rotate Att (ADD AH Ae ayy MOON cary PBtUCtiong Wh, '8Ur@ that the Q.10; 8nd choose the correc, lowing progr, iM segm, having three user rag Operation Instruction size (words) , —M(6000] Ro MILR,}) Rye Rat Ay M6009] ~ A Machine Halts Consider that the memory is byte addressable with word size 32 bits, and the Program has been loaded Starting from Memory location 1000 (decimal), If an Interrupt occurs when the CPU has been halted after ‘executing the Halt Instruction, the return address saved in the Stack will be (2) 1007 (c) 1024 Ry Pj out 19d MON “suonBonand ASV 3GVW 01 seneU DefGns NOLKCD @ Sie Pas. (b) 1020 (a) 1028, Consider that the memory is word addressable with word size 32 bits and the Program has been loaded Starting from memory location ; : : i : i ‘ADD instruction, what will be the return address Pushed on to the stack (a) 1007 (b) 1004 (c) 1005 (d) 1016 Let the clock cycles required for various ‘operations be as follows: Reglster to/from memory transfer: 3 cycles ‘Add with both operands in registers : 1 cycle Instruction fetch and decode: 2 cycle per word The total cycles required to execute the program Is & 3 z 3 £ 3 = 3 3 3 so © Copyright : ape EASY iit | 9 (8) 29 (b) 24 () 2 (2a 2.14 Match Let wih Ustll and select the correct newer Using the codes given below the lists: Ust.4 Ust-tt A A= Bi) 4, Indirect Addressing B. Whiletrarsy 9” Indexed Addressing C. int temp = *y 3. Auto increment Codes: ABC @3 2 4 )1 3 2 2 3 4 @1 2 3 Common Data For 0.12 and Q13; Consider a h \ypothetical processor ig ‘Supports both 2 address and one address instructions, It has "28 word memory A 16-bit instruction e laced inthe one memory word, O12 What is the range of two address and one ‘address instructions are supported, (@) 1103 and 128 to 364 (b) 1 to3 and 128 to 384 (C) 010.4 and 120 to 380 (2) 0103 and 64 to 256 Q.13 If two 2-adaress instructions are already existed, How many one address instructions can be supported, (@) 128 (2 (0) 256 () 2 Q.14 Match List-1 (Instructions) with List-I1 (Addressing Modes) and select the correct answer using the codes given below the lists: LUst-1 LUst-l A. ADD Ay, [2000] 1. Directaddressing mode B. MOVR,,#10 2. Immediate addressing mode C. ADDR,,R, 3. Register addressing mode D. ADDR,(100) 4. Indirect addressing mode @ wwwmadecasypublicationsorg10 | Computer Science & IT » Computer Organization and Architecture npanso Q.15 Consider the instruction ADD A, [[2000]] where ‘ADD stands for addition. The number of memory cycles required to execute the instruction is Jong, register ___ where opcode is 2 ‘word addris 1 word long and memory addris 2 word long. (0) 7 @s @3 @ 6 0.16 The memory locations 1000, 4001 and 1020 have data values 18, 1 and 16 F before the following program executed MOVI A, ti Move immediate Load Ry 1000(R,; Load frommemory ADDI Fy 10003 ‘Add immediate ‘tore! (F,), 20; Store immediate Which ofthe statement below is {Tue after the 4021 has value 20 (c) Memory location 4001 has value 20 (@) Memory location 0.17 sfweuse internal data forwarding to speed UP the performance of a CPU (Ry, A, and Fa) are registers and M[100]is a memory reference then the sequence of operations. A, M100] M(100]—> A, M(100]—> A can be replaced by @ RR (b) M[100]—> A, R,>M{100] y+ Ri Ry () R,>M[100] (4) R, > A, RF AOR, RM{100) Q.18 Inwhich addressing mode the effective address of the operand is generated by adding a constant value to the content of a register? ‘suoneaiiand ASy: Ra icant in dog /A BQWW 01 19new rDe[ang UBUA auBukdeo @ 14 SIM 0 Wed ON “yleq mor suojssiunied ue: UM OUR INOYLIM WO} Kut 4 Aue UI posiin 10 peonposdes oq A 1 0g Kew yoo Q.19 Q.20 Q21 Q.22 Q.23 publications pe ma ‘Absolute mode ») Indirect ed a x MO a immediate mode (@ ind othetical processor with an ro uW fi, 20(F) Which during ‘a yord frommemory and reads 232-8" ar atria ag2bit ragister Py. The affective sto ofthe me ry location is obtained by on instant 20 and the contents. ee ‘er ich of the lowing bestreflects coed fe implemented by this the addressit7 operand in memory instructior Consider @ Pi instruction (0) Regis (@) Base indexes i has 12 register A certain RISC processor ‘ window's and 46 global registers. Each window has 8 input 16 1ocal and 8 output register. The total number of registers in the processor is (@ 312 (b) (c) 26 (a) 304 Compared CISC processors: contain (a) More ret (b) Larger in (c) Less registers an (d) More transistor elements RISC processor gister and smaller instruction set struction set and less register \d smaller instruction set Word 20 contains 40 Word 30 contains 50 Word 40 contains 60 Word 50 contains 70 Which of the following instructions loads 60 in tothe accumulator? (a) Load immediate 20 (b) Load direct 30 (0) Loadindirect20 (d) Load indirect 30 Consider the C struct defined below: struct data { _ intmarks [100]; char grade; ; int cnumber; struct data student; © Copyright : MADE ERSU @ wm madeeasypublcations.019MADE Ensy Publications The base addres, Fegister Ri, The eda : eealble = accessed fficiently using" ST@4° can be (@) Postincrement Addressing m, (b) Pre-decrement Addressin, (©) Register direct Addressin, fe. (@) Index addressing Mode, X(R1}), pa Qh an offset representeg in 25 complomas 16-bit Teptesentation, Linked Answer for 2.24 to Q.25 A computer has 40-bit ‘register operand and 4 "Boeneel purpose ecistersend ase Mev Q.24 Ifthere aren! 2-address instructions both register and memory, address instructions (whic are possible @) (8—n)xar (©) (B-(0-1)) x27 Which uses then how many one uses only memory) (©) (24—n) x97 (9) (2~ (44) x97 Ifthere are ‘n’ two address instructions which uses both register and memory, ‘mt one address instructions which uses register operand then fog. 2870 address iristructions are possible (2) (2-1) x27 — mx 228 (b) ((2*—n) x 220 — mp x. o7 () [2° 1) x 22_ my x07 (©) (24—1) x27 — mm} 228 Q2 a Q.26 Consider a hypothetical CPU which supports 16bitinstruction, 62registers and 1 KB memory Space. I there exist 12 two address instructions Which uses register reference and 14 one address memory reference instructions. How many O-address instructions are possible? (@) 1024 (b) 2048 (©) 4096 (a) 8192 8 Numerical Answer Type 3 E} Questions Q.27 Consider the system specifications given below. What is the size of an opcode in the system respectively, ° g ® : : R 3 2 z i g 3 3 9.28 Consider the SPecifications of the hypothetical Systems given below, at is the instructi ion set size of a system Tespectively, Q.29 Consider 16 bit CPU which supports 1 word opcode, Instruction is designed with opcode and address: field, placed’ inthe memory with a Starting address of (800),9. System supports 8 registers (5) “Contain data ie, 200 r, contain EA ie,, 00, fis designated as Riwhich contain 80. 7S designated as R, which contain 700, ‘When the instruction is designed with memory ‘eference AM then address feld ofan instruction Contain 400. Memory content of a 400 is 500, Assume all values are in. decimal. Calculate: the EAWhen the instruction is designed with (@) Immediate AM (b) Register AM (©) Direct AM (A) Indirect AM (€) Register indirect AM (0) Indexed AM without R, (9) Indexed AM with A, (H) Pre auto inc. AM ()) Post auto Dec. AM ) PC-telative AM (®) Base req. AM Q.30 Considera hypothetical computer which supports instruction with register operand and memory operand. System contain 200 registers and 32 KB RAM, 24 addressing modes are used in © Copyright : maADE EASY & wmonmadeeasypublieations.org \a\onlas © y: 12 | computer Science &IT «© Computer Organizatio the CPU. 32 bit instruction is placed in the memory. How many instructions possible in the CPU if addressing modes are implemented explicitly in the instruction. bit CPU which Q.31 Consider a hypothetical 24 ced in 266 KB ‘supports 40 bit instruction pla RAM. Instruction contain 8 bit opcode, 2register operands, memory operand ‘and immediate constant field. Registerfile size is 16. | Largest unsigned consantintreinsruclon is : : ik Largest postive signed constant ir tion is y mn ee veersarispossbeinteinstucion : , ts possible Iv, Range ofsigr-magnitude consi poss in the instruction pee eg A Range of signed constants possible” the instruction is __— in the Q.s2 Consider the following code: I: ADD Nt fe Ty: Load 4, (4 — Milrell Ty: SUB ly We 9~% T,; Load (7) Mill] = ‘5 Ig: ADD iy eh + J: Halt Halts Ty: AD Gy Kao Gt 's ‘The data transfer instruction size is 64 bit, ALU operation instruction size Is $2 bit ‘and branch instruction size is 16 bit. ‘Assume program has been loaded in the ‘memory starting from the location 5000 decimal onwards. If an interrupt occurs during the ‘execution of J, the return address pushed on to the stack is : Common Data for Q.33, 0.34 and Q.35 : Consider the following program segment. Here F, R and R, are the general purpose registers. Instruction Operation Instruction size (words) R, M[3000] 2 AReMER) 1 Ae R th, 1 MOV R,, [3000]; Loop: MOV A, (Ry); ADD Ry Ry; jew 29fang AUBUAdED @ z 5 m o 3 100 ON ‘su lwio} Aue ui pesiitin 10 peonpoides oq Aeui 008 stun jo Lund *Uo|ssiuied uoniim ous ino locali a.33 Q.34 Q.35 Q.36 Q.37 10 is 100. The ion 1000. All the nu =o MADE Ens. tecture and Archite ans MILFgI < Re Rye fytt mow (A) Fei ‘ RyeR-1 1 2 a, inc Py DEC Fi Branch on non zero BNZ [00P: aa .e content of memory location 3009 g tof the register A IS 2000, The ofthe memory locations ftom 200044 program is loaded from memoy mbers in decimal. memory is word addressabye emory references for accescin, i the program complete, ‘Assume that the The number of m the data in executin: is ~ ‘Assume that the memory is word addressabje ‘After the execution of this program, the conten, ‘of memory location 2010 is. ‘Assume that the memory is byte addressabj and the word size is 32 bits. If an interrupy ‘occurs during the execution of the instruction “INC Ry", what return address will be pusheq conto the stack? Considera three word! machine instruction ADD, AIR]. @8 y The first operand (destination) “A[A,]" uses indexed addressing mode with Ras the index register. The second joperand “@ B" uses indirect addressing mode A and B are memory addresses residing at the second and third words respectively. The first word of the instruction specifies the OP-CODE, the index register designation and the source and destination addressing modes, During execution of ADD instruction the two operands are added and stored in the destination (First Operand) The number of memory cycles needed during the execution cycle of the instructionis. ‘Amachine support 16-bit instruction format the sizeof address field is 4-bit. The computer uses expanding OP-CODE techniques and 34 two address instruction and 100 one address instructions. The number of zero address instructions it can support is ‘© Copyright : MADE EASY —— ee @ wow.madeeasypublicationso9Publications. Q.38 Consider evaluating the folowing expression tree on a machine with load-store, architecture inwhich memory can be accessed ‘only through load and store instructions. The variables a, b c, dand e are initially stored in memory. The binary operators used in this expression tree can be evaluated by the machine only when the operands are in registers. The instructions produce resuttonlyin register. fnointermediate results can be stored in memory, What is the minimum number of registers needed to evaluate this expression. Q QO Q ®©O @O® © © The program below uses six temporary variables a, b, o, d,¢,f | Q39 Assuming thatall operations take their operands from registers. What is the minimum number of registers needed to execute the program without spilling? Q.40 The frequency of different types of instruction executed by a machine is tabulated below: [Operand Accessing Mode] Frequency in % Register 20 Immediate 20 Direct 2 Memory indirect 7 Index 1 Assuming two cycles are consumed for an operand to be read from the memory one cycle for index arithmetic computation and zero *Uo|ssiusied ueniim eu) inoWIIM WHO} AUB Uj pesiilin 40 psonpoides oq ABU 400g 8/43 Jo Led ON “I4IeG MEN ‘suON|BoT!aNd ASV] AGYWN 0} JenBw i99[ang AyO}LAdoD @ wirvanne | 13 cycles if operands are available in registers or with inthe instruction itself, the average operand fetch ime (in cycles) of the machine is__. Q.41 Consider a system with following content of memory addresses at this instance: Memory address Content in address 2000 20 2160 5 3000 30 3020 40 5000 50 Lt system execute following instructions in order: LOAD R,,3000 immediate mode ADD Rp, (2000) /I direct mode ADD. Ry,(F,),0 —_Iregisterindirect mode Left most registers in above instructions are destination registers and other fields are operands for instruction. The value of R, after above execution is wal, Multiple Select Questions Q.42 Consider the following statements regarding Interrupt Service Routine (ISR). Which ofthe following is true? (@) INTR signal is used to get the address of ISR routine. (6) INTA signal is used to get the address of ISR routing. (0) The retum is stored on the processor stack before start ISR. (@) Different devices may have diferent ISP's that get executed when aninterupt request is arrived. Q.43 Inthe CPU organization, ALU operands (ALU data paths) are accepted to perform the operations to manipulate the data____- (@) Only from the registers (0) Only rom the memory (©) Both register and memory (@) Only from the stack © Copyright : MADE EASY @ wwnmadeeasypublications.org>. DE ER: mADE ey 14 | Computer Science & IT » Computer Organization and Architecture Q.44 In which Of the following addressing modes, ° effective address is calculated by adding the 9 Constant value to the content of some register $ pn ariioen in org (@) Directindexed AM 2 71, amachine ree rns 64 OO Sch (0) Indirect indexed AM g long insects ong. tt needs 10 Suppoq meno : which is ae 's, which have an immediata 45 instruction to two register Operands, id Y , operand in Ce immediate operand is an ir that A ed ft the maximum value of the n (d) Indirect AM Q.45 Consider the following statements: ported (2) Inthe variable length instruction SuPI 5 insigt ps CPU design expand opcode techniaue '6. fj immediate operand iS gates required to design different instruction F eel a > byte-address; formats. sas ted g ‘der a processor with byte-addressabie (0) In the fixed loath instruction ssieniysy r2 ee cau that all registers, including : zg yemory. Capea er aa instruction $ Pees ‘Counter (PC) and Program Status Worg pia 4 z (PSW), are of size 2 Ora oa (9 innevadielnghrerctens SUPP memory mPa para. The stack po CPU design, CPU identifies the actual & (C10 is or eiolemnentor hectic length of an instruction after decoding the (SP) points to the top el The g current value of SP is (O16E);g- The CALL instruction is of two words, the first word is the op-code and the second word is the Starting address of the subroutine (one word = 2 bytes), The CALL instruction is implemented as follows: Store the current value of PC in the stack, Store the value of PSW register in the stack, Load the starting address of the subrouting inPC. The content of PC just before the fetch of a CALL instruction is (SFAO),,. After execution of the CALL instruction, the value of the stack le length opcode. (@) RISC CPU supports variab| instructions. Which of the above options are false? Q.46 Consider the following characteristics: 4. Fixed length instruction. 2. More addressing modes. 3. Hard-wired CPU design. 4, Micro-programmed CPU design. 5. Smaller instruction set. 6. Variable length instruction. 7. Expensive system . 4© Peonpoidss oq ABU i009 aly Which are the RISC CPU characteristics? 4 : @) 1,3,5 pointer is (0) 1,2,4,7 (@) (016A), (©) (0160),, (©) 1,7,5,3 (C) (0170),, (d) (0172), ©) 24,6 [Ans: (d)] 13. A hypothetical Processor uses the instruction format with three fields i.e. opcode, register address fields used to represent one of the Q.47 In the data transfer, data manipulation and transfer of control instructions execution, In Which state effective address is used to access uolss; ISStuiled Ueiism ou) noua Woy kue Uy posi the information, @ IF ) oF E Eoaisiors and memory address field, A'32 bit © D (@ PD Instruction is placed in the 2Y addressable cell (© we memory. If th i E fi hala ere exists. '2' two address structions which uses both re ister and memory MADE ERSy @ www.madeeasypublications.orgPublications feference how many one addres reference instructions possible in the (2) (282--2) x av (©) (27-2) x2 8 register Processor. (b) (28-4692) ay () (2827~2) x a8 {Ans: (b)] 4, Consider @ 16 bitprocessor in which the following appears in main memory starting at location 38246: 38248 38267 =12 36248 Next instucton | The first byte of the instruction specifies the opcode and type of addressing mode used, Second byte of the instruction is the address field. Determine the effective address of the instruction to transfer the control if the mode field uses the PC-relative addressing mode. (a) 38234 (b) 36235 (0) 38236 (d) 38248 [Ans: (c)] 5. Consider a hypothetical process which supports two address instruction format. Instruction takes two operands 1* operand using the register addressing mode and 2" operand using the indexed addressing mode. Processor supports 2” operations and 128 registers including the index register. Base address of the operand will be present in the address field of the instruction as a constant which occupies 20 bits space. What is the length of the instruction? (@) (34x n) bits (b) (34+ n) bits (©) (2°x 34) bits (d) (27+ 34) bits [Ans: (b)] T6. Acomputer supports 64 kB physical memory with the following contents MP | Mode Memory ‘0000 4000 [23H 4001 | 12H 4002 [OAH 4003 |__FCH 4004 ffff 1d ASV 3QVW 01 10NeW 320/4NS "WWOLLAdOD @ Nn 40 poonposdes oq ABW 400q S14) Jo Wed ON “TyIoG MON “suON “uoyss}uied UoHLM oY InoWIYR wi0} AUB UI P a = OO << work i | 15 The following instruction is executed on the two different computers (C, and C,). Which are having the above memory specifications. C, uses the litle-endian mechanism and C, uses the big-endian mechanism. Ty: MOV fo, @ Fy; fo MILI) {tis @ 64 bit instruction with a general purpose register size of 16 bits. Register r, contains 4002H what is the output of the above instruction when it is running on C, and C, respectively. (a) OAFCH and FCOAH (b) 2312H and 1223H (c) FCOAH and OAFCH (d) 1223H and 2312H [Ans: (c)} Consider the following program segment used ‘toexecute on al Consider all the registers are of 16 oe size , MOV CX0005 Jp MOV BXOFF7H Label fy MOV AXOBCAH 1, OR BKAX BX BX (OR)AX Js AND DXAK DX DX(AND)AX Ig LOOP label ; LOOP wICX=0 Processor clock frequency is 1 kHz. In which data transfer operations takes 6 cycles, data Manipulation operations takes 4 cycles and transfer of control operations takes 2 cycles to execute. How much time is required to execute the program on a above CPU (a) 92msec (b) 28msec (c) 108msec (d) 80msec [Ans: (a)] Consider a processor with 64 registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and a twelve-bit immediate value. Each instruction must be stored in memory in a byte-aligned fashion. Ifa program has 100 instructions, the amount of memory (in bytes) consumed by the program text is [Ans: (500)] © Copyright @ wow madeeasypublications.org16 | Compute Puter Sclence & IT » Computer Organization and Architecture To. a GH2 clock frequency processor, uses ferent h ee perand accessing modes shown Operand Accessing Mode [Frequency (%) Register pc 720mEee| Inmmediate 20 Direct 20 Memindirect 10 Indexed 7 Auto indexed IE 13 ‘Assume that 4 cycles consumed for memory reference, 2 cycles consumed for arithmetic computation and 0 eycles consumed when the operands in register or instruction itself. What is the average operand fetch rate ofthe processor (@) 290million words/sec (b) 294,11 million words/sec (©) 394,11 milion words/sec (d) 390.26 milion words/sec [Ans: (b)] 10. Consider the following program segment used fo execute on a hypothetical processor. LOAD f.() i 4 —MUloll hb ADD hip i AEAtB Ig AND he | -G88R ty ADD 4 3 8RBtS Js LOAD (9), ; Mifoll-% Jy SUB 4 5 AEN-G oly HALT ; HALTS Ig OR Hh ; ei Jy ADD yh 3 Foe Ro+h, In the processor, data transfer operations are 64 bit instruction ALU operations are 32 bit instructions and branch instruction are 16 bit instructions, (doo @ ian, '4 ASV 3OVW 61 Jenew yoofang iyolA 3 2 a 5 5 2 g 3 = 3 3 3 = g § 2 8 3 g 2 10 Hed ON 1Yleg MeN ‘su 111. 712. MADE En, Publican . been loaded in the memo, Program has : wit Promng across of 2000 JeciTl One, a staring pts occured UN he execu x he halt instruction what Could be the rep .d onto the stack, m address pushe' 2032 (a) 2034 a 2006 (0) 2007 u [Ans; (by atch List| with List and select the oy using the codes GIVEN BOI th List-I ; AA. Indirect addressing B, Indexed addressing C. Base register addressing List-ll 4. Array implementation 2. Writing relocatable code 3. Passing array as parameter Codes: ABC @3 12 ) 2 3 1 321 @13 2 TAns: (a)) ‘A1-address machine and 2-address maching executes the instructions to compute X = (A, Bx C)/(D-E xF), The instructions available for 1-address machine is LOAD, STORE, ADp, ‘SUB, MUL, and DIV. The instructions available for 2-address machine is MOV, ADD, SUB, MUL and DIV. How many extra instructions required by 1-address machine compared to 2-address machine? (a2 (8 (b) 5 @ 11 [Ans: (a)]Ol Care ree ence, Multiple Choice Questions Q.1. Which of the following is true for micro- programmed control unit? (@) The logic of the control unit is specified in memory. (0) For some sequence of control signal there cannot be any micro-programmed control unit. (c) Hardwired control unit is slower in execution as compared to micro-programmed control unit. (d) For some control signal sequence there cannot be any hardwired control unit. Q2 A particular parallel program computation tequire 200 seconds when it is executed on a single processor. If 40% of this computation is “inherently sequential” then what are the theoretically best elapsed time for this program running with 2 and 4 processors respectively? (@) 80 and 120 seconds (b) 90 and 60 seconds (©) 140 and 110 seconds (d) 100 and 80 seconds Q. e Consider a system with 24 bits wide control memory. Every microinstruction is 24 bits long and divided into two parts, control and address. Control part is further divided in to two parts, micro-opcode and flag selection. Micro-opcode field is 11 bits long and specifies the micro-operation to be performed. Flag uo|sstuved UenM e\n ino\RA UO} KU UI pesilan 10 Peanposdes oq BW yood SIM Jo Ved ON ‘Wed MEN ‘suOREOgNd ASV SAY Ot eHEUII0e/ang BUBUAKEO 2 S 2 a CPU Design Selection field used to select a flag for the Purpose of finding next address depend on value of one selected flag. There are 16 flags. Consider following statements for above control memory: S,:Maximum size of control memory is 1536 bytes. , : Flag selection field is 4 bits long, Which of the following is true? (@ Only §, is correct (6) Only S, is correct (©) Both §, and S, are correct (4) Neither S, nor Sis correct The general configuration of the micro- programmed control unitis given below: External Conditions INext Address| Generator ‘Next Address Information What are blocks B and C in the diagram respectively? (@) Block address register and cache memory (b) Control address register and control memory (©) Branch register and cache memory (d) Control address register and random access memory Consider a 5 GHz clock frequency processor used to execute the following program segment. on a processor. ©Copyright : MADE EASY ® wow.madeeasypublications.orgchit 18 | Computer Science & IT © Computer Organization and Ar 7, MI(4001] neni ry MILS001 retells 1,:MOVr,, @ 500 ly: DIViyr, Each memory references and ALU ee Consumes 3 cycles and 1 cycles respec’ Ve The total time required to complete the Pros execution is (@) 8.4 ns (0) 7.33 ns (©) 15.62 ns (@) 11.8.ns Consider two different implementations of the same instruction set architecture, P, and F. Processor P,runsona clockrate of 1.5GHz and runs on 25 GHz, There are four classes of instructions A, 8, C and D. The CPI's of each implementation are given in the following table. Class B | Class C | Class D 2 3 4 2 2 2 50% | 30% Q6 Class A — errsotF, | 1 CPIsofP, | 2 [Frequency [10% Given a program with 10° instructions divided into 4 classes according to the frequencies in the above table. Choose the correct statement from the following, @) P, is faster than P, (0) P, is faster than Ph (©) P, is same as Ps (0) None of these 10% -™ mADE eee tecture tion : () 20 bits (@ 17 bits (d) 32 bits () 22 bits der the following statements; Consi ‘wired control unit design is not rif i ip design and testing places, le ppeortal micro programmed cont) a + Fesignis implemented USING Sum ofp, expression on a flip-flops. uot +: Vertical micro programmed control unit fe Si high degree of the parallelism with, to horizontal -program control unit Inthe control unit design control signa, 3 represented in aencoding formavdecgg a format/SOP format. 9 of the following statements arg Which of (@ §, only S, only (b) S, and S,, $3 only (© S, and S, only (SS and S, Consider the following n-program: Deo Qg 1, : MAR < IR[Addr] 7,: MBR <— M[MAR] T,: ALU MBR Which of the following operation is Performeg by above u-program? (a) Instruction fetch (b) Direct operand fetch (c) Interrupt sub program initiation (d) Indirect operand fetch Q.10 Consider a micro Program control unit and list of. Corresponding Properties in control unit: design: Micro Program control unit ' P. Horizontal yp Control unit Q. Vertical 1 Contro} unit Properties iy coat Signals are in decoded binary format ll) Control Signals are in e it M) Ncoder (iy Shorter Contro| Word ba pdierne Control Word Vv) Low meee Of parallelism ©9'€e Of parallelismPublications Which of the following is the correct match between the Micro program control unit and their properties? (a) (P -1, 4, 6) and (Q -2, 3, 5) (b) (P -1, 4, 5) and (Q -2, 3, 6) (©) (P -2, 4, 6) and (Q -1, 3, 5) (A) (P -2, 3, 6) and (Q -1, 4, 5) Q.11.A typical vertical micro instruction format is characterized by (@) limited encoding with limited parallelism (0) limited encoding with high degree of parallelism (©) high degree of encoding with high degree of parallelism (d) high degree of encoding with limited parallelism Common Data for Question 12, 13 and 14: Consider the following data path of CPU: fran] [we Aly The ALU, the bus and all the registers in the data path are of identical size. All operations including increment of the PC and the GPR are to be carried out in the ALU. Two clock cycles are needed for memory read operation the first one for loading address in the MAR and the next one for loading data from the memory but into the MDR Q.12 The instruction “add 1, r," has the register transfer interpretation Ay & Ry + R, the minimum number of clock cycles needed for execution cycle of this instruction is (@) 2 () 3 (4 (d) 5 Q.13 The instructions “call R,, Sub” is a two word instruction. Assuming the PC is incremented © Copyright : MADE ERSH INS AUBUAdoD @ nd ASVa 3avN 01 40 Peonpoides 8q Kew 400d 814) Jo 11ed ON “I418q MeN “suo) ‘VOIssIUHed LoNUm ey) InoYIM WHO} AUB UI pO: Q.14 Qi a Q.16 Q.17 warciane | 19 during the fetch cycle of the first word of the instruction. Its register transfer interpretation is RA PC +1; PC MPC]; ‘The minimum number of CPU cycles needed during the execution cycle of this instruction is @2 (bo) 3 () 4 @ 5s The instructions “call Ri, Sub” is a two word instruction. Assuming the PC is incremented Guring the fetch cycle of the first word of the ‘instruction. Its register transfer interpretation is RA PC +1; PCeMIRyI: The minimum number of CPU cycles needed during the execution cycle of this instruction is (@ 2 ) 3 4 @ 5 Consider a CPU where all instructions require 7 cycles to complete operation. There are 140 instruction in instruction set. Itis found that 125 control signals are needed to be generated by the control unit. While designing the horizontal micro programmed control unit. Single address field format is used for branch control logic. What is the minimum size of the Control word and control address register (=) 125,7 (b) 125, 10 (c) 135,9 (@) 135,10 Amicro programmed control memory supports 256 instructions. Every instruction an average consume 8 micro operations. The system supports 16 flag conditions and 48 control signals, If the horizontal micro programming is used, what is the size of each control word let 1 address control instruction is used. (@) 61 bits (b) 63 bits (0) 6 bits (d) 8 bits The control field of 1-address control word has to support 2 groups of control signals. In the group-1 it is requires to generate either 1 or none of the 63 control signals. In the group-2 at most 4 from the remaining. What will be the minimum number of bits needed for control field. @ www madeeasypublications orgPee 20 | Computer Science & IT © Computer Organization and Architecture (b) 10 @ 81 (@) 6 () 67 Q.18 A hard wired CU uses 10 control signals 5; 10 Sip in various times steps T, to Ts implement 4 instruction J, to J, as shown below: qh Ty Ty St $3.55 Sy57 Sy $3555 55557] Ss_| S153555 | 5750-510 | $2565 S183 $483.55 | S2,S6S7 S10. So Which of the following pairs of expression’ represent the circuit for generating control signals S, and S,. respectively (@) FATT Ble) Ta To45 0) Tegal eB Ce) Ten err Tent Tete (a) Tg Bln ot TSH tat et1075 @.19 ACPU has only three instruction I, fp ad fy Which uses the following signals intime steps 15 $3.50. S10. Te S2.S4iS6, SeSoSi0 Bi Ti Gy Bos On Ty: Ane Bn Ty: Zoe An Ty? Bey Cou T,: End Jy: Ty: Dm Aaa Ty Ay Boa Ty: Za An Ty Ze An 7, End Which of the following logic functions will generate the hard wired control for the signal A,, T+ Tet Teh + Ts OT Ty T+ Th OUT, + TM #14 T+ Te UT, + T+ (7,474 +7, © Copyright : MADE ERSY —— Paton EAsy merical Answer Type Questions Nu! oo ae) a.20 Considerah thetical contol Unit that supp “5 groups of mutually exclusive Control signay. ‘Aiso assume that group-1 and grOUup-2 are usin, programming whereas; tou, horizontal micrO- 3,4andSareusing vertical micto-programmin The total number of bits used for contro} Words are —— [eccie| a GaN Ns common Data for Question 21, 22 and 23: ‘Apne cock oye Processors CONSUMES 4 Cele An U operations, 3 cycles for branches and 5 cyl for memory operations. The relative frequencies of 5%, 15% and 40% respective, fang AYBUASED @ Wed ON “1ulea MON WWI8Q MeN ‘suoteoliang Asya aq¥W ol ienew these operations are 45° 0.21 Whatis the average instruction execution ing {innano seconds)? & (22 Whatis performance in MIPS? © @.29 the program contains 40° instructions. What < is the program execution time (in sec)? z 3 Q.24 The instruction mix in an application ang g instruction execution speed of a hypothetical machine are shown below: Instruction Speed (cycle) Occurrence (%) ADD 8 0 SHIFT 4 2» LOAD 12 0 STORE 12 2 Ifthe clock frequency is 2.3 GHz, the machine performance in MIPS is Common Data for Question 25, 26 and 27: The micro instructions stored in the control memory of a processor have a width of 26 bits. Each micro instruction is divided into three fields: a micro operation field of 13 bits, a next address field (X) and a MUX select field (Y). Three are 8 status bits in the inputs of the MUX. *Wo|ssjuised ue nu AIIM OL INOUNIM wos Aue Ul pest 18.40 peony @ ym madeeasypublications°9——Pblications — 0.25 How many bits are there in x? Q.26 How many bits are there in Y? Q.27 Whatis the size of the control memory in number of words? Q.28 A control unit has to be support 8 groups of mutually exclusive control signals. What will be the minimum number of bits saved with respect tohorizontal micro programming, Group | Gi] G2] G3] G4 laa cs {i[3][6[7 13/3 [4 & 1 Q.29 Which of the following is true about horizontal micro-instruction? (@) It has high degree of parallelism, (b) Slower execution than vertical micro- instruction. (©) Longer control word than vertical micro- instruction. (6) Control signal is expressed in decoded binary format, Q.30 Which ofthe following statements are incorrect? (@) Operating speed of vertical micro- Programming is higher than that of horizontal micro-programming. (b) Horizontal micro-programming needs ‘signal decoders, *Uolssiuied Ueliim oui nou WHO} KuP U1 pesiilin 40 peonpoide) eq KEW H00d 614) JO Ed ON “141eq MEN ‘SUONBo}Iand ASV 3QYW 01 JeneW i9e/ang “iuBUAdeD © (©) Invertical micro-programmed control unit. For 215 instructions 10 bits are required to represent y-operation if each instructions require 6 clock cycles. (0) None of these Q.3' Inthe computer system design control signals. are represented in formats. (@) SOP expression (b) Encoded binary (©) Decoded binary (0) Hierarchial code Q3i 8 In the control memory, which of the following ‘re common micro-programs in the instruction processing. (@ Process data (6) Instruction fetch (©) Operand{etch (@) Instruction decode Qs 3 Consider the following statements. Identify the correct statements. (@) In the vertical yprogramming multiple function codes are used to represent multiple control signals in the instruction. (b) In the horizontal uprogramming multiple function codes are used to represent multiple control signals in the pinstruction, (©) In the horizontal pinstruction design, multiple control signal are enabled by Coding multiple 1's in the control field of a instruction. (4) In the vertical yprogramming, degree of parallelism is increased by using the ‘multiple function codes in the control field of apinstruction, Try Yourself A benchmark program is run on an 80 MHz processor, The executed program consists of 1,00,000 instructions with the following instruction mix and clock cycle count. a ©Copyright : MADE EASY neo ee @ wornimadecasypublcaions.org