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Nano Lab Solar Cell Final

This report details the fabrication process of heterojunction silicon solar cells using Hot-Wire Chemical Vapor Deposition (HWCVD) technology, including substrate preparation, deposition system configuration, layer deposition sequence, and metallization process. It also presents material properties and extracted solar cell parameters, highlighting key metrics such as open-circuit voltage, short-circuit current density, and efficiency calculations. The final results indicate a maximum power output of 0.624375 mW and an efficiency of approximately 3.89%.

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0% found this document useful (0 votes)
18 views7 pages

Nano Lab Solar Cell Final

This report details the fabrication process of heterojunction silicon solar cells using Hot-Wire Chemical Vapor Deposition (HWCVD) technology, including substrate preparation, deposition system configuration, layer deposition sequence, and metallization process. It also presents material properties and extracted solar cell parameters, highlighting key metrics such as open-circuit voltage, short-circuit current density, and efficiency calculations. The final results indicate a maximum power output of 0.624375 mW and an efficiency of approximately 3.89%.

Uploaded by

122301002
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Heterojunction Silicon Solar Cell

Fabrication Report
Aditya Gupta
122301002
April 27, 2025

Introduction
This report documents the fabrication process of heterojunction silicon solar cells using
Hot-Wire Chemical Vapor Deposition (HWCVD) technology. The complete characteri-
zation and analysis will be presented in a subsequent report.

1 Fabrication Process
1.1 Substrate Preparation
• Substrate Specification:
– Material: n-type crystalline silicon (c-Si)
– Orientation: <100>
– Thickness: 500 µm
– Growth method: Float-Zone
– Resistivity: 1–10 ·cm
• Surface Preparation:
– Initial cleaning: Standard RCA process
– Oxide removal: 2% HF dip for 30 seconds

1.2 Deposition System Configuration


• Cluster Tool Components:
– Load-lock chamber (base pressure: 10−6 Torr)
– 4 HWCVD reactors (for intrinsic/n-type/p-type a-Si:H)
– 1 RF sputtering chamber (for ITO deposition)
• Process Conditions:
– Substrate temperature: 200-300◦ C
– Deposition pressure: 10−2 -10−1 Torr

1
1.3 Layer Deposition Sequence
1. Front-side intrinsic a-Si:H (6-8 nm)

2. n-doped a-Si:H back surface field (20-25 nm)

3. Wafer flip and HF surface renewal

4. Rear-side intrinsic a-Si:H (6-8 nm)

5. p-doped a-Si:H emitter (14-16 nm)

6. Front ITO deposition (90-100 nm) via RF sputtering

1.4 Metallization Process


• Front Contact:

– Pattern: Finger grid design


– Material: Aluminum (1 µm thickness)
– Deposition: Thermal evaporation through shadow mask

• Rear Contact:

– Full-area aluminum back contact


– Thickness: 2 µm

• Post-Metallization Treatment:

– Sample A (Pol. HIT 525 µm): 300◦ C anneal


– Sample B (Pol. HIT 12): No anneal

2 Material Properties

Table 1: Electrical properties of deposited layers

Layer Precursors Conductivity (S/cm) Carrier Conc. (cm−3 ) Mobility (cm


Intrinsic a-Si:H SiH4 5 × 10−10 4 × 1015 —
p-doped a-Si:H SiH4 + B2 H6 + H2 24 4.2 × 1020 0.386
n-doped a-Si:H SiH4 + PH3 + H2 33 2.5 × 1020 0.8
ITO (TCO) Ar + O2 2.5 × 103 3.6 × 1020 43

2
3 Device Characterization Data

(b) Light IV (with background IV from im-


(a) Dark IV proper contact)

Figure 1: Comparison of Dark and Light IV characteristics for Device 1

3.1 Extracted Solar Cell Parameters


Table 2: Combined Solar Cell and Relevant Diode Parameters

Parameter Symbol Significance and Measurement


Photovoltaic-Specific Metrics
Open-Circuit Voltage VOC Measured at zero current under illumination
2
Short-Circuit Current Density JSC Photocurrent
 at zero bias (typically in mA/cm )
VM P P ×JM P P
Fill Factor FF VOC ×JSC
× 100%
Common PN-Junction Parameters
Series Resistance Rs High-current slope of IV curve (Ω·cm2 )
Shunt Resistance Rsh Low-voltage slope of reverse IV (Ω·cm2 )
Saturation Current I0 Dark reverse leakage current density
Junction Capacitance Cj Measured at reverse bias (typically pF)

Table 3: Parameters Extracted from Dark and Light IV Curves (Device 1)

Parameter Symbol Dark IV Light IV


Value Value
Saturation Current I0 8.6 ×10−6 A –
Series Resistance Rs 0.34 / 0.78 0.03
Shunt Resistance Rsh 115.51 4.67
Open-Circuit Voltage VOC – 0.46 V
Short-Circuit Current ISC – 10 mA
Maximum Power Voltage VM P – 0.25 V
Maximum Power Current IM P – 6.75 mA
Fill Factor FF – 37.0%
Area A 160.5564 mm2 160.5564 mm2
Power Input (Given) Pin 100mW 100mW
Power Output Pout 0W 0.624375mW
Efficency η – ≈ 3.89%

3
Abbreviations
Abbreviation Definition
a-Si:H Hydrogenated amorphous silicon
BSF Back surface field
c-Si Crystalline silicon
HWCVD Hot-Wire Chemical Vapor Deposition
ITO Indium Tin Oxide
TCO Transparent Conductive Oxide

4 Plots

Figure 2: Light IV characteristics of the fabricated device.

4
Figure 3: Dark IV characteristics of the fabricated device.

Figure 4: Inverted IV plot for detailed diode behavior visualization.

5 Codes
All the codes are here.

5
Drawing: Solar Cell (Contacts)
15.86 mm
1.78 mm

12.99 mm

0.33 mm

Area Calculation
Top rectangle area:

Areatop = 15.86 × 1.78 = 28.2308 mm2

Single rod area:

Areaone rod = 12.99 × 0.5 = 6.495 mm2

Total rods area (7 rods):

Arearods = 7 × 6.495 = 45.465 mm2

Total Area:

Total Area = 28.2308 + 45.465 = 73.6958 mm2

Total Area of Solar Cell:

Total AreaSolar Cell = 234.2522 − 73.6958 = 160.5564 mm2

Efficency Calculations
• Area of the solar cell, A = 160.5564 mm2 = 160.5564 × 10−6 m2

• Fill Factor, F F = 37% = 0.37

• Open-circuit voltage, Voc = 0.25 V

• Short-circuit current, Isc = 6.75 mA = 0.00675 A

• Incident light power density = 100 W/m2

6
Step 1: Maximum Power Output
The maximum power output Pmpp is given by:

Pmpp = F F × Voc × Isc


Substituting the given values:

Pmpp = 0.37 × 0.25 × 0.00675


Pmpp = 0.37 × 0.0016875
Pmpp = 0.000624375 W
Pmpp = 0.624375 mW

Step 2: Input Power


The input power Pin is:

Pin = Irradiance × A
Pin = 100 × 160.5564 × 10−6
Pin = 0.01605564 W

Step 3: Efficiency Calculation


The efficiency η is:
 
Pmpp
η= × 100
Pin
Substituting:
 
0.000624375
η= × 100
0.01605564
η ≈ 3.89%

Final Result:
• Maximum Power Output: 0.624375 mW

• Efficiency: η ≈ 0.389%

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