CHA P TER

Field-Effect
Transistors
5
DDsVp
5 . 1 I N T R O D U C T I O N

three-terminal device used for a variety of appli-

ald.effect transistor (FET) is a
described in Chapters
extent, those of the BJT transistor
that match,
to a large of devices,
c a t ians
ons differences between the two types
there are impOrtant
and 4. Alhough similarities that will be pointed out in
the sections to follow.
here are also many transistors is the fact that the
difference between the two types of
depicted in Fig. 5.la, while the the
The primary JFET
current-controlled device as
RITtransistor is a device as shown in Fig.
5.1b. In other words,
current
Transistor is a voltage-controlled
function of the level of Ig.
For the FET the
5. la is a direct 5.1b.
as shown in Fig.
current Ic in Fig. VGs applied to the input circuit
of the
voltage
will be a function of the circuit is being
controlled by a parameter
the current of the output voltage.
In each case current level and
in the other an applied
case a
circuit-in one
input

lc

(Control current)/p| FET

BIT

(Control voltage) Vas

Figure 5.l (a) Current

controlled and (b) voltage-
controlied amplitiers.
(b)
(a) n-channel and p-chan-
there are
and pnp bipolar
transistors,
keep in
mind that the BJT
Just are npn to
as there transistors. However, it is important conduction level is a
revealing that the device
Cd-ellect prefix bi- unipolar
holes. The FET is
device-the
transi IS a bipolar
a

electronsand hole (p-channel)

conduction.
1argecarriers,
function oftwochar (n-channel)
or
explanation.
We are
electron some
S o l e l y on either
deper deserves
name the magnet to
the chosen metal filings
term "Tield-effecti n
The magnet to
draw
permanent
magnet has
field of the
permanent
all familiar with the ability of a on the part
of
The magnetic an effort
Without the need i contaçt. through
electric field is
lor actual
the magnet
them to FET an
attracted For the
envelope the filing and
short as
possible. conduction path ofthe output
the magne flux lines to be as
control the
present
that will 237
ished by the charge
ges
 and c o n t r olled
il.
between
the controlling
contact

the need
for direct
circuit without second
device with a ramo
df
a
quantities. when
introducing
some of the general char
rac-
tendency
There is
a natural
already
introduced to compare
characteristics ofthe FET
mostimportant
one
similar to it far exceed.
other. One of the
applications
hundred megohms
versus the several
teristics of one impedance. At a level of I to configurations-a
-a very impor
S its high input
resistance levels ofthe
BJT transistor hand, the
systems. On the other
1the typical input of linear ac
amplifier In othee
characteristic in the design to changes inthe
applied signal.
tant
transistor has . much higher
sensitivity
a great deal more for BJTs then
BJT is typically reason, typical ac voltage gains
variation in outputcurrent
words, the applied voltage. For
this
general, FETs are more
same change in In
FETs for the than for FETs.
a great deal than
more
lor BJT amplifiers are
FETs are usually smaller in construction
BJTs, and The construc
temperature stabie than integrated-circuit(IC) chips.
them particularly useful in make them more
sensitive to han-
BIs, making of some FETs,
however, can
tion characteristics
dling than BJTs. the junction field-effect
introduced in this chapter:
Two types of FETs will be iransistor (MOS.
m e t a l - o x i d e - s e m i c o n d u c t o r field-efect
and the
fransistor (UFET) into depletion and enhancement
is further broken down
FET). The MOSFET category one of the most
transistor has become
which are both described. The MOSFET circuits for digi-
types, construction of integrated
devices used in the design and make it ex-
important and other general
characteristics
tal computers. It's thermal stability, element in a typi-
However, as a discrete
tremely popular in computer circuit design. discussed in a later
with care (to be
cal top-hat container, it must be handled
section). been introduced the biasing
Once the FET construction and characteristics have
The analysis performed in Chapter 4
arrangements will be covered in Chapter 6.
of the important equations
using BJT transistors will prove helpful in the derivation
and understanding the results obtained for FET circuits.

5.2 CONSTRUCTION
AND CHARACTERISTICS OF JFETs
As indicated earlier, the JFET is a three-terminal device with one ternminal capable of
controlling the current between the other two. In our discussion of the BJT transistor
the npn transistor was employed through the major part of the analysis and design
sections with a section devoted to the impact of using a pnp transistor. For the JFET
transistor the n-channel device will appear as the prominent device with
and sections devoted to the impact of using a p-channel JFET. paragraphs
The basic construction of the n-channel JFET is shown in
Fig. 5.2. Note that the
major part of the structure is the n-type material that forms the channel
embedded layers of p-type material. The top of the n-type channel isbetween the
through an ohmic contact to the a terminal refered to as the drain connected
lower end of the sane material is connected (D), while the
through an ohmic
contact to a terminal
referred to as the source (S). The two p-type materials áre
the gate (G) terminal. In connected together and to
essence, theretore, he drain and source
connected to the
ends of the n-type channel and the gate to the two layers of are

absence of any applied potentials the p-type material. In the

conditions. The result is
JFET has two
p-n junctions under no-bias
a
depletion
resembles the same region of a diode region at each junction as
shown in
denletion region is that region void under no-bias conditions. RecallFig.
ot free carriers
5.2 that
also that a
and therefore
conduction through the region. unable to support
Chanter 5 Field-Fffect Transictoors
 Ohmic
Drain (D)
n-channel
contacts

DDsV

Gate (G)

Depletion
region Depletion
region

Source (S) Figure 5.2 Junction field-effect

transistor JFET).
care seldom perfect and at times can be
gyofFig. 5.3 does provide.a sense for the JFET control at the gate misleading,
butterminal
the waterandanal-
the
eness of the terminology applied to the
terminals of the device. The source Source
resure
ofwater
can be likened to the
ca pressure
applied voltage from drain to source
establisha floweof water that will
lectrons) from the spigot (source). The "gate," through an Gate
d sicnal (potential), controls the flow of water
applied
(charge) to the "drain." The
and source terminals are at opposite ends of the n-channel as
drain
introduced in
Fg. 5.2 because the terminology is defined for electron flow.
Drain

Vcs =
0V, VDs Some Positive Value Figure 5.3 Water analogy for
the JFET control mechanism.
In Fig. 5.4 a positive voltage Vps has been applied across the channel and the gate has
heenconnected directly to the source to establish the condition Vos = 0V. The result
is a gate and source terminal at the same potential and a depletion region in the low
end of each p-material similar to the distribution of the no-bias conditions of Fig. 5.2.
The instant the voltage VpD (= Vps) is applied, the electrons will be drawn to the
drain terminal, establishing the conventional current Ip with the defined direction of
Fig. 5.4. The path of charge flow clearly reveals that the drain and source currents are
is
cquivalent (p =1s). Under the conditions appearing in Fig. 5.4, the flow of charge
n-channel between
Telatively uninhibited and limited solely by the resistance of the
drain and source.

+
n-channel
Depletion
region

G VpD
Vps

Vos=0V

JFET in the Vas

=

Figure 5.4
OV and VpsOV.

of JFETs
209
Characteristics
Construction and
5.2
 wider near the top of both p-tvne
depletion region is
+2V
It 1s important to note that thc
best described throuph
in width of the region is
materials. The reason for thec change in the n-channel, the resistance of
help of Fig.
the channcl 5.5. Assuming a uniform resistance
the can be broken down to thc divisions appearing in Fig. 3.5. The current 1
will establish the voltage levels through the channel as indicated on the same figure
material will be reverse-biased
Vs 2 V The resuit is that the upper region of the p-type
by about 1.5 V, with the lower region only reverse-biased by 0.5 V. Recall from
G0A
the discussion of the diode operation that the greater the applied reverse bias, the
0 5 Vi
wider the depletion region-hence the distribution of the depletion region as shown
in Fig. 5.5. The fact that the p-n junction is reverse-biased for the length of the
V channel results in a gate current of zero amperes as shown in the same figure. The
fact that IG 0A is an important characteristic of the
=
JFET.
Figure 5.5 Varying reverse-bias As the voltage Vos is increased from 0 to a few volts, the current will increase
potentials across the p-n
junction as determined by Ohm's law and the plot of Ip versus Vps will appear as shown in
ol an n-channel JFET. Fig. 5.6. The relative straightness of the plot reveals that for the region of low values
otDs.the resistance is essentially constant. As Vps increases and approaches a level
reterred to as Vp in Fig. 5.6, the depletion regions of Fig. 5.4 will widen, causinga
noticeable reduction in the channel width. The reduced path of conduction causes the
esistance to increase and the curve in the graph of Fig. 5.6 to occur. The more
horizontal the curve, the higher the resistance,
suggesting that the resistance is ap-
proaching "infinite'" ohms in the horizontal region. If VDs is increased to a level
where it appears that the two
a condition referred
depletion regions would "touch" as shown in Fig. 5.7,
to as
pinch-off
condition is referred to as the
will result. The level of Vps that establishes
this
5.6. In
pinch-off voltage and is denoted by Vp, as shown in
Fig.
actuality, the term *pinch-off" is a misnomer in that it
current IpD is pinched off and drops to 0 A. As shown in suggests that the
hardly the case-Ip maintains a saturation level defined as Fig. 5.6, however, this is
a
very small channel still exists, with a current Ipss in Fig. 5.6. In reality
of very high
and maintains the saturation density.
does not drop off at The fact that Ip
is verified by the
pinch-off level indicated in
following fact: The absence of a drain current would Fig. 5.6
possibility different potential levels through the
of remove the
varying levels of reverse bias
n-channel material to establish the
depletion region distribution along
the p-n
that caused
junction. The result would be a loss of the
pinch-off in the first place.

D
Pinch-off

pss Saturation level

Vas 0V
Increasing resistance due
Vxs V
to narrowing channel

Gs=0 V

n-channel resistance

V
Vps
Figure 5.6 Ip verss Vps for Vos = 0v.
Figure 5.7 Pinch-off (Vos =
OV, Vps
210 Chapter 5
Field-Efect Transistors
=
Vp).
 DosN
the region of close encounter between the two
As Vns is increased beyond Vp.
injetion regions will increase in length along the channel, but the level of Ip remains
nally the same. In essence. therefore, once VpDs>Vp the JFET has the charac-
spcS of a current source. As shown in Fig. 5.8, the current is fixed at Ip = Ipss.
Load
levels> Vp) is detemined by the applied load.
the voitage Vps (for
The choice of notation inss is derived from the fact that it is the Drain-to-Source
source. As we continue to investi-
a Short-circut connection trom gate to
with
Tent
characteristacs of the device we will find that:
gate the Figure 5.8 Current source
JFET and is defined by the condi-
Ins is the maximum drain current for a equivalent for Ves = 0V,

tionsVas =0V and Vps>|Vp VDsVp

Note in 5.6 that Vas
Fig. 0 V for the entire length of the curve. The next few
=

how the characteristics of Fig. 5.6 are affected by changes in

raragraphs will describe
the level of Vas

Vos O V

The voitage from gate to source, denoted VGS, is the controlling voltage of the JFET.
for
Just as vanious curves for Ic versus VcE were established for different levels of I
the BJT transistor, curves of lp versus Vps for various levels of Vos can be developedd
for the JFET. For the n-channel device the controlling voltage Vos is made more and
its Vas=0 V level. In other words, the gate terminal will be set
more negative from
at lower and lower potential levels as compared to the source.
between the gate and
In Fig. 5.9 a negative voltage of -1 V has been applied
source terminals for a low level of Vps. Theeffect of the applied negative bias Vas is
to establish depletion regions similar to those obtained with Vos = 0 V but at lower

levels of VDs. Therefore, the result of applying a negative

bias to the gate is to reach
the saturafion level at a lower level of VDs as shown
in Fig. 5.10 for VGs= -1 V.
The resulting saturation level for Ip has been reduced and in fact will continue to
Note also on Fig. 5.10 how the
decreaseas VGs is made more and more negative.manner as VGs becomes more and
pinch-off voltage continues to drop in a parabolic negative to
more negative. Eventually, Vs when will be
VGs =-Vp sufficiently
establish a saturation level that is essentialy 0 mA, and for all practical purposes the
device has been *turned off." In summary:

G=0A
g Vas0V

Vos-1 V

Figure 5.9 Application of a

voltage to the gate ot a

negative
JFET.
211
5.2 Construction and Characteristics of JFETs
 vahes
pinch-off
(mA) Locus of

Saturation Region
Ohmic Vas-0 V
Region

-1 V

Gs=-2 V

os3v
os-4V=,

25
Vos(V
15 20

V,(for VosOV) -4V.

8 mA and Vp
=

Ipss
=

characteristics with
igure 5.10 n-Channel JFET

by Vos= Vp,
with Vp
that results in 1p =
0 mA is defined
The level of Vos voltage for n-channel devices and a positive voliage for
being negative
a

p-channel JFETs.
as VGSofn rather
the pinch-off voltage is specified
On most specification sheets, when the primary
sheet will be reviewed later in the chapter
than Vp. A specification the right of the pinch-off
introduced. The region to
clements of concern have been
linear amplifiers (amplifiers
of 5.10 is the region
Fig. typically employed in referred to as the
locus applied signal) and is commonly
with minimum distortion of the
constant-current, saturation, or linear amplification region.

Voltage-Controlled Resistor
5.10 is referred to as the ohmic or
The region to the left of the pinch-off locus of Fig.
the JFET can actually be em-
voliage-controlled resistance region. In this region
control system) whose
ployed as a variable resistor (possibly for an automatic gain
resistance is controlled by the applied gate-to-source voltage. Note in Fig. 5.10 that
the slope of each curve and therefore the resistance of the device between drain and
sourcefor Vps<Vp is a function ofthe applied voltage Vas. As Vos becomes more
and more negative, the slope of each curve becomes more and more horizontal,
corresponding with an increasing resistance level. The following equation will pro-
vide a good first approximation to the resistance level in terms of the applied voltage
Vos
(5.1)
a(1-VasVp
where r, is the resistance with Vas =0 V and ra the resistance at a particular level of
Vos
For
an n-channel JFET with r, equal to 10 ksN (VGs =
0 V, Vp -6 V),
(5.1) will result in 40 kl at Vos = -3 V.
=
Eq.

p-Channel Devices
The p-channel JFET is constructed
exactly the same manner as the n-channel
in
device of Fig. 5.2 with a reversal of the p- and n-type materials as shown in Fig. 5.11.
Chapter 5 Field-Effect Transistors
 ppsV

VpS
VpD

Figure 5.1l p-Channel JFET.

are the actual polarities for the

volt
The defined current directions are reversed, as increas-
the p-channel device the channel will be constricted by
ages Vcs and Vps. For notation for Vps
from gate to source and the double-subscript
ing positive voltages
characteristics of Fig. 5.12, which has
will result in negative voltages for Vps on the
of Vos +6 V. Do not let the minus signs
an Ipss of 6 mA and a pinch-off voltage
=

the source is at a higher potential than

for Vps throw you. They simply indicate that
the drain.

(mA)

VGs-0V

Vos=+1V
Breakdown
VGs+2 V region

VGs+3 V
Vos+4
V VGs= +5 V

-10 -20 -25

Figure 5.12 p-Channel JFET characteristics with lpss =

6 mA and V= +6 V.

rise to levels that seem un-

Note at high levels of Vps that the curves suddenly
breakdown has occurred and the
an indication that
bounded. The vertical rise is
Current through the channel (in the same
direction as normally encountered) is now
5.10 for the
limited solely by the external circuit. Although not appearing in Fig.
n-channel
n-channel device, they do occur. for the level of
device if sufficient voltage is
applied. This region can be avoided if the Vps, is noted on the specification
is such that the actual level of Vps is less than this value for all
sheet and the design
values of Vas.
213
5.2 Construction and Characteristics of JFETs
 Symbols JFETS are provided in Fie
n-channel andp-channel
n-channel device of Fig. 5. 13a to
The graphic symbols for the
in for the
were forward-biased. For the
.15. Note that the arrow is pointing
flow if the p-n junction
would is the direction ofthe
represent the direction Ig difference in the symbol
P-channel device (Fig. 5.136) the only
arrow

Vps Vps

VGS VGs

Figure 5.13 JFET symbols: (a)

(b) n-channel (6) p-channel.
(a)

Summary
A number of important parameters and relationships were introduced in this section.
A few that will surface frequently in the analysis to follow in this chapter and the next
for n-channel JFETs include the following
The maximum current is defined as Ipss and occurs when Vas = 0 V and

VpsVPl as shown in Fig. 5.14a.

For gate-to-source voliages Vcs less than (more negative than) the pinch-off
level, the drain current is 0 A (lp = 0 A), as appearing in Fig. 5.14b.

For all levels of Vos between 0 V and the pinch-off level the current Ip will
range between Ipss and 0 A, respectively, as reviewed by Fig. 5.14c.
For p-channel JFETs a similar list can be developed.

D
+ Vos-VoG
pIpss VoD2V p 0A
Vos 0V VGs
No Vos

Vocl2iV
(a)
(b)

Vol2ocl20V
D
OmASlpss
D
VpD
VoaVos Figure 5.14 (a) Vos= 0V,
Ip Ipss: (b) cutoff
VGs less than the
(lp= 0 A)
(c) pinch-off level
Io exists between 0 A
and
torVcs less than or equal to 0lpss
V
and greater than
the pinch-off
level.
Chapter 5 Field-Effect Transistors
 IDDs
.3 TRANSFER CHARACTERISTICS
perivation
For the BJT transistor the output current c and input controlling current I were
related by beta, which was considered constant for the analysis to be performed. In
equation form,

control variable

Ie-) (5.2)

constant
In Eg. (5.2) a linear relationship exists between Ic and Ig. Double the level of I and
le will increase by a factor of 2 also.
Unfortunately, this linear relationship does not exist between the output and input
quantities of a JFET. The relationship between Ip and Vos is defined by Shockley's
equation:

control variable

(5.3)
constants-
The squared term of the equation will result in a nonlinear relationship between Ip and
Vas. producing a curve that grows exponentially with increasing values of Vas
For the dc analysis to be performed in Chapter 6 a graphical rather than mathemat-
ical approach will in general be more direct and easier to apply. The graphical ap
proach, however, will require a plot of Eq. (5.3) to represent the device and a plot of
the network equation relating the same variables. The solution is defined by the point
of intersection of the two.curves. It is important to keep in mind when applying the
network in
graphical approach that the device characteristics will be unaffected by the
which the device is employed. The network equation may change along with the
intersection between the two curves, but the transfer curve defined by Eq. (5.3) is
unaffected. In general, therefore:
The transfer characteristics defined by Shockley's equation are unaffected by
the nerwork in which the device is employed.
The transfer curve can be obtained using Shockley's equation or from the output
characteristics of Fig. 5.10. In Fig. 5.15 two graphs are provided with the vertical
Figure 5.15 Obtaining the
(mA) (mA) transter curve from the drain
10 10 characteristics.

9 9 - Vas=0V
DSS8-8Eoss
A 7

-Vas-1 V

-Vas=-2 V
VGs-3 V
Vas-4 Vv
L
VGs (V)-4 -3
10 15 25 Vps
p=OmA, VGs = Vp

215
5.3 Transfer Characteristics
 above is sufficiens
the equations
of cach of Recall that Vae
of the impact configurations.
A clear understanding of de
complex
the most conliguration. Similarly
background to approach analysis
an of a BJT ofa lFETconfigura
key the to initiating for the analysis
.VWasoften the starting point to be determined
condition I - 0 A is often the first parameter
the In is normally between the analysis of
For the BJT configuration, number of
similarities
on it is normally Va
The 6.
apparent in Chapter
For the JFET
JFET dc configurations
will become quite
BJT and

5.7 DEPLETION-TYPE MOSFET

are two types

of FETs: JFETs and MOS
introduction, there enhancement type
noted in the chapterfurther broken down into depletion type and
As while the
FETs. MOSFETs are enhancement define their basic mode of operation,
terms depletion and ransistor. Since
The metal-oxide-semiconductor-field-effect

MOsFET stands for each type of MOSFET

Tabel differences in the and operation of
characteristics
there are examine the depletion-type
covered in separate sections. In
this section we
they are characteristics similar to
those of a JFET between
MOSFET, which happens to have characteristics that
added feature of
Cutoff and saturation at Ips, but then has the
Cxtend into the region of opposite polarity for Vas

Basic Construction
in
The basic construction of the n-channel depletion-type MOSFET is provided
base and is referred to
Fig. 5.23. A slab of p-type material is formed from a silicon
as the substrate. It is the foundation upon which the device will be constructed. In
Some cases the substrate is internally connected to the source terminal. However,
many discrete devices provide an additional terminal labeled SS, resulting in a four
terminal device, such as that appearing in Fig. 5.23. The source and drain terminals
are connected through metalliccontacts to n-doped regions linked byan n-channel as
shown in the figure. The gate is also connected to a metal contact surface but remains
insulated from the n-channel by a very thin silicon dioxide (Si0,) layer. Si02 is a
particular type of insulator referred to as a dielectric that sets up opposing (as revealed

(Drain)
Si0 n-channel

Metal contacts

(Gale) Substrate
G SS
Substrute

S doped
(Source) regions

Figure 5.23 n-Channel depletion-type MOSFEI

Chapter 5 Field-Effect Transistors

 DDsV
hy the prefix di-) electric ficlds within the dielectric when exposed to an externally
aplied field. The fact that the SiO, layer is an insulating layer reveals the following
app
fact
There is no direct electrical connection between the gate terminal and the
channel of a MOSFET.

In addition:

insulating layer of SiO, in the MOSFET construction that accounts

It is the
for the very desirable high input impedance of the device.
MOSFET is often that of the typical JFET, even
In fact, the input resistance of a
JFETs is sufficiently high for most applications.
though the input impedance of most
continues to fully support the fact that the gate current
The very high input impedance
for dc-biased configurations.
d) is essentially zero amperes metal-oxide-semiconductor FET is now fairly obvious.
The reason for the label
and gate connections to the proper surface-in
The metal for the drain, source,
control to be offered by the surface area of the
particular, the gate terminal and the and the semiconductor for
contact, the oxide for the silicon dioxide insulating layer,
are diffused. The insulating
the basic structure on which the n- and p-type regions
has resulted in another name for the device:
layer between the gate and channel
FET or this label is used less and less in current
1GFET, although
insulated-gate
literature.

Characteristics
Basic Operation and
volts by the direct connection
In 5.24 the gate-to-source voltage is set to zero
Fig. across the drain-to-sourcee
from one terminal to the other, and a voltage Vps applied
is
at the drain by the free
terminals. The result is an attraction for the positive potential
similar to that established through the channel
electrons of the n-channel and a current to be labeled
=0V continues
JFET. In fact, the resulting current with Vos
of the
pSS. as shown in Fig. 5.25.
D

SS
G VpD

Vos=0V

p Is =lpss

5.24 n-Channel depletion-type MCSFET with Vos= 0V

Figure
and an applied voltage Vpp.
225
5.7 Depletion-Type MOSFET
 p (mA)
-Vs+1V

Depletion 10.9
=0V
Enhancement

mode mode
-

Vas
pss

-Vas-1V

-Vos-2 v
DSS
2 as -3 v
pSS
4 sv
Vos
s VGs V=-6V
-6 -5 4 -3 -21-1 0
0.3v,
MOSFET
for an n-channel depletion-type
characteristics
igure 5.25 Drain and transfer

such as -1 V. The negative

5.26, Ves has been set at a negative voltage
In Fig. electrons toward the p-type
substrate (like
at the gate will tend to pressure
polential substrate (opposite charges attract)
charges repel) and attract holes from the p-type of the negative bias established
shown in Fig. 5.26. Depending on the magnitude
as electrons and holes will occur that will re-
by Vos, a level of recombination between
duce the number of free electrons in the n-channel
available for conduction. The
more negative the bias, the higher the rate of recombination. The resulting level of
drain current is therefore reduced with increasing negative bias for Vos as shown
in Fig. 5.25 for Vcs = -1 V, -2 V, and so on, to the pinch-off level of -6 V. The
resulting levels of drain current and the plotting of the transfer curve proceeds
exactly as described for the JFET.

SiO2 layer ,n-channel

Recombinarion
process

G- P-material
ubstrate

Holes attracted
Metal to negative
contact potential at gate

Electrons repelled
by negative Figure 5.26 Reduction in free
potential at gate carriers in channel
ive
due to a nega-
potential at the gate terminal.
For positive values of VGs the positive
carriers) from the p-type gate will draw additional
substrate to the reverse leakage currentelectrons (free
new carriers through the collisions due
resulting between
gate-to-source voltage continues to increase
and establish
accelerating
veals that the drain current will increase at a in the positive particles. As the
rapid direction,
rate for the Fig. 5.25 re-
reasons 1listed above.
Chapter 5 Field-Effect Transistors
heVertical spacing between the Vas 0 V and Vos +1 V curves of Fig. 5.25 is
IDos
lear indieation ot how much the current has increased for the 1 volt change in Vos.
N to the rapid rise, the user must be aware of the maximum drain current rating
Ne it could be exceeded with a positive gate voltage. That is, for the device of Fig.
15. the application of a voltage Vos +4 V would result in a drain current of
m A . which could possibly exceed the maximum rating (current or power) for
the device. As revealed above, the application of a positive gate-to-source voltage has
enhanced" the level of free carriers in the channel compared to that encountered
with Vos=0 V. For this reason the region of positive gate voltages on the drain or
transfer characteristics is often referred to as the enhancement region, with the region
heween cutoff and the saturation level of Ipss referred to as the depletion region.
t is particularly interesting and heclpful that Shockley's equation will continue to
applicable for the depletion-type MOSFET characteristics in both the depletion
and enhancement regions. For both regions it is simply necessary that the proper sign
monitored in the
e included with Vos in the cquation and the sign be carefuly
mathematical operations.

MOSFET with EXAMPLE 5.3

Sketch the transfer characteristics for an n-channel depletion-type
= - 4 V.
Ipss= 10 mA and Vp

Solution
D IDss = 10 mA
At Vos 0 V,
(mA)
I=0 mAA
Vas=Vp = -4 V, 17

VGs
Vas= = =
-2 V, DSS= 10mA
=D8 4
=2.5 mA4 16
15

and at l =
DSS VGs=0.3 Vp
=
0.3(-4 V) =-1.2 V
13

12
all of which appear in Fig. 5.27. increases very
of Vas, keep in mind that Ip 11
Before plotting the positive region be conservative with
values of Vos. In other words,
rapidly with increasing positive In this case, we will DSS 10
substituted into Shockley's equation.
the choice of values to be
try +1 V as follows:
2
Ip=Inss1-s
V
1 0 mA(l +0.25) =
10 mA(1.5625)
10mA1
-

-4
=

15.63 mA
which is sufficiently high to finish the plot.

p-Channel Depletion-Type MOSFET Lo3V

reverse of that
MOSFET is exactly the
depletion-type
The construction of a p-channel substrate and a p-type channel, Figure 5.27 Transter character-
That is, there is now an n-type depletion-
appearing in Fig.
5.23. but all the voltage polari istics for an n-channel

5.28a. The terminals remain as identified, drain MOSFET with lpss l0 mA

as shown in Fig. same figure. The ype
as shown in the and Vp = -4V.
directions are reversed, values, Ip
ties and the current as in 5.25 but with Vps negative
Fig.
characteristics would appear exactly 227
5.7 Depletion-Type MOSFET
 o (mA)
p (mA)
- Vas = -1 V

as 0V

as+1 V
pSS
+2 V
-Vas =

s+3 V

G as 4 V

as+5V
s
Vas o
Vos V +6V

VGs
P
(c)
(a) (b)
MOSFET with Ipss
=
6 mA and Vp=
+6 V,
igure 5.28 p-Channel depletion-type
and Vos having the
the defined direction is now reversed),
positive as indicated (since wili result in a miror
as shown in Fig.
5.28c. The reversal in Vas
Opposite polarities characteristics as shown
in Fig. 5.28b. In
(about the Ip axis) for the transfer in the positive
increase from cutoff at Vas= Vp
image
other words, the drain current will negative values of
continue to increase for increasingly
Gs region to Ipss and then the correct
and requires simply placing
VGs. Shockley's equation is still applicable
sign for both Vas and Vp in the equation.

and Case
Symbols, Specification Sheets,
Construction
MOSFET are provided in
The graphic symbols for an n- andp-channel depletion-type
reflect the actual construction of the
Fig. 5.29. Note how the symbols chosen try to
device. The lack of a direct connection (due to the gate insulation) between the gate
and channel is represented by a space between the gate and the other terminals of the
symbol. The vertical line representing the channel is connected between the drain and
source and is "supported" by the substrate. Two symbols are provided for each type
of channel to reflect the fact that in some cases the substrate is externally available,
while in others it is not. For most of the analysis to follow in Chapter 6, the substrate
and source will be connected and the lower symbols will be employed.

n-channel p-channel
9D
PD
SS
SS

9D
9D

Figure 5.29 Graphic symbols

for (a) n-channel
depletion-type
MOSFETs and (b) p-channel de-
(a) (b) pletion-type MOSFETs.
5 Field-Effect Transistors
Chapter
228
 another point is normally nro
level,
beyond the Ipss (lor an n-channel
however, since lp can
extend
for s o m e positi ve voltage dc with Vne=
valuc of Ip mA

VIded that reflects a typical

5.30, 1, is
specified as Ip(on)
For the unit of Fig.
device).
10 V and Vas= 3.5 V

5.8 ENHANCEMENT-TYPE MOSFET

and mode of operation

between
construction
in
Athough there
are s o m e
similarities
MOSFETs, the
characteristics
of enhance
the
enhancement-type thus far. The transfer
depletion-type and obtained
different from anything cut off unti1
are quite current is now
ent-type MOSFET and the drain
is not defined by Shockley's
equation current control
curve In particular,
voltage reaches a specific magnitude. rather than
the gate-to-source gate-to-source voltage
effected by a positive
an n-channel device is now and n-channel deple
in n-channel JFETs
encountered for
of voltages
tne range negative
tion-type MOSFETs.

Basic Construction
MOSFET is provided i
the n-channel enhancement-type
basic construction on
The and is again referred
is formed from a silicon base
ig. 5.31. A slav p-type
ofmaterial
is sometimes
to as the substrate. As with the depletion-type
MOSFET, the substrate
lead is made
to the while in other cases a fourth
terminal,
internally connected source
terminals are
The source and drain
availablefor external control of its potential level.
contacts to n-doped regions,
but note in Fig. 5.31|
again connected through metallic
This is the primary differ-
the absence of a channel between the two n-doped regions.
MOSFETs
ence between the construction of a depletion-type and enhancement-type
of the device. The Si0, layer is
the absence of a channel as a constructed component
between the drain andd
still present to isolate the gate metallic platform from the region
from a section of the p-type material. In
source, but now it is simply separated
construction of an enhancement-type MOSFET is quite simi-
summary, therefore, the
absence ofa channel between
lar to that of the depletion-type MOSFET except for the
the drain and source terminals.

Si02
n-doped
region

no-channel

Metallic
contacts

P-ype Substrate
Go substrate -oSS

n-doped
region

5.31 n-Channel enhancement-type MOSFET

Figure

Field-Effect Transistors
Chapter 5
 IpDS
and Characteristics
8asic Operation
e is set at 0 V and a voltage applied between the drain and source of the device of
Fig.5.31, the absence of an n-channcl (with its generous number of free carriers) wil
result in a current of cifectively Tero ampcres quite different from the depletion-
voe MOSFET and JFET where i loss. It is not sufficient to have a large accumu-
ation of carriers (clectrons) at the drain and source (due to the n-doped regions) ifa
nath fails to exist between the two. With Vpy some positive voltage, Ves at 0 V, and
erminal SS directly connected to the source, there are, in fact, two reverse-biased p-n
iunctions between the n-doped regions and the p-substrate to oppose any significant
drain and source.
flow between
In Fig. 5.32 both Vps and Vess have been set at some positive voltage greaterthan
zero volts, cstablishing the drain and gate at a positive potentiai with respect to the
sOurce. The positive potential at the gate will pressure the holes (since like charges
repel) in the p-substrate along the edge of the SiO, layer to leave the area and enter
deeper regions of the p-substratc, as shown in the figure. The result is a depietion
near the SiO, insulating layer void of holes. However, the in the
region electrons
p-substrate (the minority carrIers of the material) wili be attracted to the positive gate
and its
and accurnulate in the region ncar the surfacc of the SiO, Jayer. The SiO, layer
insulating qualities will prevent the negative carriers from being absorbed at the gate
terminal. As Vos incrcases in magnitude the concentration of electrons near the Si0,
a measurabie
surface increases until eventually the induced n-type region can upport
in the significant increase
flow between drain and source. The level of Ves that results
in drain current is called the threshold voliaze and is given the synbol Vy. On specif
be used
cation sheets it is referred to VowThy although Vs is less unwieldy and will
as
V and "en
in the analysis to follow. Sine the channel is nonexistent with Vas=0
MOSFET
this type of
hanced by the application of a positive gate-o-ource votage.
is called an enhancement-type MOSFET. Both depletion and enhancement-type
applied to the latter
MOSFETs have enhancement-type regions, but the label was

since it is its only mde of operation

Elecrons trced to psitive zae

Ginhucs nchannel)
Rezjon teieed d p ty
carriers (ties)

Figaee 5 2 Chatnei isemanee

insulaing laye Hoies npeiliest hae miatcz
peMOSEET

58 Eabacen-1Irge MOSEET
 density of
frece arriers in the
carriere

level the
threshold drain current How.
the level
of
drain current.
increased
beyond in an
As Vas is
increased
resulting of Vps.
the will
channel will
increase,
increase
the level depletion-type AfAOS.
induced and J F E T and
the
we hold Vas
constant
o c c u r r e d for
depicted by the
narrow
cver, if level as
saturation process ower
eventually
reach a
due to a
pinching-off
shown in Fig.
.33.
5.3 Applying
off of Ip is channel as
FET. The leveling
the induced M O S F E T of Fig. 5.33 we
drain end of of the
at the terminal voltages
channel law to the
Kirchhoffs voltage
find that (5.11)
oaVp Vos

Pinch-off (beginning)
Depletion region
Si02

lG =0A +

G p-type Vps
substrate

Vas

Figure 5.33 Change in channel

and depletion region with in-
creasing level of Vps for a fixed
value of VGS

If Vos is held fixed at some value such as 8 V and Vps is increased from 2 V to
5 V, the voltage Vpc Iby Eq. (5.11)] will drop from -6 V to -3 V and the gate will
become less and less positive with respect to the drain. This reduction in gate-to-drain
voltage will in turn reduce the attractive forces for free carriers (electrons) in this
region of the induced channel, causing a reduction in the effective channel width.
Eventually, the channel will be reduced to the point of pinch-off and a saturation
condition will be established as described earlier for the JFET and
MOSFET. In other words, any further increase in Vps at the fixed value depletion-type
of Vas will
not affect the saturation level of lp until breakdown
conditions are encountered.
The drain characteristics of Fig. 5.34 reveal that for
the device of Fig. 5.33 with
VGs 8 V, saturation occurred at a level of Vps 6 V. In fact, =

for Vps is related to the level of applied the saturation level

VGs by

VosVos Vr (5.12)
Obviously, therefore, for a fixed value of Vr the
saturation level for Vps. as shown in Fig. 5.33higherthethelocus
level of VGs, the more the
by of saturation levels.

Chapter 5 Field-Effect Transistors

 DosP
o (mA)
Locus of Vps

Vos +8V

Vos= +7 Vv

Vos + 6 V

Vas=+5 V

GS+4V
GS+3 V
15 V 20 V 25 v Vos V=2v os
5V 0V
6 V

Figure 5.34 Drain characteristics of an n-channel enhancement-type

2V and k 0.278 x 103 Av2
=

MOSFET with V7 =

revealed by the fact

5.33 the level of Vr is 2 V, as
For the characteristics of Fig. therefore:
has dropped to 0 mA. In general,
that the drain current
drain current of an en-
For values of Vos less
than the threshold level the
is 0 mA.
hancemeni-type MOSFET
increased from Vr to 8 V, the
5.34 clearly reveals that as the level of Vos
Figure mA to 10 mA. In
increased from a level of 0
saturation level for Ip also
resulting levels of Vos increased as
noticeable that the spacing between the
addition, it is quite increments in drain cur-
increased, resulting in ever-increasing
the magnitude of VGs
rent. related to the applied gate-to-source
For levels of VosVs
the drain current is
nonlinear relationship:
voltage by the following (5.13)
oKVs-Vr
nonlinear (curved) relationship bee
term that results in the of the
Again, it is the squared that is a function of the construction
tween Ip and Vos. The
k term is a constant equation [derived
from
be determined from the following the
device. The value ofk for each at a particular point
can on
are the values
and VoS(on)
Eq. (5.13)] where Ip(on)
characteristics of the device.
(5.14)

GSon) V
Voston) = 8 V from the
characteristics
of Fig
10 mA when
Substituting Ipo)=
5.34 yields
10 mA 10 mA
10 mA
36 v2
( 8 V -2 V (6 V¥
= 0.278 x 10- A/V
of Fig. 5.34 results:
for Ip for the characteristics
and a general equation
I=0.278 x 10(Vas-2 V

5.8 Enhancement-Type MOSFETT

s/V
Substituting Vos =
4 V, we find that

Ip =
0.278 x 10 4 V -

2 V= 0.278 x 10 (2)?
1.11 mA
0.278 x 10(-4)=
as verified by Fig. 5.34. At Vos= Vr the squared term is 0 and Ip = 0 mA.
For the de analysis of enhancement-type MOSFETs to appear in Chapter 6
transfercharacteristics will again be the characteristics to be employed in the the
cal solution. In Fig. 5.35 the drain and transfer characteristics have been set side graphi
side to describe the transfer process from one to the other. Essentially, it proceeds by
introduced earlier for the JFET and depietion-type MOSFETs. In this case, howeveAs
must be remembered that the drain currentis 0 mA for Vos Vr. At this point.
measurable current will result for lp and will increase as detined by Eq. (5.13). Note
that in defining the
points on the transfer characteristics from the drain characteristice
only the saturation levels are employed, thereby limiting the region of operation
levels of VDs to
greater than the saturation levels as defined by Eq. (5.12).

p (mA)
/ (mA)
10
0- GS+8 V
9

-
Vas =+7V

Vos+6 V

Vas +5 V

GS+4 V
o 3 45
8 Vas 0 Gs+3 V
10 15 20 25

Figure 5.35 Vos=V=2v

Sketching the transfer characteristics
ment-type MOSFET from the drain characteristics. for an n-channel enhance-

The transfer curve of

earlier. For an n-channel
Fig. 5.35 is certainly quite different
and does not rise until
(induced) device it is now totally in thefrom those obtained
Vos Vr. The =
positive Vos region
transfer characteristics given the levels ofquestion now surfaces as
to how to
included below for a plot
k and Vs as the
MOSFET:
particular
I =0.5 x
10 (Vas-4 V
First a horizontal line is drawn at
shown in Fig. 5.36a. Next, a level of Ip
0 mA from =

Vas 0V to VGs 4 V as =
=

Vas greater than Vp such as 5 V is chosen and

substituted into Eq. (5.13) to determine the
resulting level of Ip as follows:
Ip 0.5 x
10cs-4 v¥
=
0.5 x
10-(5 V 4 V
-

=
0.5
= 0.5 mA
x
10-2(12

Chapter 5 Field-Effect Transistors

o (mA) Ip (mA)

Vos o 2 3 5 6 7 8
Vos

(b)
(a)

' (mA)

Vr
Vas
(c)
of an n-channel enhancement-
characteristics
5.36 Ploting the transfer
Figure and Vr = 4V.
type MOSFET
with k =0.5 x
10 AN

additional levels
as shown in Fig. 5.36b. Finally,
obtained 6 V,
point on the plot is In particular, at Vas
=

and a
levels of Ip obtained.
of Vos are chosen and
the resulting as shown on
and8 mA, respectively,
is 2 mA, 4.5 mA,
7 V, and 8 V the level of Ip
5.36c.
the resulting plot of Fig.
p-Channel Enhancement-Type MOSFETs
of
is exactly the
reverse
MOSFET
enhancement-type now an n-type
of ap-channel is, there is
The construction
shown in Fig. 5.37a. That
5.31 as The termninals
thatappearing in Fig. under the drain and
source
connections.
directions are re-
substrate and p-doped regions and the curent
but all the voltage
polarities with increasing
remain as identified, Fig. 5.37c,
will appear as shown in
characteristics
values of Vas.
The transfer
versed. The drain negative
from increasingly transter curve of Fig.
levels of current resulting (about the lp axis) of the
the mirror image as shown
characteristics will be
negative values of VGs beyond Vr,
5.35 with lp increasing
with increasingly
are equally
applicable to p-channel
(5.11) through (5.14)
in Fig. 5.37b. Equations
devices. 235
5.8 Enhancement-Type MOSFET
 mA)
mA)
oS6 Vv

Vas=-5V

GS=-4V
Go
Vos= -3V

es -2v
Gs
T
(c)
(a) (b)
0.5 x 10'AN
2Vand k
=

MOSFET with V, =

igure . 3 7 p-Channel enhancement-type

Case
Symbols, Specification Sheets, and
Construction
enhancement-type MOSFETs
are pro-
The graphic symbols for the n- and p-channel construction
to reflect the actual
vided as Fig. 5.38. Again note how the symbols try
source was chosen to
reflect the fact
of the device. The dashed line between drain and
no-bias conditions. It is, in fact,
that a channel does not exist between the two under
the only difference between the symbols for the depletion-type and enhancement-type
MOSFETs.

n-channel P-channel
D 9D
SS SS

Figure 5.38 Symbols for (a)

n-channel enhancement-type
MOSFETs and (b) p-channel en-
(a) (b) hancemen-type MOSFETS
The specification sheet for a
Motorola n-channel
provided as Fig. 5.39. The enhancement-type MOSFET is
construction and terminal
case
Dext to the maximum
ratings, which now include a maximum
identification are provided
30 mA dc. The specification sheet drain current of
provides the level of Ipss
under
which is now simply 10 nA de (at
Vos= 10 V and Vas 0 V) *off" conditions,
=
milliampere range for the JFET and compared to the
depletion-type MOSFET. The threshold
voltage
Chapter 5 Field-Effect Transistors
 IILS the to
y s I e m . 1 h e
shorun
possibility ot appiying be inserted in the
With the ring the device. a
esh- minals of
maintained at 0 V.
V At the
potential across any
potential difference
very least always between
touch ground toany two
ermunals i s

the ccumulated statio

atic charge
before
discharge of
by the casing handling the device, and permit
always
t r a n s i s t .

thechen transients (sharp changes in

Tup
the

h e r ea r e o f t e n
ick
re removed or
elements are r e m o
voltage inserted if the or current)
in a network
when
power is on. The transient
the
devic vice can handle, and theretore the levels can often be
than

are made.
power should always be off
nHore
changes when
rork
The maximum gate--to-source voltage is
normally
provided in the list of maximum
of the
device. One method of ensuring that this
ratings

ent
by transier
voltage is not exceeded (per-
effects) for either polarity is to introduce
two Zener diodes, as ?D
haps
41. The Zeners are back to back to
ensure
shown

1C hoth are 30-V Zeners and a positive transient protection for either
arity. of 40 V
polar fire at 30 V and the upper will turn on appears, the lower
with a zero-volt G
7encnsitive on" region of a semiconductor diode)
drop (ideally
across the other diode. The
for
ISa1aximum
of 30 V for the
result gate-to-source voltage. One disadvantage intro-
duced by the Zener ction is that the off resistance of a Zener diode is less than the
ncdance established by the Si0; layer. The result is a reduction in input
input
ance, but even so it is still high enough for most applications. So many of
resista.
the
afeerete devices now have the Lener protection that some of the concerns listed above
nOt as troublesome. However, it is still best to be somewhat cautious when han- Figure 5.41 Zener-protected
MOSFET devices. MOSFET.
dling discrete

5.10 VMOS
One of the disadvantages of the typical MOSFET is the reduced power-handling
levels (typically, less than 1 W) compared to BJT transistors. This short fall for a
device with so many positive characteristics can be softened by changing the con-
struction mode from one of a planar nature such as shown in Fig. 5.23 to one with
a

of the planar MOSFET

vertical structure as shown in Fig. 5.42. All the elements
are

vertical metal-oxide-silicon FET (VMOS)-the metallic surface con-

in the
present to
nection the terminals of the device-the Si02 layer between the gate and the p-type
induced n-channel (en-
region between the drain and source for the growth of the

Source teminals
externally connected

S
G

Si02
N
Effective length
of channel

(substrate)

Wider channel
Figure 5.42 VMOS construc
tion.
D

5.10 VMOS
 that the
to
the lact
vertical is due primarilyhorizontal
direction for
The term the
operation).
direction
rather than appearance of a v
nancement-mode the
formed in the
vertical also has
channel is now of Fig. 5.42 characteristic
for mental
the channel as a
device. However, stands out 5 . 4 2 1S somewhat
ne
planar base, which often
construction
of Fig.
cut in the
semiconductor
The but it does
of the
device. levels of doping,
of the name
the transition
memorization s o m e of
in leaving out
nature, facets of
its operation.
Simplistic
important voltage to the
of the most and a negative
permit a description to the drain s h o w n in Fig. 5.42
a positive
voltage level as
h e application of positive "on
with the gate at 0
V or s o m e typical
p-type region
of
the device. The
Source the narrow which can
induced n-channel in of the p-region,
wllresult in the defined by the vertical height construction. On a
of the channel is now using planar
ength less than that of
a channel
to 2
m i c r o m e t e r s (um)

limited to 1
De made significantly
the length of the
channel is
of Fig. 5.42)
can be con-
norizontal plane the p-region
channel lengths result in
as
(1 um = 10 m). Diffusion layers (such
Since decreasing
device (power lost in the
fractions of a micrometer.
rolled to small dissipation level of the
the contact area
the power
reducedresistance levels, current levels will be reduced. In addition, vertical
at operating mode
m hecat)
Ot
increased by the
Detween the channel and thent region is greatly resistance level
and an in-
to further decrease in the
Construction, contributing a existence of two
doping layers. There is also the
Creased area for current between the further contrib-
in Fig. 5.42, to
Conduction drain and source, as shown
paths between currents that can
result is a device with drain
ute to a higher current rating. The net
exceeding 10 W.
reach the ampere levels with power levels
In general:
MOSFETs, VMOS FETs have
Compared with commercially available planar
reduced channel resistance levels and higher current and power ratings.
An additional important characteristic of the vertical construction is:
VMOS FETs have a positive temperature cocfficient that will combat the pos-
sibility of thermal runaway
If the temperature of a device should increase due to the surrounding medium or
currents of the device, the resistance levels will increase, causing a reduction in drain
current rather than an increase as encountered for a conventional device. Negative
temperature coefficients result in decreased levels or resistance with increase in tem-
perature that fuel the growing current levels and result in further temperature instabil-
ity and thermal runaway.
A further positive characteristic of the VMOS
configuration is:
The reduced charge storage levels resul1 in faster
switching times for VMOS
construction compared those
for conventional planar construction.
to

In fact, VMOS devices typically have switching times less

than one-half that
encountered for the typical BJT transistor.

5.11 CMOS
A Very effective logic circuit can be established by
n-channel MOSFET on the same substrate as shownconstructing
in and an a
p-channel
n-channel on the left and the induced Fig. 5.43, Note the
n-channel
devices, respectively. The configuration is
on the right for the p- and
n-channel
arrangement, abbreviated CMOS, nat nasS reterred
to as a
complementary MOSFET
design, The relatively high input impedance,extensive applications in computer logic
e r levels of the CMOS 1ast switching speeds, and lower
configuration have operat-
resulted in a whole
referred to as CMOS logic design. new
discipline
tor 5 Field-Effect Transistors
 pos/V

G2 G
D

SiO,

When "on" Whe

Pchannel MOSFET
nchannel MOSPET
m-type substrate

CMOS with the connections indicated in Fig 544

Figure 5.43

One very effective use of the complementary arrangement is as an inverter, as

appearing in Fig. 5.44. As introduced for switching transistors,aninverter is a logic
clement that "inverts" the applied signal. That is, ifthe logic levels of operation are
result in an output level of
OV 0 state) and 5 V(l state). an input level of 0 V will
5V. and vice versa. Note in Fig. 5,44 that both gates are connected to the applied
MOSFET (22) is
signal and both drains to the output Vo. The source of the p-channel n-channel MOS-
connected directly to the applied voltage Vss while the source of the
FET (Q) is connected to ground. For the logic levels defined above. the application
0 V at the output. With 5 V at Vi
of 5 V at the input should result in approximately low
(with respect to ground), Vas, V; and Q1 is *on," resulting in a relatively
=

in Fig. .45. Since V; and Vss are at

resistance between drain and source as shown
in
less than the required Vy for the device resulting
an
5 V. Vos. 0 V, which isresistance
=

level between drain and source is quite high for

off state. The resulting of the voltage-divider rule will reveal
3. as shown in Fig. 5.45. A simple application the desired inversion process.
that V, is very close to 0 V or the 0 state, establishing
0 V and Qi will be off with Vss,
=

For an applied voltage V, of 0 V (0 state) Vos,

=

a small
MOSFET. The result is that Q2 will present
-5 V. turning on the p-channel
resistance level and Q a high
resistance and V. Vss =5 V (the 1 state). Since the
=

is limited by the "off" transistor to the leakage

drain curent that flows for either case low. Additional
the device in either state is very
value, the power dissipated by in Chapter 17.
comment on the application
of CMOS logic is presented

9ss=5 V

VG$2 Vss 5V

p-channel eakage
MOSFET
0 ,off R,high)

V,EOV RSS 0v (0-state)

-o R+R
(0-state)

on R,low)
n-channel
5V
MOSFET
(1-state)
Q1
VGS levels for
5.45 Relative resistance
Figure
V, 5V (1-state).
Figure 5.44 CMOS inverter. 241
5.11 CMOS
posP 5.12 SUMMARY TABLE
from one type of
c h a r a c t e r i s t i c s
vary
important
from o n e
differences
the
and s o m e display
transfer
curves
to clearly of the table
Since the
parameters
developed and
Table 5.2 w a s all the c u r v e s Chapters 6
FET to another, understanding
of to f o l l o w
in

A clear and ac analysis

device to the next. for the dc and their derivation
background is recognizable

w7llprovide a sufficient
that each
curve
levels of the important
to ensure of the
and 8. Take a
moment comparison
a basis for
establish
understood and then device.
parameters of R, and C, for each

Input Resistance
TABLE 5.2 Field Effect Transistors
and Capacitance
-Symbol- Transfer Curve

Basic Relattonships
Type
JFET
(7-channe)
pSS

l =0A,lp =s
R,>100MQ
D
DSS C: (1- 10) pF

4
S

0.3V 0 Vos
Iploss(1

MOSFET
depletion-type
(n-channel) lG=0A, Ip =!s
QD
pss
R,>10 Q
C:(1-10) pF

oVcs Vcs

MOSFET
enhancement-type IG = 0 A, lp =ls
(n-channel)
D

lpon) R,>10t0
C;(1- 10) pF
S
p =k(Vos-Vy?
k Dn)
(GSon)Vr VGS(on)

Chapter 5 Field-Effect Transistors

242